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dMazeRunner: Executing Perfectly Nested Loops on Dataflow Accelerators

ACM TRANSACTIONS ON EMBEDDED COMPUTING systems 2019年第5期18卷 70-70页

作者： Dave, Shail Kim, Youngbin Avancha, Sasikanth Lee, Kyoungwoo Shrivastava, Aviral Arizona State Univ Compiler Microarchitecture Lab Sch Comp Informat & Decis Syst Engn Tempe AZ 85281 USA Yonsei Univ Seoul South Korea Intel Labs Parallel Comp Lab Bangalore Karnataka India

Dataflow accelerators feature simplicity, programmability, and energy-efficiency and are visualized as a promising architecture for accelerating perfectly nested loops that dominate several important applications, including image and media processing and deep learning. Although numerous accelerator designs are being proposed, how to discover the most efficient way to execute the perfectly nested loop of an application onto computational and memory resources of a given dataflow accelerator (execution method) remains an essential and yet unsolved challenge. In this paper, we propose dMazeRunner - to efficiently and accurately explore the vast space of the different ways to spatiotemporally execute a perfectly nested loop on dataflow accelerators (execution methods). The novelty of dMazeRunner framework is in: i) a holistic representation of the loop nests, that can succinctly capture the various execution methods, ii) accurate energy and performance models that explicitly capture the computation and communication patterns, data movement, and data buffering of the different execution methods, and iii) drastic pruning of the vast search space by discarding invalid solutions and the solutions that lead to the same cost. Our experiments on various convolution layers (perfectly nested loops) of popular deep learning applications demonstrate that the solutions discovered by dMazeRunner are on average 9.16x better in Energy-Delay-Product (EDP) and 5.83x better in execution time, as compared to prior approaches. With additional pruning heuristics, dMazeRunner reduces the search time from days to seconds with a mere 2.56% increase in EDP, as compared to the optimal solution.

关键词： Coarse-grained reconfigurable array dataflow deep neural networks loop optimization energy-efficiency systolic arrays mapping analytical model design space exploration

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RiBoSOM: Rapid Bacterial Genome Identification Using Self-Organizing Map implemented on the Synchoros SiLago Platform 18

RiBoSOM: Rapid Bacterial Genome Identification Using Self-Or...

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18th International Conference on Embedded Computer systems - Architectures, Modeling, and Simulation (SAMOS)

作者： Yang, Yu Stathis, Dimitrios Sharma, Prashant Paul, Kolin Hemani, Ahmed Grabherr, Manfred Ahmad, Rafi Royal Inst Technol KTH Stockholm Sweden Indian Inst Technol Delhi Delhi India Uppsala Univ Uppsala Sweden Inland Norway Univ Appl Sci Hamar Norway

ISBN: (纸本)9781450364942

Artificial Neural Networks have been applied to many traditional machine learning applications in image and speech processing. More recently, ANNs have caught attention of the bioinformatics community for their ability to not only speed up by not having to assemble genomes but also work with imperfect data set with duplications. ANNs for bioinformatics also have the added attraction of better scaling for massive parallelism compared to traditional bioinformatics algorithms. In this paper, we have adapted Self-organizing Maps for rapid identification of bacterial genomes called BioSOM. BioSOM has been implemented on a design of two coarse grain reconfigurable fabrics customized for dense linear algebra and streaming scratchpad memory respectively. These fabrics are implemented in a novel synchoros VLSI design style that enables composition by abutment. The synchoricity empowers rapid and accurate synthesis from Matlab models to create near ASIC like efficient solution. This platform, called SiLago (Silicon Lego) is benchmarked against a GPU implementation. The SiLago mentation of BioSOMs in four different dimensions, 128, 256, 512 and 1024 Neurons, were trained for two E Coli strains of bacteria with 40K training vectors. The results of SiLago implementation were benchmarked against a GPU GTx 1070 implementation in the CUDA framework. The comparison reveals 4 to 140x speed up and 4 to 5 orders of improvement in energy-delay product compared to implementation on GPU. This extreme efficiency comes with the added benefit of automated generation of GDSii level design from Matlab by using the Synchoros VLSI design style.

关键词： Neural networks Self-Organizing Maps SiLago Synchoros VLSI Design parallel architecture 3D DRAM GPU

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High-rate Modeling and Computing for Optical systems: Gigapixel image Formation and x-ray imaging Physics

High-rate Modeling and Computing for Optical Systems: Gigapi...

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作者： Gong, Qian Duke University

学位级别：Ph.D.

With the rapid development of computational sensing technologies, the volume of available sensing data has been increasing daily as sensor systems grow in scale. This is sometimes referred to as the "data deluge". Many physical computing applications have to spend great effort on meeting the challenges of this environment, which has prompted a need for rapid and efficient processing of massive datasets. Fortunately, many algorithms used in these applications can be decomposed and partially or fully cast into a parallel computing framework. This dissertation discusses three sensing models—gigapixel image formation, x-ray transmission and x-ray scattering—and proposes methods to formulate each task as a scalable and distributed problem which is adapted to the massively parallel architecture of Graphics processing Units (GPUs). For the gigapixel images, this dissertation presents a scalable and flexible image formation pipeline based on the MapReduce framework. The presented implementation was developed to operate on the AWARE multiscale cameras, which consist of microcamera arrays imaging through a shared hemispherical objective. The microcamera field-of-views slightly overlap and are capable of generating high-resolution and high dynamic range panoramic images and videos. The proposed GPU implementation takes advantage of the prior knowledge regarding the alignment between microcameras and exploits the multiscale nature of the AWARE image acquisition, enabling the rapid composition of panoramas ranging from display-scale views to gigapixel-scale full resolution images. On a desktop computer, a 1.6-gigapixel color panorama captured by the AWARE-10 can be delivered in less than a minute, while 720p and 1080p panoramas can be stitched at the video frame rate. We next present a pipeline that rapidly simulates x-ray transmission imaging via ray-tracing on GPU. This pipeline was initially designed for statistical analysis of x-ray threat detection in the context of aviatio

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Making Halide Efficient for Multicore systems

Making Halide Efficient for Multicore Systems

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International Conference on Big Data Computing and Communications (BIGCOM)

作者： Yu Zhang Yuxiang Zhang School of Computer Science and Technology University of Science and Technology of China China

Graphics and imaging applications, especially emerging medical imaging or self-driving cars, demand orders of magnitude more computation, and require efficient image processing pipeline implementations. Halide is domain-specific language and compiler designed to make it easier write high performance image processing code. It separates what is being computed from how to compute, enabling programmers to tune to find a high performance schedule. However, Halide applications suffer poor scalability on large number of CPU cores. In this paper, we first perform a detailed parallelism and performance analysis of Halide applications on a 4x8-physical core Linux system. Our analysis shows that page faults and contention on shared address space as well as unaligned packed data movements are part of reasons for poor scalability. To improve the performance of Halide, we propose a novel thread model-Sthread-and adopt it to reimplement Halide runtime, i.e. Shalide, without modifying the Halide language, compiler and the runtime interface. The Sthread model allows each thread has its own memory management structure, and directly shares heap objects, globals and stack data with other threads. On six image processing benchmarks, Shalide shows better speedup and gives up to 1.53x faster than the original Halide.

关键词： Benchmark testing Schedules Task analysis image processing parallel processing Instruction sets Scalability

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OPTRONIC HIGH-RESOLUTION SAR processing WITH THE CAPABILITY OF FULL-RESOLUTION imaging

OPTRONIC HIGH-RESOLUTION SAR PROCESSING WITH THE CAPABILITY ...

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IEEE International Geoscience and Remote Sensing Symposium

作者： Lei Liu Yesheng Gao xingzhao Liu Department of Electronic Engineering Shanghai Jiao Tong University China

The improvement of synthetic aperture radar (SAR) resolution brings a broader applications but poses a great burden for SAR data processor. Real-time processing becomes a difficulty. Optronic technology has been developed for SAR real-time processing due to its ultrafast processing speed. A novel real-time optronic high-resolution SAR processor is proposed in this paper. It has the capability of full-resolution imaging. Restricted with the data scale of spatial light modulators (SLMs), SAR raw data cannot be all encoded onto the light beams at a time. To solve this, subaperture architecture is introduced in our system scheme. SAR data is optically processed in parallel by multiple optical subaperture processing modules and synthesized into a full-resolution SAR image. The module is implemented by multiple SLMs and lenses, which is innovatively proposed in this paper. The proposed system is applicable to large-scale SAR data processing, and the data scale is easy to extend with implementation of adding identical optical subaperture processing modules. Airborne SAR real data is used in the experiment, and a high-resolution image is also given. The PSLR of the focus results with and without subaperture partition are analyzed, which validates the satisfying image quality of the proposed algorithm.

关键词： Synthetic aperture radar Optical imaging Partitioning algorithms Azimuth Adaptive optics Real-time systems

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Real-time computation of parameter fitting and image reconstruction using graphical processing units

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COMPUTER PHYSICS COMMUNICATIONS 2017年 215卷 71-80页

作者： Locans, Uldis Adelmann, Andreas Suter, Andreas Fischer, Jannis Lustermann, Werner Dissertori, Gunther Wang, Qiulin Paul Scherrer Inst CH-5232 Villigen Switzerland ETH Inst Teilchenphys CH-8092 Zurich Switzerland Univ Latvia 19 Raina Blvd LV-1586 Riga Latvia Tsinghua Univ Inst Med Phys Beijing Peoples R China

In recent years graphical processing units (GPUs) have become a powerful tool in scientific computing. Their potential to speed up highly parallel applications brings the power of high performance computing to a wider range of users. However, programming these devices and integrating their use in existing applications is still a challenging task. In this paper we examined the potential of GPUs for two different applications. The first application, created at Paul Scherrer Institut (PSI), is used for parameter fitting during data analysis of mu SR (muon spin rotation, relaxation and resonance) experiments. The second application, developed at ETH, is used for PET (Positron Emission Tomography) image reconstruction and analysis. applications currently in use were examined to identify parts of the algorithms in need of optimization. Efficient GPU kernels were created in order to allow applications to use a GPU, to speed up the previously identified parts. Benchmarking tests were performed in order to measure the achieved speedup. During this work, we focused on single GPU systems to show that real time data analysis of these problems can be achieved without the need for large computing clusters. The results show that the currently used application for parameter fitting, which uses OpenMP to parallelize calculations over multiple CPU cores, can be accelerated around 40 times through the use of a GPU. The speedup may vary depending on the size and complexity of the problem. For PET image analysis, the obtained speedups of the GPU version were more than x40 larger compared to a single core CPU implementation. The achieved results show that it is possible to improve the execution time by orders of magnitude. (C) 2017 Elsevier B.V. All rights reserved.

关键词： GPU CUDA Musrfit PET image reconstruction

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In-database batch and query-time inference over probabilistic graphical models using UDA-GIST

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VLDB JOURNAL 2017年第2期26卷 177-201页

作者： Li, Kun Zhou, xiaofeng Wang, Daisy Zhe Grant, Christan Dobra, Alin Dudley, Christopher Univ Florida Dept Comp & Informat Sci & Engn Gainesville FL 32611 USA Univ Oklahoma Sch Comp Sci Norman OK 73019 USA

To meet customers pressing demands, enterprise database vendors have been pushing advanced analytical techniques into databases. Most major DBMSes use user-defined aggregates (UDAs), a data-driven operator, to implement analytical techniques in parallel. However, UDAs alone are not sufficient to implement statistical algorithms where most of the work is performed by iterative transitions over a large state that cannot be naively partitioned due to data dependency. Typically, this type of statistical algorithm requires pre-processing to set up the large state in the first place and demands post-processing after the statistical inference. This paper presents general iterative state transition (GIST), a new database operator for parallel iterative state transitions over large states. GIST receives a state constructed by a UDA and then performs rounds of transitions on the state until it converges. A final UDA performs post-processing and result extraction. We argue that the combination of UDA and GIST (UDA-GIST) unifies data-parallel and state-parallel processing in a single system, thus significantly extending the analytical capabilities of DBMSes. We exemplify the framework through two high-profile batch applications: cross-document coreference, image denoising and one query-time inference application: marginal inference queries over probabilistic knowledge graphs. The 3 applications use probabilistic graphical models, which encode complex relationships of different variables and are powerful for a wide range of problems. We show that the in-database framework allows us to tackle a 27 times larger problem than a scalable distributed solution for the first application and achieves 43 times speedup over the state-of-the-art for the second application. For the third application, we implement query-time inference using the UDA-GIST framework and apply over a probabilistic knowledge graph, achieving 10 times speedup over sequential inference. To the best of our knowledge,

关键词： In-database analytics Query-time inference Batch inference Data-parallel analytics Graph-parallel analytics

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Development of an Embedded Atmospheric Turbulence Mitigation Engine 2

Development of an Embedded Atmospheric Turbulence Mitigation...

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Conference on Long-Range imaging ii

作者： Paolini, Aaron Bonnett, James Kozacik, Stephen Kelmelis, Eric EM Photon Inc 51 East Main StSuite 203 Newark DE 19711 USA Univ Delaware Dept Elect & Comp Engn 140 Evans Hall Newark DE 19716 USA

ISBN: (数字)9781510609105

ISBN: (纸本)9781510609099;9781510609105

Methods to reconstruct pictures from imagery degraded by atmospheric turbulence have been under development for decades. The techniques were initially developed for observing astronomical phenomena from the Earth's surface, but have more recently been modified for ground and air surveillance scenarios. Such applications can impose significant constraints on deployment options because they both increase the computational complexity of the algorithms themselves and often dictate a requirement for low size, weight, and power (SWaP) form factors. Consequently, embedded implementations must be developed that can perform the necessary computations on low-SWaP platforms. Fortunately, there is an emerging class of embedded processors driven by the mobile and ubiquitous computing industries. We have leveraged these processors to develop embedded versions of the core atmospheric correction engine found in our ATCOM software. In this paper, we will present our experience adapting our algorithms for embedded systems on a chip (SoCs), namely the NVIDIA Tegra that couples general-purpose ARM cores with their graphics processing unit (GPU) technology and the xilinx Zynq which pairs similar ARM cores with their field-programmable gate array (FPGA) fabric.

关键词： Atmospheric Turbulence Turbulence Mitigation Atmospheric Compensation image processing LongRange imagery image Enhancement Real-Time Embedded

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A review of GPU-based medical image reconstruction

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PHYSICA MEDICA-EUROPEAN JOURNAL OF MEDICAL PHYSICS 2017年 42卷 76-92页

作者： Despres, Philippe Jia, xun Univ Laval Dept Phys Genie Phys & Opt 1045 Ave Med Quebec City PQ G1V 0A6 Canada Univ Texas Southwestern Med Ctr Dallas Dept Radiat Oncol 2280 Inwood RdMC 9303 Dallas TX 75390 USA Univ Laval CHU Quebec Dept Radiooncol 11 Cote Palais Quebec City PQ G1R 2J6 Canada

Tomographic image reconstruction is a computationally demanding task, even more so when advanced models are used to describe a more complete and accurate picture of the image formation process. Such advanced modeling and reconstruction algorithms can lead to better images, often with less dose, but at the price of long calculation times that are hardly compatible with clinical workflows. Fortunately, reconstruction tasks can often be executed advantageously on Graphics processing Units (GPUs), which are exploited as massively parallel computational engines. This review paper focuses on recent developments made in GPU-based medical image reconstruction, from a CT, PET, SPECT, MRI and US perspective. Strategies and approaches to get the most out of GPUs in image reconstruction are presented as well as innovative applications arising from an increased computing capacity. The future of GPU-based image reconstruction is also envisioned, based on current trends in high-performance computing. (C) 2017 Associazione Italiana di Fisica Medica. Published by Elsevier Ltd. All rights reserved.

关键词： Tomographic reconstruction Medical imaging Graphics processing Unit (GPU)

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In-pixel ADC in 3D technology 15

In-pixel ADC in 3D technology

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15th IEEE International New Circuits and systems Conference (NEWCAS)

作者： Brochard, Nicolas Ginhac, Dominique Univ Bourgogne Franche Comte Le2i CNRS Arts & Metiers F-21000 Dijon France

ISBN: (纸本)9781509049912

Decreasing size of CMOS technology plays a key role in embedding more and more functionalities in CMOS image sensors. By integrating sensing with processing, new types of CMOS imaging systems can be designed and applied in domains such as machine vision, surveillance, or medical imaging. Digital pixel sensors (DPSs) are a good example of smart vision chips including image capturing and processing modules. Indeed, they incorporate, for each pixel, parallel analog-to-digital conversion thus allowing performing such conversion in early stages. Moreover, DPSs offer several benefits such as an improved SNR (Signal Noise Ratio) and a wider dynamic range. In addition, the emergence of new technologies, typically CMOS 3D-IC technology, offers the opportunity to reduce pixel area and improve fill factor, making DPSs suitable for numerous fields of applications. This paper presents a digital pixel sensor (DPS) integrating an in-pixel sigma-delta analog-to-digital converter (ADC). The digital pixel includes a photodiode, a delta-sigma modulation and a digital decimation filter, featuring high-speed conversion, programmable resolutions (up to 10-bit). Based on the CMOS 130 nm 3D-IC Tezzaron technology, an optimized design of the pixel is provided, revealing a high fill-factor of about 90%.

关键词： Estimation Field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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