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IEEE Aerospace Conference

作者： Stackler, Marc Glascott-Jones, Andrew Chantier, Nicolas E2v Semicond Ave Rochepl F-38521 St Egreve France

ISBN: (纸本)9781479953806

Ultra high speed data converters have applications ranging from data acquisition systems, radar, satellite and terrestrial communications and radio astronomy telescopes. The latest data converters offer signal bandwidths of up to 7GHz along with sample rates at 5GSps and more. This capability means that efficient and flexible wideband data transmission system for high data producing hardware, such as imaging cameras, can be designed and constructed. This system could be easily extended to use on assets requiring encrypted data transfer, such as UAVs. This paper describes a system design which uses a 12 bits 3GSps DAC from e2v (EV12DS130A) as the transmitting element and a 10 bits Quad 1.25 GSps ADC (EV10AQ190A) in 3GSps single channel configuration as the receiving element. The transmission is based on a 256-QAM. The processing is done by a Stratix ii FPGA from Altera on the transmitter end;the receiver is based on a Virtex 6 FPGA from xilinx. A transmission system based on a parallel architecture for the software was developed which can reach data rates up to 6Gbps. The modulation processing consists of 8 QAM256 modulators in parallel using NCO (Numerically Controlled Oscillator) as sine wave generators and LVDS transmitters to interface the FPGA and the DAC. The reception stage also interfaces ADC and FPGA through LVDS receivers and uses a multi-stage correlation method to demodulate the data. In this paper, the choice of modulation standard will be discussed along with the architecture of the scheme adopted. Finally demonstration of test results using various data patterns will be presented. The extension of this technique to communication standards like DOCSIS (Data Over Cable Service Interface Specification) is also considered along with the use of frequency hopping encryption.

关键词： Data Over Cable Service Interface Specification Transmission systems direct conversion data converters Communication standards high speed transmission DATA ACQUISITION systems parallel architectures radio astronomy

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Ultra-Low Power Render-Based Collision Detection for CPU/GPU systems 48

Ultra-Low Power Render-Based Collision Detection for CPU/GPU...

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48th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO)

作者： de Lucas, Enrique Marcuello, Pedro Parcerisa, Joan-Manuel Gonzalez, Antonio Univ Politecn Cataluna Comp Architecture Dept Barcelona Spain Broadcom Corp Barcelona Spain

ISBN: (纸本)9781450340342

Smartphones have become powerful computing systems able to carry out complex tasks, such as web browsing, image processing and gaming, among others. Graphics animation applications such as 3D games represent a large percentage of downloaded applications for mobile devices and the trend is towards more complex and realistic scenes with accurate 3D physics simulations, like those in laptops and desktops. Collision detection (CD) is one of the main algorithms used in any physics kernel. However, real-time highly accurate CD is very expensive in terms of energy consumption and this parameter is of paramount importance for mobile devices since it has a direct effect on the autonomy of the system. In this work, we propose an energy-efficient, high-fidelity CD scheme that leverages some intermediate results of the rendering pipeline. It also adds a new and simple hardware block to the GPU pipeline that works in parallel with it and completes the remaining parts of the CD task with extremely low power consumption and more speed than traditional schemes. Using commercial Android applications, we show that our scheme reduces the energy consumption of the CD by 99.8% (i.e., 448 x times smaller) on average. Furthermore, the execution time required for CD in our scheme is almost three orders of magnitude smaller (600 x speedup) than the time required by a conventional technique executed in a CPU. These dramatic benefits are accompanied by a higher fidelity CD analysis (i.e., with finer granularity), which improves the quality and realism of the application.

关键词： Mobile GPU Rendering image Based Collision Detection

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Embedded system of the iris segmentation module

Embedded system of the iris segmentation module

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International Conference on Modelling, Identification and Control (ICMIC)

作者： Khaoula Mannay Yassine Aoudni Mohamed Abid Electrical department Computer Embedded System Laboratory National school of Engineers of Sfax Tunisia

Iris Recognition is one of the important biometric recognition systems that identify people based on their eyes and iris. Most modern systems are currently deployed on traditional sequential digital systems, such as a computer. However, modern advancements in reconfigurable hardware, most FPGAs (Field-Programmable Gate Arrays) have provided an exciting opportunity to discover the parallel nature of modern image processing algorithms. So that, many authentication applications can be carried out by portable devices. In this paper, we implement the new version C of the iris segmentation [1], which is developed from the Osiris system, in a Cyclone ii FPGA DE2_70 FPGA. In the first step, as a software application using Nios ii, In the second step, as a hardware-software application using Quartus ii and SOPc Builder to accelerate the time processing, after the use of Hardware accelerators. The results show that with a clock speed of 50MHZ from image of 640*480, the gain in the time execution is 768 ms, from the total time needed by the software solution running on the same embedded microprocessor in the architecture.

关键词： Iris recognition Hardware Field programmable gate arrays Software image segmentation Computer architecture Pattern recognition

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image-Optimized Rolling Cache: Reducing the Miss Penalty for Memory-Intensive Vision algorithms

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IEEE TRANSACTIONS ON CIRCUITS AND systems FOR VIDEO TECHNOLOGY 2014年第3期24卷 539-551页

作者： Kim, Young-Geun Kweon, In-So Korea Adv Inst Sci & Technol Taejon 305701 South Korea

In real-time memory-intensive image processing and vision applications, increasing image resolution requires the use of external SDR/DDR memories. However, the arbitrary pixel access patterns used in most algorithms reduce their memory throughput as a result of increasing access latency. Efficient cache design is paramount in real-time memory-intensive applications. Its effectiveness depends on the spatial and temporal locality of data access. In image processing, the spatial locality denotes the neighboring pixels, located horizontally and vertically in 2-D. However, the conventional caches used in general processors cannot define the vertical locality. We propose a rolling cache optimized for image format and algorithms, a method to reduce the miss penalty by moving the cache horizontally and vertically, and a parallel processing architecture with interpolation, multilevel and multiple caches. To support our idea, we compare it with other types of caches and show that the average memory access time and the memory bandwidth are decreased by 28% and 74%, respectively, for a 2048x2048 image. Its performance is greater than that of the 16-way set associative cache, but the tag memory size is a bit larger than that of the direct-mapped cache. Using two different applications, we show that the proposed architecture is applicable to a number of algorithms if data access follows an arbitrary curve or block-wise pattern, which is the usual case with image processing and vision algorithms. If an application is based on local data access in resource-limited systems, it is possible to achieve high performance with lower operational frequency using the proposed architecture.

关键词： Cache computer vision high performance system homogeneous transformation image processing interpolation object tracking pipelined architecture rolling cache

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High-accuracy hierarchical parallel technique for hidden Markov model-based 3D magnetic resonance image brain segmentation

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CONCURRENCY AND COMPUTATION-PRACTICE & ExPERIENCE 2014年第1期26卷 194-216页

作者： El-Moursy, Ali A. ElAzhary, Hanan Younis, Akmal Univ Sharjah Sharjah U Arab Emirates Elecron Res Inst Giza Egypt Univ Miami Dept Elect & Comp Engn Miami FL USA

Scientific applications represent a dominant sector of compute-intensive applications. Using massively parallel processing systems increases the feasibility to automate such applications because of the cooperation among multiple processors to perform the designated task. This paper proposes a parallel hidden Markov model (HMM) algorithm for 3D magnetic resonance image brain segmentation using two approaches. In the first approach, a hierarchical/multilevel parallel technique is used to achieve high performance for the running algorithm. This approach can speed up the computation process up to 7.8x compared with a serial run. The second approach is orthogonal to the first and tries to help in obtaining a minimum error for 3D magnetic resonance image brain segmentation using multiple processes with different randomization paths for cooperative fast minimum error convergence. This approach achieves minimum error level for HMM training not achievable by the serial HMM training on a single node. Then both approaches are combined to achieve both high accuracy and high performance simultaneously. For 768 processing nodes of a Blue Gene system, the combined approach, which uses both methods cooperatively, can achieve high-accuracy HMM parameters with 98% of the error level and 2.6x speedup compared with the pure accuracy-oriented approach alone. Copyright (c) 2012 John Wiley & Sons, Ltd.

关键词： massively parallel processing parallel algorithms performance analysis medical image processing

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Research on Calibration Method of The Panoramic Stereo Sphere Vision System

Research on Calibration Method of The Panoramic Stereo Spher...

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IEEE International Conference on Mechatronics and Automation

作者： Junchao Zhu Yongchen Li Chang Liu Zhijun Ma Baofeng Zhang Tianjin Key Laboratory for Control Theory and Applications in Complicated Systems Tianjin University of Technology 391 Binshui Xidao Xiqing District Tianjin 300384 China School of Electrical Engineering Tianjin University of Technology 391 Binshui Xidao Xiqing District Tianjin 300384 China

ISBN: (纸本)9781479970995

Panoramic stereo spherical vision system can simultaneously realize panoramic stitching and three-dimensional ranging. Its multi-channel image acquisition system is located in 3D space through the mechanical encapsulation. In this paper, an effective calibration method is explored to solve the problem of slight errors generated by the encapsulation structure installation and manufacturing. More importantly, the errors are difficult to measure, which leads the optical axes of lenses are not parallel. This paper uses a fine-tuning method of focused laser spot detection to solve the problem by analyzing the encapsulation structure and imaging model of the system. And its image processing algorithms and calibration process are described. The final experimental results confirm it is indeed feasible to this method.

关键词： Panoramic Stereo Sphere Vision Camera Calibration image processing

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ARC 2014: Towards a Fast FPGA Implementation of a Heap-Based Priority Queue for image Coding Using a parallel Index-Aware Tree

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ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND systems 2015年第1期9卷 8-8页

作者： Bai, Yuhui Ahmed, Syed Zahid Granado, Bertrand Univ Cergy Pontoise ENSEA UMR CNRS 8051 ETIS Cergy France Univ Paris 06 Sorbonne Univ UMR7606 LIP6 F-75005 Paris France

The embedded image processing systems like smartphones and digital cameras have tight limits on storage, computation power, network connectivity, and battery usage. These limitations make it important to ensure efficient image coding. In the article, we present a novel heap-based priority queue structure employed by an Adaptive Scanning of Wavelet Data scheme (ASWD) targeting an embedded platform. ASWD is a context modeling block implemented via priority queues in a wavelet-based image coder to reorganize the wavelet coefficients into locally stationary sequences. The architecture we propose exploits efficient use of FPGA's on-chip dual-port memories in an adaptive manner. Innovations of index-aware system linked to each element in the queue makes the location of queue element traceable in the heap as per the requirements of the ASWD algorithm. Moreover, use of 4-port memories along with intelligent data concatenation of queue elements yielded in a cost effective enhanced memory access. The memory ports are adaptively assigned to different units during different processing phases in a manner to optimally take advantage of memory access required by that phase. The architectural innovations can also be exploited in other applications that require efficient hardware implementations of generic priority queue or classical sorting applications which sort into the index. We designed and validated the hardware on an Altera's Stratix IV FPGA as an IP accelerator in a Nios ii processor based System on Chip. We show that our architecture at 150MHz can provide 45x speedup compared to an embedded ARM Cortex-A9 processor at 666MHz targeting the throughput of 10MB/s.

关键词： Design Experimentation Performance image compression adaptive scanning priority queue heapsort system-on-chip embedded system FPGA

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Optical image processing for synthetic-aperture imaging ladar based on two-dimensional Fourier transform

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APPLIED OPTICS 2014年第9期53卷 1846-1855页

作者： Sun, Zhiwei Hou, Peipei Zhi, Ya'nan Sun, Jianfeng Zhou, Yu xu, Qian Lu, Zhiyong Liu, Liren Chinese Acad Sci Shanghai Inst Opt & Fine Mech CAS Key Lab Space Laser Commun & Detect Technol Shanghai 201800 Peoples R China

A two-dimensional (2D) Fourier transform algorithm for the image reconstruction of synthetic-aperture imaging ladar (SAIL) collected data is suggested. This algorithm consists of quadratic phase compensation in azimuth direction and 2D fast Fourier transform. Based on this algorithm and the parallel 2D Fourier transform capability of spherical lens, an optical principle scheme that processes the SAIL data is proposed. The basic principle, design equations, and necessary analysis are presented. To verify this principle scheme, an experimental optical SAIL processor setup is constructed. The imaging results of SAIL data obtained by our SAIL demonstrator are presented. The optical processor is compact, lightweight, and consumes low power. This optical processor can also provide inherent parallel and speed-of-light computing capability, and thus has potential applications in on-board and satellite-borne SAIL systems. (C) 2014 Optical Society of America

关键词： Fast Fourier transforms image processing image quality image reconstruction Liquid crystal modulators Optical processing devices

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Hardware Accelerator for Fast image/Video Thinning

Hardware Accelerator for Fast Image/Video Thinning

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IEEE International Conference on imaging systems and Techniques (IST) / IEEE International School on imaging

作者： Davalle, Daniele Carnevale, Berardino Saponara, Sergio Fanucci, Luca Terreni, Pierangelo Univ Pisa Dept Informat Engn Via G Caruso 16 I-56122 Pisa Italy

ISBN: (纸本)9781479952205

image thinning algorithms are widely used in image processing to simplify elaboration preserving geometrical features. Standard approaches are based on iterative methods and on distance transforms. Both techniques are well known to be computationally intensive. In this work we propose a parallel, fast and flexible hardware architecture for image thinning to achieve real-time performance. The test case is the 720 x 576 PAL standard video at 25 frame per second (fps). Synthesis was performed for a Stratix ii FPGA EP2S30 and for a standard cell 65 nm CMOS technology. The former showed a usage of 4 % slices and 1 % registers, the latter gave an occupation of 5 kgates for the processing core. The execution time for one frame was 0.03 s on the FPGA and 0.009 s on the 65 nm, resulting in a maximum throughput of 33 fps and 111 fps, respectively.

关键词： CMOS integrated circuits field programmable gate arrays image thinning iterative methods transforms video signal processing CMOS technology PAL standard video Stratix ii FPGA EP2S30 distance transforms geometrical feature preservation hardware accelerator image processing size 65 nm video thinning Algorithm design and analysis Computer architecture Field programmable gate arrays Hardware image segmentation Random access memory Standards image thinning Field programmable gate arrays iterative methods hardware accelerator distance transform Algorithm design and analysis CMOS technology random access machine Computer Architecture Video signal processing CMOS integrated circuits image processing image segmentation Computer hardware Transform

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HNCP-ii: A 16-core 65nm microprocessor ASIC for image processing algorithms

HNCP-II: A 16-core 65nm microprocessor ASIC for image proces...

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9th International Symposium on Reconfigurable and Communication-Centric systems-on-Chip (ReCoSoC)

作者： Boussadi, Mohamed Amine Tixier, Thierry Landrault, Alexis Derutin, Jean-Pierre Inst Pascal UMR 6602 CNRS UBP IFMA F-63171 Aubiere France

ISBN: (纸本)9781479958108

In many video and image processing applications, complexity has reached a point where the performance requirements can no longer be supported by standard architectures based on a single processor. This is why many systems are based on multiprocessor architecture. In this paper, we present HNCP-ii a 16-core flexible distributed memory ASIC dedicated to embedded application field (image processing applications). Connected through a torus on-chip network, each tile of the overall system includes an open-source RISC processor, a floating point unit, a video management module and a set of built in hardware features for multicore communication. This specific hardware enables to meet most relevant overall parallelism scheme (parallel skeletons) thanks to software-configurable modules. Results are presented for two image processing algorithms in term of execution time, speedup and efficiency. Area, power and timing performance of the synthesized ASIC are given for a CMOS 65nm technology node.

关键词： image processing algorithm network-on-chip application specific integrated circuits ASIC Uniprocessor Tile toruses macroprocessor MULTIPROCESSOR ARCHITECTURE

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