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5th International Symposium on Photoelectronic Detection and imaging (ISPDI) - imaging Sensors and applications

作者： Yang, Jie Shi, Cong Long, xitian Wu, Nanjian Chinese Acad Sci Inst Semicond State Key Lab Superlattices & Microstruct Beijing 100083 Peoples R China

ISBN: (纸本)9780819497772

In this paper we present a programmable computational image sensor for high-speed vision. This computational image sensor contains four main blocks: an image pixel array, a massively parallel processing element (PE) array, a row processor (RP) array and a RISC core. The pixel-parallel PE is responsible for transferring, storing and processing image raw data in a SIMD fashion with its own programming language. The RPs are one dimensional array of simplified RISC cores, it can carry out complex arithmetic and logic operations. The PE array and RP array can finish great amount of computation with few instruction cycles and therefore satisfy the low- and middle-level high-speed image processing requirement. The RISC core controls the whole system operation and finishes some high-level image processing algorithms. We utilize a simplified AHB bus as the system bus to connect our major components. Programming language and corresponding tool chain for this computational image sensor are also developed.

关键词： Computational image sensor high-speed image processing SIMD PE

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Efficient algorithm for the temporal and spatial based calculation of speckle contrast

Efficient algorithm for the temporal and spatial based calcu...

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Conference on Novel Biophotonic Techniques and applications ii (NBTA)

作者： Steimers, A. Farnung, W. Kohl-Bareis, M. Univ Appl Sci Koblenz D-53424 Remagen Germany

ISBN: (纸本)9780819496508

We demonstrate an efficient algorithm for the temporal and spatial based calculation of the laser speckle contrast analysis (LASCA) for the imaging of blood flow that reduces the numerical complexity of necessary calculations, facilitates a multi-core implementation of the speckle analysis and enables an independence of temporal or spatial resolution and SNR. The new algorithm was evaluated for both spatial and temporal based analysis of speckle patterns with different image sizes and incorporated pixels as sequential and multi-core code. The improvement is about a factor of 5 and can be increased to about a factor of 15 for multi-core computers. This allows an online-analysis of larger speckle images or at a higher frame rate.

关键词： Speckle imaging speckle spectroscopy parallel processing digital image processing high-resolution spectroscopy multi-frame image processing laser speckle contrast analysis blood flow perfusion imaging

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Autofocusing in microscopy systems using graphics processing units

Autofocusing in microscopy systems using graphics processing...

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Conference on applications of Digital image processing xxxVI

作者： Valdiviezo-N, Juan C. Hernandez-Tapia, Jorge Mera-Gonzalez, Laura Toxqui-Quitl, Carina Padilla-Vivanco, Alfonso Univ Politecn Tulancingo Div Ingn Hidalgo 43629 Mexico

ISBN: (纸本)9780819497062

Autofocus is of fundamental importance for a real time automatic system. In many microscopy applications, a desired automatic system should provide the best focused image with enough accuracy and the least computation time. During the last years, several metrics based on images have been proposed for the autofocus process. Although many of these techniques present good results, their main limitations reside in the high computation time. Recently, the development of graphics processing units (GPUs) has given place to new scientific applications oriented to diminish the computational effort of the central processing unit (CPU). This manuscript presents the parallel implementation of eight different autofocus algorithms using GPUs for microscopy applications. The main objective of the proposed manuscript is to demonstrate that the use of GPUs can speed up the computational time required to perform the mentioned techniques. The reduction of computation time achieved with the proposed implementation suggests that graphics processing units can effectively be used for autofocus in real time microscopy.

关键词： Autofocusing microscopy images GPU parallel computing

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Realtime parallel back-projection algorithm for three-dimensional optoacoustic imaging devices

Realtime parallel back-projection algorithm for three-dimens...

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Conference on Opto-Acoustic Methods and applications

作者： Ozbek, Ali Dean-Ben, x. L. Razansky, Daniel Tech Univ Munich Inst Biol & Med Imaging Ingolstadter Landstr 1 D-85764 Neuherberg Germany

ISBN: (纸本)9780819496492

Back-projection algorithms are probably the fastest approach to reconstruct an image from a set of optoacoustic (photoacoustic) data set. However, standard implementations of back-projection formulae are still not adequate for real-time (greater than 5 frames per second) visualization of three-dimensional structures. This is due to the fact that the number of voxels one needs to reconstruct in three-dimensions is orders of magnitude larger than the number of pixels in two dimensions. Herein we describe a parallel implementation of optoacoustic signal processing and back-projection reconstruction in an attempt to achieve real-time visualization of structures with three-dimensional optoacoustic tomographic systems. For this purpose, the parallel computation power of a graphics processing unit (GPU) is utilized. The GPU is programmed with OpenCL, a programming language for heterogenous platforms. We showcase that with the implementation suggested in this work imaging at frame rates up to 50 high-resolution three-dimensional images per second is achievable.

关键词： Optoacoustic tomography photoacoustic tomography parallel back-projection algorithm GPU acceleration

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A new space digital signal processor design

Lecture Notes in Electrical Engineering

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Lecture Notes in Electrical Engineering 2014年 289卷 51-60页

作者： Donati, Massimiliano Saponara, Sergio Fanucci, Luca Errico, Walter Colonna, Annamaria Piscopiello, Giuseppe Tuccio, Giovanni Bigongiari, Franco Odendahl, Maximilian Leupers, Rainer Spada, Antonio Pii, Vincenzo Cordiviola, Elena Nuzzolo, Francesco Reiter, Frederic Department of Information Engineering University of Pisa via Caruso 16 Pisa56120 Italy Consorzio Pisa Ricerche SCARL Corso Italia 116 Pisa56120 Italy SITAEL spa via Livornase 1019 Pisa56122 Italy Institute for Communication Technologies and Embedded Systems RWTH Aachen University Sommerfeldstraße 24 Aachen52074 Germany INTECS spa Polo Attività Montacchiello via Forti Trav. A5 Pisa56121 Italy Space Applications Services NV Leuvensesteenweg 325 Zaventem1932 Belgium

ISBN: (纸本)9783319043692

The increasing demand of on-board real-time processing represents one of the critical issues in forthcoming scientific and commercial European space missions. Faster and faster signal and image processing algorithms are required to accomplish planetary observation, surveillance, Synthetic Aperture Radar imaging and telecommunications, especially due to the importance of elaborate the sensing data before sending them to the Earth, in order to exploit effectively the bandwidth to the ground station. The only available space-qualified Digital Signal Processor (DSP) free of International Traffic in Arms Regulations restrictions (ATMEL TSC21020) faces a poor performance of 60 MFLOPs peak, and it is becoming inadequate to fulfill the computation demand of the space missions. For this reason, the development of a new generation of space-qualified DSP is well known in the European space community. The space-qualified DSP architecture proposed in this work fills the gap between the computational requirements and the available devices. Additionally, it has been implemented using technologies available in Europe without any restriction. The DSP processor leverages a pipelined and massively parallel core based on the Very Long Instruction Word paradigm, with 64 registers and 8 operational units. The rest of the System-on-Chip architecture consists in the instruction and the data cache memories, the memory controllers and two SpaceWire interfaces. The processor, implemented in CMOS 65 nm technology, reaches an operational frequency of 120 MHz and area occupation of around 350 Kgates. The correlated SoftwareDevelopment Environment (SDE), with compiler, assembler, linker, debugger and instruction-level simulator, allows for an easy programming of the device in C language. © Springer International Publishing Switzerland 2014.

关键词： Digital signal processors

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Achieving the image interpolation algorithm on The FPGA platform based on ImpulseC

Achieving the image interpolation algorithm on The FPGA plat...

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8th Symposium on Multispectral image processing and Pattern Recognition (MIPPR) - parallel processing of images and Optimization and Medical imaging processing

作者： Jia, Ge Peng, xianrong Chinese Acad Sci Inst Opt & Elect Beijing Sichuan Provinc Peoples R China

ISBN: (纸本)9780819498052

ImpulseC is based on the C language which can describe highly parallel and multi-process applications. It also generates a underlying hardware description for the dedicated process. To improve the famous bi-cubic interpolation algorithm, we design the bi-cubic convolution template algorithms with better computing performance and higher efficiency. The results of simulation show that the interpolation method not only improves the interpolation accuracy and image quality, but also preferably retains the texture of the image. Based on ImpulseC hardware design tools, we can make use of the compiler features to further parallelize the algorithm so that it is more conducive to the hardware implementation. Based on the xilinx Spartan3 of xC3S4000 chip, our method achieves the real-time interpolation at the rate of 50fps. The FPGA experimental results show that the stream of output images after interpolation is robust and real-time. The summary shows that the allocation of hardware resources is reasonable. Compared with the existing hand-written HDL code, it has the advantages of parallel speedup. Our method provides a novel idea from C to FPGA-based embedded hardware system for software engineers.

关键词： ImpulseC image interpolation bi-cubic convolution FPGA

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Carotid Artery Phantom Designment and Simulation using Field ii

Carotid Artery Phantom Designment and Simulation using Field...

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8th Symposium on Multispectral image processing and Pattern Recognition (MIPPR) - parallel processing of images and Optimization and Medical imaging processing

作者： Lin, Yuan Yang, xin Ding, Mingyue Huazhong Univ Sci & Technol Image Proc & Intelligence Control Key Lab Educ Minist China Dept Biomed EngnColl Life Sci & Technol Wuhan 430074 Peoples R China

ISBN: (纸本)9780819498052

Carotid atherosclerosis is the major cause of ischemic stroke, a leading cause of mortality and disability. Morphology and structure features of carotid plaques are the keys to identify plaques and monitoring the disease. Manually segmentation on the ultrasonic images to get the best-fitted actual size of the carotid plaques based on physicians personal experience, namely "gold standard", is a important step in the study of plaque size. However, it is difficult to qualitatively measure the segmentation error caused by the operator's subjective factors. In order to reduce the subjective factors, and the uncertainty factors of quantification, the experiments in this paper were carried out. In this study, we firstly designed a carotid artery phantom, and then use three different beam-forming algorithms of medical ultrasound to simulate the phantom. Finally obtained plaques areas were analyzed through manual segmentation on simulation images. We could (1) directly evaluate the different beam-forming algorithms for the ultrasound imaging simulation on the effect of carotid artery;(2) also analyze the sensitivity of detection on different size of plaques;(3) indirectly reflect the accuracy of the manual segmentation base on segmentation results the evaluation.

关键词： Atherosclerosis Beam-Forming ultrasound phantom Gold standard Evaluation

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A FPGA-based Architecture for Real-Time image Matching

A FPGA-based Architecture for Real-Time Image Matching

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8th Symposium on Multispectral image processing and Pattern Recognition (MIPPR) - parallel processing of images and Optimization and Medical imaging processing

作者： Wang, Jianhui Zhong, Sheng xu, Wenhui Zhang, Weijun Cao, Zhiguo Huazhong Univ Sci & Technol Sch Automat Sci & Technol Multispectral Informat Proc Lab Wuhan 430074 Peoples R China

ISBN: (纸本)9780819498052

image matching is a fundamental task in computer vision. It is used to establish correspondence between two images taken at different viewpoint or different time from the same scene. However, its large computational complexity has been a challenge to most embedded systems. This paper proposes a single FPGA-based image matching system, which consists of SIFT feature detection, BRIEF descriptor extraction and BRIEF matching. It optimizes the FPGA architecture for the SIFT feature detection to reduce the FPGA resources utilization. Moreover, we implement BRIEF description and matching on FPGA also. The proposed system can implement image matching at 30fps (frame per second) for 1280x720 images. Its processing speed can meet the demand of most real-life computer vision applications.

关键词： SIFT BRIEF image matching Field Programmable Gate Array (FPGA)

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Performance Tuning on Multicore systems for Feature Matching within image Collections

Performance Tuning on Multicore Systems for Feature Matching...

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42nd Annual International Conference on parallel processing (ICPP)

作者： Tang, xiaoxin Mills, Steven Eyers, David Huang, Zhiyi Leung, Kai-Cheung Guo, Minyi Shanghai Jiao Tong Univ Dept Comp Sci Shanghai Key Lab Scalable Comp & Syst Shanghai 200030 Peoples R China Univ Otago Dept Comp Sci Otago New Zealand

ISBN: (纸本)9780769551173

parallel programming is the mainstream for today's HPC applications. Programmers need to parallelize their programs to achieve better performance on multicore systems. However, due to a lack of good understanding of parallelism in algorithms, scheduling policy in runtime systems, and multicore architectures, programmers usually find it very hard to write high-performance, scalable programs on these parallel platforms. Although using a parallelized library written by experts can reduce the amount of work for coding, it does not automatically guarantee good performance according to our study. A better understanding of parallelism in algorithms, the OS/runtime systems, and hardware architectures is necessary if programmers wish to further improve performance. In this paper, we use SIFT-based feature matching within large-scale image collections to show the importance of three factors-the level of parallelism, scheduling policy, and memory architecture-that affect the performance of large-scale feature matching on multicore systems. We demonstrate experimental results using programs based on OpenCV and OpenMP, which are executed on both 16-core and 64-core machines. From our experimental results, we find that images with a large number of features achieve poor scalability on the 64-core machine due to a poor cache utilization. To address this issue of cache performance, we propose a Divide-and-Merge algorithm that divides the feature space into several small sub-spaces so that they fit within the cache. Our experiments show that the performance tuning addressing all of the three factors improves the speedup of feature matching from 10.6x to 21.5x on the 64-core machine. While the speedup is improved by 103%, the scalability of the feature matching algorithm is improved by up to 6.45 times on the 64-core machine with our performance tuning. Our study indicates that performance tuning on multicore systems is very challenging even for a simple image processing algorithm.

关键词： cache storage image matching memory architecture merging multiprocessing systems parallel processing scheduling

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A Multi-Core FPGA-based Clustering Algorithm for Real-Time image processing

A Multi-Core FPGA-based Clustering Algorithm for Real-Time I...

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60th IEEE Nuclear Science Symposium (NSS) / Medical imaging Conference (MIC) / 20th International Workshop on Room-Temperature Semiconductor x-ray and Gamma-ray Detectors

作者： Sotiropoulou, Calliope-Louisa Annovi, Alberto Beretta, Matteo Luciano, Pierluigi Nikolaidis, Spyridon Volpi, Guido Aristotle Univ Thessaloniki Dept Phys Elect Lab Thessaloniki 54124 Greece Ist Nazl Fis Nucl Natl Lab Frascati Italy Univ Pisa Pisa Italy

ISBN: (纸本)9781479905348

A multi-core FPGA-based 2D-clustering algorithm for real-time image processing is presented. The algorithm uses a moving window technique adjustable to the cluster size in order to minimize the FPGA resources required for cluster identification. The window size is generic and application dependent (size/shape of clusters in the input images). A key element of this algorithm is the possibility to instantiate multiple clustering cores working on different windows that can be used in parallel to increase performance exploiting more resources on the FPGA device. In addition to the offered parallelism, the algorithm is executed in a pipeline, thus allowing the cluster readout to be performed in parallel with the cluster identification and the data pre-processing. The algorithm is developed for the Fast Tracker processor for the trigger upgrade of the ATLAS experiment but is easily adjustable to other image processing applications which require real-time pixel clustering.

关键词： Clustering algorithms

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