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ParkNest - The Smart Parking System Using IoT

ParkNest - The Smart Parking System Using IoT

引用

Smart systems for applications in Electrical Sciences (ICSSES), international conference on

作者： S Gagan H.K. Ravi Dept. of EIE M-Tech in VLSI Design and Embedded Systems Siddaganga Institute of Technology Tumkur INDIA Dept. of EIE Siddaganga Institute of Technology Tumkur INDIA

ISBN: (数字)9798350364040

ISBN: (纸本)9798350364057

The rise of the Internet of Things (IoT) has sparked innovation across various sectors, with ongoing exploration and implementations aimed at tackling modern-day obstacles. Among these, transportation stands out due to the increasing demand driven by population growth. As urban areas experience a surge in vehicle ownership, the availability of parking spaces becomes a pressing issue, especially in public areas like shopping malls, parks, and theaters. While manual parking systems persist in many places, the lack of clear regulations for outdoor parking worsens the problem. Traditional methods are outdated and contribute to traffic congestion, minor accidents, and inefficiencies. To address these challenges, this paper proposes a smart outdoor parking system leveraging IoT technology, specifically utilizing embedded controllers and infrared (IR) sensors. Entry and exit gate management is also implemented to allow only users who had reserved the parking slot. An Android application is developed using android studio for users to check slot availability, reserve parking spaces, and efficiently navigate to their destinations. This system is tested on a prototype of parking area creating six parking slots. By integrating hardware, cloud, and mobile application, this system aims to transform parking management, providing structured, adaptable, and user-friendly solutions for urban parking dilemmas.

关键词： Technological innovation Smart cities Transforms Real-time systems Mobile applications Internet of Things Sustainable development

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Compute-In-Place Serial FeRAM: Enhancing Performance, Efficiency and Adaptability in Critical embedded systems

Compute-In-Place Serial FeRAM: Enhancing Performance, Effici...

引用

IFIP international conference on Very Large Scale Integration (vlsi-SoC)

作者： J.-P. Noel E. Valea L. Grenouillet B. Chapuis C. Fisher A. Recoquillay B. Giraud CEA LIST Univ. Grenoble Alpes Grenoble CEA LETI Univ. Grenoble Alpes Grenoble CEA List Université Paris-Saclay Palaiseau France

In an era where embedded systems play an increasingly vital role in critical domains like electric mobility, healthcare, industry, or infrastructure monitoring, the demand for real-time data processing is paramount. This paper addresses the challenges posed by high sensor data rates and limited processing power of microcontrollers (MCUs) in these applications. It introduces a novel computational method leveraging the Serial Ferroelectric RAM (FeRAM) architecture, along with the Computational SRAM concept, and will be called Compute-In-Place (CIP). This exploration of CIP Serial FeRAM reveals its potential for improving predictability, energy efficiency and security in high-throughput processing of large volumes of sensor data. Unlike conventional computing architectures, CIP Serial FeRAM lightens the MCU's computational load, reduces latency and improves energy efficiency by enabling computational tasks within memory. This paper emphasizes the flexibility of CIP Serial FeRAM for diverse real-time tasks, paving the way for more performance, efficient and adaptable critical embedded systems.

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Design and optimization of power management circuits for low-power vlsi systems

Design and optimization of power management circuits for low...

引用

Innovative Computing, Intelligent Communication and Smart Electrical systems (ICSES), international conference on

作者： T. Ramashri A. Ananthi Christy K Abdul Munaf V. Gowri D. Raja Ramesh M. Deivakani Department of Electronics and Communication Engineering SVU College of Engineering SV University Tirupati India Department of Marine Engineering AMET University Chennai Tamil Nadu India Department of Electronics and Communication Engineering IIIT RK Valley Idupalapaya India Department of Electronics and Communication Engineering JJ College of Engineering and Technology Trichy Tamil Nadu Department of Electronics and Communication Engineering MVGR College of Engineering (A) Vizianagaram Andhra Pradesh Department of Electronics and Communication Engineering PSNA College of Engineering and Technology Dindigul Tamil Nadu

This study delves into the topic of low-power vlsi system power management circuit design and optimization. The purpose of this research is to learn what influences vlsi circuits' power consumption and how to minimize that effect in low-power vlsi designs. Using multiple linear regression analysis, this research determines that capacitance, frequency, voltage and temperature are all important predictors of power usage in vlsi circuits. The study's findings may be utilized to guide the creation of novel power management strategies and technologies, with significant implications for the design and optimization of power management circuits in low-power vlsi systems. New materials and technologies for vlsi systems, as well as improved power management strategies, are only two examples of where the report proposes future research should go. This study's findings have significant significance for a broad variety of applications, including embedded systems, mobile devices and IoT gadgets, since they provide light on the design and optimization of power management circuits for low-power vlsi systems.

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FMEA on Critical systems: A Cross-Layer Approach Based on High-Level Models 1

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29th IFIP WG 10.5/IEEE international conference on Very Large Scale Integration (vlsi-SoC)

作者： Roux, Julie Morin-Allory, Katell Beroulle, Vincent Bossuet, Lilian Cezilly, Frederic Berthoz, Frederic Genevrier, Gilles Cerisier, Francois Leveugle, Regis Univ Grenoble Alpes LCIS Grenoble INP Inst Engn CNRS F-26000 Valence France Univ Grenoble Alpes TIMA Grenoble INP Inst Engn CNRS F-38000 Grenoble France Univ Lyon Lab Hubert Curien F-42000 St Etienne France THALES F-26000 Valence France AEDVICES F-38430 Moirans France

ISBN: (数字)9783031168185

ISBN: (纸本)9783031168185;9783031168178

Designing embedded systems for critical applications requires meeting strict safety constraints according to official standards. In current practice, safety analysis (e.g., Failure Mode and Effects Analysis) is often only relying on human experience and therefore lacks detailed data. Performing more detailed analyses on complex systems is a major challenge to avoid pessimistic assumptions and consequently to avoid over-design of the system, i.e., adding too many protections with respect to the system specifications and risk. Many fault injection techniques have been previously proposed to better evaluate the robustness of circuit designs described at various abstraction levels. However, very few take into account the global system constraints. Also, fault injection experiments become very time-consuming for complex designs. At the highest levels of abstraction (e.g., Transaction level), simulations are faster but suffer of the lack of realism of high-level models. Our contribution is to propose both an increase in safety analysis precision and a fault injection flow improving the analysis duration. The flow is based on an iterative process, taking into account the global system specifications and allowing improvements of high-level models to achieve both precision and efficiency. Improvements are based on metrics, and results are shown on a real airborne system.

关键词： Safety embedded system FMEA Fault simulation Cross-layer

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A 0.75mm2 407μW Real-Time Speech Audio Denoiser with Quantized Cascaded Redundant Convolutional Encoder-Decoder for Wearable IoT Devices

A 0.75mm2 407μW Real-Time Speech Audio Denoiser with Quanti...

引用

international conference on vlsi Design

作者： Dimple Vijay Kochar Maitreyi Ashok Anantha P. Chandrakasan Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Audio denoising is crucial for delivering high-quality sound in applications ranging from communication devices to entertainment systems. On-device denoising is critical for en-suring consistent performance across various host platforms. Machine learning (ML) models exhibit strong audio processing performance in the frequency domain but require efficient hardware design. This paper focuses on enhancing audio quality using convolutional encoder-decoder ML models with low power consumption while meeting real-time processing constraints. We achieve this by developing a quantized network that optimally reduces computational costs without compromising enhancement quality. Furthermore, our hardware quantization scheme reduces memory usage by up to 75% while maintaining accuracy. Next, we design a complementary processing element activation routing scheme tailored to our algorithm, significantly reducing the on-chip memory accesses by $\mathbf{5}-\mathbf{9}\times$ . Fabricated in 28nm CMOS process, our chip demonstrates real-time audio denoising, processing each frame within 8ms while consuming only $407\ \mathbf{\mu} \mathbf{W}$ or 3.24 μJ/frame at 0.65V, 18.5 MHz, making it ideal for battery-powered IoT devices. In terms of performance, our chip also achieves the highest evaluation score for audio quality (PESQ), outperforming previous works.

关键词： Performance evaluation Quantization (signal) Power demand Accuracy Computational modeling Noise reduction Very large scale integration Real-time systems Hardware Internet of Things

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Cross-layer Approach to Assess FMEA on Critical systems and Evaluate High-Level Model Realism 29

Cross-layer Approach to Assess FMEA on Critical Systems and ...

引用

29th IFIP/IEEE international conference on Very Large Scale Integration (vlsi-SoC)

作者： Roux, Julie Morin-Allory, Katell Beroulle, Vincent Leveugle, Regis Bossuet, Lilian Cezilly, Frederic Berthoz, Frederic Genevrier, Gilles Cerisier, Francois Univ Grenoble Alpes CNRS Grenoble INP LCIS F-26000 Grenoble France Univ Grenoble Alpes CNRS Grenoble INP TIMA Grenoble France Univ Lyon Labo Hubert Curien F-42000 Saint Etienne France THALES F-26000 Valence France AEDVICES F-38430 Moirans France

ISBN: (纸本)9781665426145

embedded systems in critical applications are constrained by very strict standards. The safety of such systems is crucial, however, their safety analysis (e.g., Failure Mode and Effects Analysis, or FMEA) is often empirical and mainly relies on the experience of engineers. Performing empirical analyses on complex designs is a major challenge that leads engineers to make very pessimistic assumptions and consequently to over-design multiple countermeasures. Many fault injection techniques have been developed to evaluate the robustness of hardware designs from Register Transfer Level to Transaction Level. At the RT-level, these techniques are circuit-centered, and therefore do not rely on the overall system specifications. Besides, with complex hardware designs, fault simulations become very time-consuming. Conversely, at the transaction level, fault simulation is fast to the detriment of the realism of high-level models. In this paper, we present a new iterative cross-layer robustness analysis flow taking into account the overall critical system specifications and verifying the realism of high-level models. The first step of the flow leads to extract critical parameter ranges. Then, these ranges are used to quickly evaluate the robustness of each RTL block in the circuit. In the last step, we compute some metrics reflecting the realism of the high-level models. According to these metrics, we can determine if the high-level models must be improved. We apply this methodology to a case study of a real airborne system.

关键词： safety fault simulation SystemC TLM embedded system FMEA

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Design of a Novel Encoder for Flash Analog to Digital Converter

Design of a Novel Encoder for Flash Analog to Digital Conver...

引用

2022 IEEE international conference on Data Science and Information System, ICDSIS 2022

作者： Sadath, Arshiya Deepa Siddaganga Institute of Technology Vlsi Design and Embedded Systems Tumakuru India

ISBN: (数字)9781665498012

ISBN: (纸本)9781665498012

Analog to digital converters (ADC) are extensively used as a basic component in signal processing systems to convert the available analog signals to digital signals. Flash ADC, also called as parallel ADC offer high speed conversion than other ADCs. The major issues occurring in the Flash ADC are the response time of comparators and speed of thermometer to binary encoder. Therefore, different designs have been proposed previously for both comparators and encoders to overcome these issues. This work is centred on the encoder and reviews the different designs of encoders such as multiplexers, adders, adders with majority gates as its carry function and XOR-MAJ encoder. A novel encoder is proposed which is designed using full adders to reduce the number of transistors and eventually reducing number of capacitance nodes to reduce delay. The design is simulated at 130nm CMOS technology using Mentor Graphics EDA tool. The comparison of designs shows the worst-case delay, number of transistors and power consumption. The result analysis show that the novel encoder uses 92 transistors with the worst-case delay of 144.77 ns but the power dissipation is about 51.34 nW which is comparatively highest. Hence the analysis shows the novel encoder can be used when the constraints are number of transistors and delay but not for low power applications. © 2022 IEEE.

关键词： Adders

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FPGA Implementation of Systolic Array for 2D Convolution Using Residue Number System

FPGA Implementation of Systolic Array for 2D Convolution Usi...

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Electrical, Electronics, Communication and Computers (ELEXCOM), international conference on

作者： Tulip Bera Shuvabrata Dey Microelectronics and VLSI Technology Maulana Abul Kalam Azad University of Technology Haringhata Nadia West Bengal India VLSI Design and Embedded Systems Maulana Abul Kalam Azad University of Technology Haringhata Nadia West Bengal India

This paper presents an FPGA implementation of a systolic architecture for 2D convolution using the residue number system (RNS) with a designed new residue adder and residue multiplier. The proposed architecture offers improved processing speed by leveraging the benefits of RNS. Additionally, the use of a systolic array enhances parallelism, further boosting the overall performance of the convolution operation. Experimental results demonstrate the effectiveness of the approach, highlighting its potential for accelerated convolutional neural networks and real-time signal processing applications.

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A new MBFF merging strategy for post-placement power optimization of IoT devices 18

A new MBFF merging strategy for post-placement power optimiz...

引用

18th ACS/IEEE international conference on Computer systems and applications (AICCSA)

作者： Attaoui, Yassine Chentouf, Mohamed Ismaili, Zine El Abidine Alaoui El Mourabit, Aimad Siemens EDA CSD Cal Synth Solut Rabat 10010 Morocco Mohammed V Univ Informat Commun & Embedded Syst ICES Team Rabat 10010 Morocco Abdelmalek Essaadi Univ Syst & Data Engn Team ENSA Tangier Tetouan Morocco

ISBN: (纸本)9781665409698

Recently power has become the most important factor in vlsi design. As clock network is the largest design element in terms of power consumption in modern low-power Very Large Scale Integration (vlsi) Designs and IoT applications, several studies have been made in order to reduce the power leaks and unnecessary switching of the clock network. The clock gating, as well as the use of Multibit Flip Flops (MBFFs), are some of the widely used low-power technics. In this paper, we presented a novel approach for power consumption reduction in IoT systems by applying an iterative MBFF insertion. we will make several trials on the use of multi-bit Flip-Flops during each phase of logic Synthesis, Placement, and Optimization. In the first trial, we have measured the impact of MBFF merging on power and circuit performance in several development stages using 2-bits and 4-bits MBFFs. In the second trial, we have combined 2-bits and 4-bits MBFFs and measured the power numbers and circuit's performance. Finally, we have applied an iterative MBFF merging algorithm and measure the PPA (Power, Performance, and Area) impact versus traditional MBFF implementation. The result of this experiment achieved a better total MBFF merging coverage of 76.6%, a good routability maintenance with less congestion, less wire-length by 3.8% leading to a switching power improvement of around 3.3% with no timing and area degradation.

关键词： ASIC Logic Synthesis Low-Power Clock Tree Multibit Flip-Flop IoT

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Fabrication and Testing of a PneuNet Actuator-Based Caterpillar Like Amphibian Soft Robot for Multi-Terrain applications

Fabrication and Testing of a PneuNet Actuator-Based Caterpil...

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IEEE international conference on Flexible and Printable Sensors and systems (FLEPS)

作者： Sourav Karmakar Astitva Ranjan Aftab M Hussain FleCS Lab Center for VLSI and Embedded Systems Technology (CVEST) International Institute of Information Technology Hyderabad India

Bio-inspired structures provide several new possibilities in the area of robotics due to their superiority and diversity in execution. Researchers have been developing various robotic applications with the combination of soft materials such as silicone and various 3D printed materials. These kinds of soft robots can be useful for various human-robotic interactions such as search and rescue, medical surgery and so on. In this work, we present the fabrication and characterization of a small caterpillar-like soft robot (7 cm $\times 3.5$ cm $\times 3$ cm) powered using PneuNet actuation. Due to the limitations of traditional robotics, we believe that such soft material-based robots can be effective in various applications. The fabricated silicone-based PneuNet soft robot, which moves like a caterpillar, has also been embedded with an ESP camera module and LED light to enable applications such as surveillance and search-and-rescue. This soft robotic actuator can also perform tasks on various types of terrains, including ice and water surface. We find that the normalized distance travelled per actuation cycle on gravel to be 0.23 BL.

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