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检索条件"任意字段=Internation Conference on Embedded Systems and Applications/International Conference on VLSI"

共 884 条记录，以下是11-20 订阅

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Towards Scalability and Performance: Framework for Heterogeneous Cluster Integration in Deep Learning Accelerators 4

Towards Scalability and Performance: Framework for Heterogen...

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4th IEEE international conference on vlsi systems, Architecture, Technology and applications, vlsi SATA 2024

作者： Bhagirath, K. Pant, Dheeraj Tiwari, Abhishek Khaneja, Vivek Centre For Development Of Advanced Computing Embedded Systems Division Noida India

ISBN: (纸本)9798350362268

This paper presents a streamlined approach to address the challenges of integrating heterogeneous clusters in deep learning(DL) accelerators. As the demand for scalable and high-performance computing in DL continues to grow, the proposed framework offers an easy implementation solution, ensuring efficiency without compromise. The method details core components and design principles, guiding the inclusion of heterogeneous clusters step by step. Extensive experiments show the framework's adaptability, handling diverse workloads and cluster architectures. Our exploration integrates various dataflows, dynamically selected by NN during runtime for optimal performance. Results indicate improved scalability and robustness compared to existing methods. This research provides a valuable resource for practitioners seeking efficient and accessible solutions for harnessing the power of heterogeneous clusters in DL acceleration, with implications for advancements in AI and computational efficiency. © 2024 IEEE.

关键词： Computational efficiency

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Investigation of Reliability of a Polypyrrole coated Conductive Cotton Fabric for Sensing applications 6

Investigation of Reliability of a Polypyrrole coated Conduct...

引用

international conference on Flexible and Printable Sensors and systems (FLEPS)

作者： Fatema, Anis Mishra, Saurabh B. Hussain, Aftab M. Int Inst Informat Technol FleCS Lab Ctr VLSI & Embedded Syst Technol CVEST Hyderabad India

ISBN: (纸本)9798350383270;9798350383263

Electrically conductive fibers are attracting attention because of the newly emerging areas of interactive textiles and smart fabrics. In this paper, we present the fabrication and characterization of a flexible conductive cotton fabric (CCF) of size 20 cmx20 cm coated with polypyrrole synthesized using in-situ chemical oxidative polymerization. This is the largest area reported in the literature for a polypyrrole-coated conducting fabric. The characteristics of the conducting fabric were investigated at 25 points by sandwiching it between the electrodes in the form of a 5x5 array. To test its reliability, the CCF was washed with distilled water 10 times, and its response was measured after every wash. We observed that there was a change in the resistance after the first four washes, however, the response stabilized thereafter. The average deviation in resistance until first four washes was found to be 27.45%, whereas for washes 6 to 10, it was 5.11%.

关键词： Conductive fabric Flexible Piezoresistive Polypyrrole Reliability

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Proceedings - 37th international conference on vlsi Design, vlsiD 2024 - held concurrently with 23rd international conference on embedded systems, ES 2024

Proceedings - 37th International Conference on VLSI Design, ...

引用

37th international conference on vlsi Design, vlsiD 2024

ISBN: (纸本)9798350384406

The proceedings contain 124 papers. The topics discussed include: a novel approach to control a DC-DC converter using its empirical physical model;optimizing medical image analysis: leveraging efficient hardware and AI algorithms;DFT static verification using early RTL exploration and debug for mobile SoC and edge AI applications;reconfigurable processing-in-memory architecture for data intensive applications;parallel-series diode-based ring amplifier for switched capacitor circuits;enhancing output corruption through GSHE switch based logic encryption;on managing test-time, power, and layer assignment in 3D socs with built-in-self-repair modules;a compact low-power 29 Gb/s pseudo random quaternary sequence generator in 65 nm CMOS;and CAD tools pathway in hardware security.

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REMOTE: Re-thinking Task Mapping on Wireless 2.5D systems-on-Package for Hotspot Removal 31

REMOTE: Re-thinking Task Mapping on Wireless 2.5D Systems-on...

引用

31st IFIP/IEEE international conference on Very Large Scale Integration (vlsi-SoC)

作者： Medina, Rafael Huang, Darong Ansaloni, Giovanni Zapater, Marina Atienza, David Ecole Polytech Fed Lausanne Embedded Syst Lab ESL Lausanne Switzerland HES SO REDS Inst Delemont Switzerland

ISBN: (纸本)9798350325997

2.5D systems-on-Package (SoPs) are composed by several chiplets placed on an interposer. They are becoming increasingly popular as they enable easy integration of electronic components in the same package and high fabrication yields. Nevertheless, they introduce a new bottleneck in inter-chiplet communication, which must be routed through the interposer. Such a constraint favors mapping related tasks on computing cores within the same chiplet, leading to thermal hotspots. Inpackage wireless technology holds promise to reconsider such a position because integrated wireless antennas provide low-latency and high-bandwidth communication paths, thus bypassing the interposer bottleneck. Furthermore, in this work, we propose a new task mapping heuristic that leverages in-package wireless technology to improve the thermal behavior of 2.5D SoPs executing complex applications. Combining system simulation and thermal modeling, our results show that we can distribute computation in wireless 2.5D SoPs to reduce peak temperatures by up to 24% through task mapping with a negligible performance impact.

关键词： Task mapping In-package wireless communication Thermal management Multi-chiplet systems

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A 2.75-2.94 GHz Voltage Controlled Oscillator with Low Gain Variation for Quantum Sensing applications 35

A 2.75-2.94 GHz Voltage Controlled Oscillator with Low Gain ...

引用

35th international conference on vlsi Design (vlsiD) / 21st international conference on embedded systems (ES)

作者： Edakkadany, Adithya Sunil Desaiz, Kuntal Srivastavay, Abhishek IIIT Hyderabad Ctr VLSI & Embedded Syst Technol CVEST Hyderabad India IIT Kanpur Dept Elect Engn Kanpur Uttar Pradesh India

ISBN: (纸本)9781665485050

Quantum sensing applications such as nitrogen vacancy based magnetometry require phase locked loops (PLL), which can synthesize microwave frequencies in a narrow band near 2.87 GHz. Moreover, it is also required that the PLLs should have low noise and low jitter for high stability and fast settling time. These requirements seek low phase noise voltage controlled oscillator (VCO) with small variation in its gain (K-VCO) within the desired tuning range. In this paper, we present a technique for designing a low phase noise VCO with low K-VCO and small K-VCO variation. To validate the proposed technique, an LC VCO has been designed and implemented in 0.18 mu m CMOS process and post layout simulation results are presented. The simulation results show that the proposed LC VCO achieves K-VCO variation of +/- 3.82% in the frequency range of 2.75 - 2.94 GHz and exhibits a phase noise of -118.64 dBc/Hz at an offset of 1 MHz, while consuming 9 mW of power from a 1.8 V supply.

关键词： VCO low phase noise K-VCO variation quantum sensing oscillator

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international conference on vlsi, Signal Processing, Power Electronics, IoT, Communication and embedded systems, VSPICE 2023

International Conference on VLSI, Signal Processing, Power E...

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international conference on vlsi, Signal Processing, Power Electronics, IoT, Communication and embedded systems, VSPICE 2023

ISBN: (纸本)9789819746569

The proceedings contain 35 papers. The special focus in this conference is on vlsi, Signal Processing, Power Electronics, IoT, Communication and embedded systems. The topics include: Sensor Perception Reliability in Automated Vehicles;design and Implementation of 16-Bit Posit Arithmetic;emergence, Evolution, and applications of Medical Cyber-Physical systems;smart Insole Design for Foot Pressure Monitoring;an Efficient Cryptographic Technique to Improve Data Privacy and Security in E-Commerce;an Iot-Based Transmission Line Fault Monitoring System;performance Analysis of the System of IoT Architecture;real-Time Implementation of IoT-Based Home Automation System on Arduino Platform;Data Security Paradigms: Paillier Homomorphic Encryption and AES in the Context of Privacy-Preserving Computation;a Review on Watermarking Techniques of Digital Image;An Improved Pre-charging Strategy for Asymmetrical Mixed-Cell Submodule (SM) Based Modular Multilevel Converter;classification of Remotely Sensed Data Using Fisher’s Linear Discriminant;design of Smart Wheelchair for Disabilities with Quadriplegia Through Brain–Computer Interface;Automatic Load Distribution of Power During Low Power Generation Using PLC;AI-driven Lung Cancer Detection for Rapid Analysis of Medical Imaging Data;comparative Study of Transfer Learning Models for Mushroom Classification;automated Software Defect Prediction Model: AdaBoost-Based Support Vector Machine Approach;Preprocessing of MRI Data for the Early Detection of Alzheimer’s Disease Using DWT;classification of Soybean Seed Using Support Vector Machine with Image Enhancement Techniques;From Deployment to Drift: A Comprehensive Approach to ML Model Monitoring with Evidently AI;a Real-Time Computer Vision-Based Green Intensity Estimation Method for the Arecanut Tree Pesticide Spraying System;key Enabling Technologies for Next-Generation Wireless systems.

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Design and Implementation of BIST Architecture for low power vlsi applications using Verilog

Design and Implementation of BIST Architecture for low power...

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2023 international conference on Smart systems for applications in Electrical Sciences, ICSSES 2023

作者： Gonda, Aadesh Bharathi, S.H. Reva University Vlsi and Embedded Systems Bangalore India School of Ece Reva University Bangalore India

ISBN: (纸本)9798350347296

The proposed BIST architecture focuses on minimizing power consumption during the testing phase while maintaining high fault coverage. It leverages the capabilities of the Verilog hardware description language to model and simulate the design. The research investigates various power reduction techniques, including test pattern compression, selective clock gating, and power-aware test scheduling, to optimize power consumption during testing. This research paper presents the design and implementation of a Built-In Self-Test (BIST) architecture specifically tailored for low-power Very Large-Scale Integration (vlsi) applications. The increasing demand for energy-efficient electronic devices and the proliferation of portable systems have necessitated the development of power-aware design techniques. BIST, a onchip testing technique, plays a crucial role in ensuring the quality and reliability of integrated circuits. The implementation is performed on a field-programmable gate array (FPGA) platform, demonstrating the feasibility and practicality of the proposed design. The research contributes to the field of low-power vlsi design by providing a comprehensive BIST architecture that effectively reduces power consumption during testing. The proposed design is compatible with standard Verilog synthesis and is readily applicable to a wide range of low-power vlsi applications. The findings from this study can guide designers in developing energy-efficient and reliable integrated circuits, promoting sustainability, and extending battery life in portable devices. © 2023 IEEE.

关键词： vlsi circuits

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Design and Analysis of Posit Quire Processing Engine for Neural Network applications 36

Design and Analysis of Posit Quire Processing Engine for Neu...

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36th international conference on vlsi Design (vlsiD) / 22nd international conference on embedded systems (ES)

作者： Edavoor, Pranose J. Raveendran, Aneesh Selvakumar, David Desalphine, Vivian Shankar, Dharani G. Raut, Gopal Ctr Dev Adv Comp Bangalore Secure Hardware & VLSI Design Grp Bangalore Karnataka India

ISBN: (纸本)9798350346787

Multiplications-Accumulations (MACs) are the significant computations in deep learning networks that must be hardware efficient and result in higher inference accuracy for the given set of network layers. Typically, the processing engines (PEs) which comprise the MAC units are the most resource-intensive element in a Deep Neural Network (DNN) accelerator. This paper proposes efficient PEs and presents an architectural design, accuracy, and resources cost analysis for hardware-based parameterized Posit Quire Processing Engine (PQPE) supporting P(8,0), P(16,1), P(32,2), and P(64,3). PQPE performs the vector computations (dot products) on Posit numbers with a wide quire accumulator and has been enabled with instructions, commands, and responses. PQPE has been modelled in Python to evaluate the inference accuracy for various DNN kernels and datasets. LeNet-5, AlexNet, custom 5 layers and 4 layers CNN models have been adopted and evaluated for inference accuracy with MNIST, CIFAR-10, and Alphabet recognition datasets. The PQPE has been used for matrix computations in convolutions. P(16,1) without quire provides same accuracy as float32 with less hardware resources. P(16,1) with quire brings same accuracy level as without quire and hence quire is not advantageous for larger posit data widths. Posit (8,0) with / without quire results insignificant loss of 0.8% / 3.28% (LeNet + MNIST) to 3.8% / 10.1% (AlexNet + CIFAR-10) accuracy as compared to P(16,1)/float32. Further, PQPE was modelled using Verilog HDL, synthesized targeting Xilinx Virtex-7 FPGA using Xilinx-Vivado. PQPE (8,0) achieved a f(max) of 372 MHz and utilized 77.6% fewer hardware resources as compared to float32 at the cost of insignificant accuracy loss for CIFAR-10 which is 0.8% on LeNet and 3.8% on AlexNet. PQPE (16,1) has used 6.5% less resources and achieved equivalent accuracy as compared to float32.

关键词： Posit MAC Engine Posit Quire Accumulators Posit for AI/ML Neural Network Processing Engine Inference Accuracy

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2023 IFIP/IEEE 31st international conference on Very Large Scale Integration, vlsi-SoC 2023

2023 IFIP/IEEE 31st International Conference on Very Large S...

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31st IFIP/IEEE international conference on Very Large Scale Integration, vlsi-SoC 2023

ISBN: (纸本)9798350325997

The proceedings contain 51 papers. The topics discussed include: a 16-bit floating-point near-SRAM architecture for low-power sparse matrix-vector multiplication;optimized quantum circuit implementation of payoff function;dynamic scheduling for event-driven embedded industrial applications;towards robust process design kits with a scalable DevOps quality assurance platform;a novel approach to extract embedded memory design parameter through irradiation test;synthesis of SFQ circuits with compound gates;frontiers in ai acceleration: from approximate computing to FeFET monolithic 3D integration;and on the reliability of RRAM-based neural networks.

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Design of vlsi Architecture Using AES Algorithm 3

Design of VLSI Architecture Using AES Algorithm

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3rd international conference on Artificial Intelligence For Internet of Things, AIIoT 2024

作者： Indra, J. Shiny Pershiya, A. KPR Institute of Engineering and Technology Department of ECE Coimbatore India

ISBN: (纸本)9798350372120

Security in signal processing involves implementing robust encryption techniques and authentication measures to safeguard sensitive information from unauthorized access or manipulation, ensuring the integrity and confidentiality of processed data in various applications. This paper presents a pioneering vlsi architecture merging Discrete Wavelet Transform (DWT) with robust encryption algorithms for fortified security in data processing. Aimed at embedded systems, it ensures data integrity and confidentiality. By marrying DWT's computational efficiency for analysis and encryption prowess of AES, it enables real-time processing while safeguarding sensitive information. The design harnesses parallel processing, augmenting throughput and reducing latency for extensive data volumes. Comparative results highlight superior performance in speed, security, and resource utilization over traditional systems. This adaptable framework finds application in secure communications, biomedical signal processing, multimedia encryption, and IoT devices, addressing the critical intersection of signal processing and data security. This vlsi integration of DWT and advanced encryption presents a potent solution for secure, efficient data processing in resource-limited environments. The proposed system exhibits an on-chip power consumption of 535mW, a memory capacity of 819.922 MB, and a gain of 519.445 dB, all while maintaining a stable junction temperature of 33°C. © 2024 IEEE.

关键词： Discrete wavelet transforms

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