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检索条件"任意字段=Internation Conference on Embedded Systems and Applications/International Conference on VLSI"

共 884 条记录，以下是61-70 订阅

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An mmWave Frequency Range Multi-Modulus Programmable Divider for FMCW Radar applications

An mmWave Frequency Range Multi-Modulus Programmable Divider...

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international conference on vlsi Design

作者： Sresthavadhani Mantha Adithya Sunil Edakkadan Arpit Sahni Abhishek Srivastava Center for VLSI and Embedded Systems Technology (CVEST) IIIT Hyderabad India

Recently, there has been a major shift in advanced driver assistance systems (ADAS) from the camera and LiDAR-oriented systems to mmWave radar-based systems. Such high-frequency band radars currently using frequency modulated continuous wave (FMCW) technique require programmable dividers with large divide ratios and fine frequency resolution to obtain high-frequency chirps with sufficiently large bandwidth. This paper presents a low-power multi-modulus programmable frequency divider for a frequency synthesizer operating in the 19.25-20.25 GHz frequency band from a reference frequency of 40 MHz. The divider consumes 14 mW of power and is capable of producing divide ratios in the range of 481.25-506.25 with a fine resolution of 1 MHz. The divider has a phase noise of −146 dBc/Hz at an offset of 2 kHz.

关键词： Phase noise Frequency synthesizers Frequency modulation Voltage-controlled oscillators Very large scale integration Frequency conversion Transceivers

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A Fully On-Chip Tunable Impedance Matching Strategy for Maximum Power Transfer in RF Energy Harvesting systems 2nd

A Fully On-Chip Tunable Impedance Matching Strategy for Max...

引用

2nd international conference on Advances in vlsi and embedded systems, AVES 2021

作者： Makwana, Dhruv Mohan, Arun Mondal, Saroj Birla Institue of Science and Technology Pilani Hyderabad Campus Hyderabad India

ISBN: (纸本)9789811967795

This paper presents a fully on-chip tunable impedance matching scheme to reduce the power transfer losses across the antenna rectifier interface in an RF energy harvesting system. The proposed matching scheme avoids bulky off-chip inductors and utilizes on-chip varactor-based inductors for low form-factor applications. The proposed scheme has been designed and simulated using a 0.18 μ m CMOS technology node for an operating frequency of 953 MHz. A study of the S11 characteristics exhibits a magnitude of greater than −20 dB, thereby illustrating the effectiveness of the proposed matching scheme. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Varactors

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RISC-V Based Secure Processor Architecture for Return Address Protection

RISC-V Based Secure Processor Architecture for Return Addres...

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international conference on vlsi Design

作者： Lalit Sharma Neeraj Goel Indian Institute of Technology Ropar India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

RISC-V-based cores are increasingly becoming pop-ular in embedded system applications because of their open-source architecture. Protecting such systems against memory-based attacks is one of the most difficult challenge. Buffer over-flow (BFO) attacks, specifically on Stack, can alter the program execution flow and are extensively employed by attackers. RISC-V foundation is working on specifications that will be used to maintain the control flow integrity (CFI) of the overall system. It will add ‘zicfiss’ and ‘zicfiip’ extensions for both backward edge and forwarded edge CFI, respectively. We propose a hardware-based approach that uses existing Return Address Stack (RAS) and requires low overhead, minimal microarchitecture changes, and limited software overhead to protect against such attacks. We assessed the performance of our design using buffer-intensive benchmarks. We verified its security by subjecting it to evaluation with the RIPE benchmark and our in-house test cases for BFO check. This approach safeguards the system from BFO attacks and could also enhance its security against Spectre attacks that exploit RAS vulnerabilities. We validated our design with Rocket-Core-based SoC and found less than 0.1% memory overhead and 2% timing overhead from the best case.

关键词： Out of order embedded systems Microarchitecture Memory management Benchmark testing Very large scale integration Software Delays Security Protection

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Proceedings of the 2022 IFIP/IEEE 30th international conference on Very Large Scale Integration, vlsi-SoC 2022

Proceedings of the 2022 IFIP/IEEE 30th International Confere...

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30th IFIP/IEEE international conference on Very Large Scale Integration, vlsi-SoC 2022

ISBN: (纸本)9781665490054

The proceedings contain 90 papers. The topics discussed include: a hardware-based HEFT scheduler implementation for dynamic workloads on heterogeneous SoCs;RISC-V processor trace encoder with multiple instructions retirement support;guiding FPGA detailed placement via reinforcement learning;generation of formal CPU profiles for embedded systems;simulation-based maximum coverage hazards detection and elimination analysis, supporting combinational logic loops;investigation on performance, power, area trade-offs using deterministic and Monte-Carlo process variation aware synthesis flows;system design for computation-in-memory: from primitive to complex functions;frequency synthesizers for 5G applications;gradient backpropagation based feature attribution to enable explainable-AI on the edge;enabling automotive electrification on heterogeneous automotive microcontroller using virtual system modelling;and a comparison of SAT-based and SMT-based frameworks for X-value combinational equivalence checking.

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Using Monte Carlo Tree Search for EDA - A Case-study with Designing Cross-layer Reliability for Heterogeneous embedded systems 29

Using <i>Monte Carlo Tree Search</i> for EDA - A Case-study ...

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29th IFIP/IEEE international conference on Very Large Scale Integration (vlsi-SoC)

作者： Sahoo, Siva Satyendra Kumar, Akash Tech Univ Dresden Ctr Adv Elect Dresden CfAED Chair Processor Design Dresden Germany

ISBN: (纸本)9781665426145

Continued transistor scaling and increasing power density have led to considerable increase in fault-rates in silicon nanotechnology-based real-time systems. Cross-layer fault tolerance techniques present a more cost-efficient methodology for adapting to such increased fault rates by distributing fault-tolerance to different layers. To this end, we propose a methodology for integrating the design space exploration (DSE) for task-mapping on heterogeneous hardware-platforms with designing cross-layer reliability. Specifically, we model the DSE for task-mapping with cross-layer reliability as a tree search problem and use Monte Carlo Tree Search for task-mapping and scheduling applications with specific reliability requirements. The proposed methodology results in considerable improvements over a standalone approach to task-mapping and implementing cross-layer reliability.

关键词： Cross-layer System Design Reliability Randomized Algorithms Design Space Exploration System-level Design embedded systems

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Comparative performance analysis of FinFET, CNTFET and GNRFET for low power digital logic circuit applications

Comparative performance analysis of FinFET, CNTFET and GNRFE...

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2022 IEEE international conference of Electron Devices Society Kolkata Chapter, EDKCON 2022

作者： Arora, Sneha Tripathi, Suman Lata Lovely Professional University Vlsi Design School of Electronics and Electrical Engineering Punjab Phagwara India

ISBN: (纸本)9781665472050

Power dissipation is one of the critical considerations while designing CMOS vlsi circuits for battery- and externally-powered embedded computer applications. This paper discusses a collection of methods that are well-suited for CMOS technology and are easily applicable to vlsi systems and circuit designers specifically for digital logic circuits, SRAM cells and Ternary Logic Gates. Supply-voltage-scaled CMOS is described as a low-power method for digital logic that provides a flexible design space for balancing energy (and power) consumption with circuit speed. Decoders are essential for vlsi and consideration for low power devices is in high demand as portability and battery become a challenge these days. In this paper, a review of techniques and circuits used for ternary logic gates is presented. Also, decoders using GNRFET and FinFET are simulated using HSPICE Tool. Scaling traditional complementary metal-oxide semiconductors (CMOS) has been plagued by issues such as the short channel effect and leakage power. Many transistors based on FinFET, GNRFETs, and DGFETs technologies are used to improve the performance metrics like power consumption, delay, IC area etc. Also, a comparative analysis shows a reduction in power of the order of 102 with 14T and 15T GNRFET based decoder over the MOSFET counterpart. © 2022 IEEE.

关键词： Logic gates

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MERGERS: Multi-Access Edge Resource Governance for Real-Time SaaS systems

MERGERS: Multi-Access Edge Resource Governance for Real-Time...

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international conference on vlsi Design

作者： Aakashjit Bhattacharya Arnab Sarkar Ansuman Banerjee ATDC IIT Kharagpur India ACMU ISI Kolkata India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

The Multi-access Edge computation (MEC) paradigm is being regarded as a viable alternative for handling data and computation requirements of complex real-time and safety-critical applications in upcoming IoT systems. This paper presents a resource arbitration technique called MERGERS that utilizes a central adaptive orchestrator called Resource Arbiter (RA), to dynamically allocate real-time service requests among heterogeneous MEC servers of a 5G MEC Software-as-a-Service (SaaS) provider. The objective of MERGERS is to maximize overall resource utilization of the given set of MEC servers through efficient load balancing. The approach partitions time into uniform intervals known as epochs. At the start of each epoch, RA takes into account the computational, storage, and deadline requirements of new client requests received in the previous epoch. It then uses a strict admission control policy to assign the new requests to suitable MEC edge servers, while ensuring that the hard real-time requirements of already scheduled tasks are not compromised. A newly arrived request is rejected if it's inclusion in the system can lead to deadline misses. Experimental results show MERGERS is able to achieve high task acceptance rates over a variety of simulation scenarios.

关键词： Multi-access edge computing embedded systems Corporate acquisitions Software as a service Admission control Very large scale integration Load management Real-time systems Servers Resource management

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OwlsEye: Real-Time Low-Light Video Instance Segmentation on Edge and Exploration of Fixed-Posit Quantization

OwlsEye: Real-Time Low-Light Video Instance Segmentation on ...

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international conference on vlsi Design

作者： Gaurav Shah Abhinav Goud Zaqi Momin Joycee Mekie Indian Institute of Technology Gandhinagar

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Video Instance Segmentation (VIS) in low light conditions presents a significant challenge when deployed on resource-constrained edge devices, especially in autonomous vehicles, surveillance, robotics, or similar applications. This paper presents OwlsEye, which, to the best of our knowledge, is the first hardware implementation for real-time Video Instance Segmentation under low-light settings using an off-the-shelf RGB camera. Implemented on the Intel Nezha embedded platform, OwlsEye demonstrates an improvement in Frames Per Second (FPS) from 0.6 to 28 FPS using model weight quantization, brightness verification, and asynchronous FIFO Pipelining. This paper also presents the EQyTorch framework, an extension of Qtorch+ for fixed-posit numbers, used in weight quantization for the YOLOv8 architecture. We show that fixed-posit quantization achieves an improvement in latency and power utilization of $2.35\times, 3.6\times$ , and $9.02\times, 87.91\times$ compared to INT8 and FP32 for 65nm CMOS. Furthermore, this paper presents a synthetic DarkCOCO2017 validation dataset to test the OwlsEye segmentation performance in enhanced, original, and dark images. Our work highlights a novel real-time low-light VIS system and the potential of using Fixed-Posit quantization for edge AI applications.

关键词： Instance segmentation Quantization (signal) Image edge detection Surveillance Robot vision systems Streaming media Very large scale integration Real-time systems Robots Pipeline processing

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Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS

Optimal Placement of TDC Sensor for Enhanced Power Side-Chan...

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international conference on vlsi Design

作者： Debayan Das Majid Sabbagh Rana Elnaggar Guang Chen Sayak Ray Jason Fung Department of Electronic Systems Engineering Indian Institute of Science Bangalore India Intel Corporation Hillsboro OR USA

Power side-channel analysis (SCA) attack significantly threatens the security of cryptographic algorithms, which are otherwise computationally secure. Hence, evaluating the power SCA resiliency of a crypto implementation is critical before manufacturing. In this work, we utilize an FPGA-based framework to perform probeless power SCA leakage assessment, leveraging the prior works on the time-to-digital converter (TDC)-based voltage sensing. Most prior works use several TDC sensors spread throughout the FPGA fabric to sense the SCA leakage, which consumes a large area & is not a feasible solution when analyzing large IPs. Hence, in this work, we focus on the optimal placement of the TDC sensor on the fabric to minimize the total area. Specifically, this work performs a fundamental analysis of the impact of the power delivery network (PDN) on the TDC-based voltage sensing for power SCA leakage assessment of crypto IPs on an FPGA. Through spice-level PDN simulations & FPGA measurements, we obtain the optimal placement of the TDC to sense the maximum voltage fluctuations on the FPGA fabric. A dual-clock TDC with a shared clock tree is implemented to minimize the sensor area. The optimal placement of the dual-clock TDC circuit & a greedy gradient search heuristic to obtain the best TDC sampling point leads to $\sim 8 \times $ reduction in the sensor area compared to prior work using an Intel Stratix 10 FPGA. The proposed methodology is generic & can be applied to other TDC-based voltage sensing applications.

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Delay-Aware Control for Autonomous systems

Delay-Aware Control for Autonomous Systems

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international conference on vlsi Design

作者： Sumana Ghosh Indian Statistical Institute Kolkata India

The increasing demand for implementing multiple perception-based real-time applications (e.g., lateral control) onto autonomous systems is introducing new challenges into their control design paradigm, such as the delay-aware design of software controllers for such systems. This becomes more challenging when a variable delay occurs due to the variation of the workload of computation associated with the perception tasks, such as compute-intensive image processing tasks. For such systems, the traditional controller-design-followed-by-implementation paradigm fails to provide the desired control performance all the time. One such example is designing controllers by considering worst-case perception computation delay and thus providing sub-optimal control performance. The primary focus of this work is to address this issue by introducing a novel multi-rate control synthesis approach for autonomous systems. The idea is to apply multiple controllers and adaptively switch among them based on the current delay value without compromising the stability while improving the control performance. We report promising results w.r.t state-of-the-art approaches toward enhancing control performance and optimizing control cost.

关键词： embedded systems Autonomous systems Image processing Switches Very large scale integration Control systems Software

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