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Optimal Placement of TDC Sensor for Enhanced Power Side-Channel Assessment on FPGAS

Optimal Placement of TDC Sensor for Enhanced Power Side-Chan...

引用

international conference on vlsi Design

作者： Debayan Das Majid Sabbagh Rana Elnaggar Guang Chen Sayak Ray Jason Fung Department of Electronic Systems Engineering Indian Institute of Science Bangalore India Intel Corporation Hillsboro OR USA

Power side-channel analysis (SCA) attack significantly threatens the security of cryptographic algorithms, which are otherwise computationally secure. Hence, evaluating the power SCA resiliency of a crypto implementation is critical before manufacturing. In this work, we utilize an FPGA-based framework to perform probeless power SCA leakage assessment, leveraging the prior works on the time-to-digital converter (TDC)-based voltage sensing. Most prior works use several TDC sensors spread throughout the FPGA fabric to sense the SCA leakage, which consumes a large area & is not a feasible solution when analyzing large IPs. Hence, in this work, we focus on the optimal placement of the TDC sensor on the fabric to minimize the total area. Specifically, this work performs a fundamental analysis of the impact of the power delivery network (PDN) on the TDC-based voltage sensing for power SCA leakage assessment of crypto IPs on an FPGA. Through spice-level PDN simulations & FPGA measurements, we obtain the optimal placement of the TDC to sense the maximum voltage fluctuations on the FPGA fabric. A dual-clock TDC with a shared clock tree is implemented to minimize the sensor area. The optimal placement of the dual-clock TDC circuit & a greedy gradient search heuristic to obtain the best TDC sampling point leads to $\sim 8 \times $ reduction in the sensor area compared to prior work using an Intel Stratix 10 FPGA. The proposed methodology is generic & can be applied to other TDC-based voltage sensing applications.

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Delay-Aware Control for Autonomous systems

Delay-Aware Control for Autonomous Systems

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international conference on vlsi Design

作者： Sumana Ghosh Indian Statistical Institute Kolkata India

The increasing demand for implementing multiple perception-based real-time applications (e.g., lateral control) onto autonomous systems is introducing new challenges into their control design paradigm, such as the delay-aware design of software controllers for such systems. This becomes more challenging when a variable delay occurs due to the variation of the workload of computation associated with the perception tasks, such as compute-intensive image processing tasks. For such systems, the traditional controller-design-followed-by-implementation paradigm fails to provide the desired control performance all the time. One such example is designing controllers by considering worst-case perception computation delay and thus providing sub-optimal control performance. The primary focus of this work is to address this issue by introducing a novel multi-rate control synthesis approach for autonomous systems. The idea is to apply multiple controllers and adaptively switch among them based on the current delay value without compromising the stability while improving the control performance. We report promising results w.r.t state-of-the-art approaches toward enhancing control performance and optimizing control cost.

关键词： embedded systems Autonomous systems Image processing Switches Very large scale integration Control systems Software

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LAMA: A Latency Minimum Resource Constraint Accelerator for CNN Models

LAMA: A Latency Minimum Resource Constraint Accelerator for ...

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international conference on vlsi Design

作者： Sutirtha Bhattacharyya Fedrick Nongpoh Karthik Maddala E. Bhawani Eswar Reddy Chandan Karfa IACS Kolkata Nagaland University Indian Institute of Technology Guwahati

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Deep learning models, particularly Convolutional Neural Networks (CNNs), have become crucial in various domains due to their wide applications and exceptional performance. However, deploying these models on hardware often requires balancing between high performance and resource efficiency. This paper presents a novel framework, LAMA, to optimize specific layers in the CNN model by using optimization strategies that result in hardware-efficient accelerators. We introduce a template library for each layer, enabling designers to fine-tune area and latency trade-offs based on application-specific requirements. Our framework converts the CNN model to behavioral C and uses Large Language Models (LLMs) to make the code baseline synthesizable and then iteratively optimizes it using HLS guided by performance to hardware gain. This iterative process involves exploring the template library to meet predefined area constraints while minimizing latency. Experimental results demonstrate that our method significantly improves performance while holding to the hardware constraints, making it a viable solution for deploying computationally intense CNN models in resource-limited environments.

关键词： embedded systems Computational modeling Large language models Very large scale integration Libraries Space exploration Convolutional neural networks Iterative methods Optimization Hardware acceleration

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Hardware Implementation of Machine Vision System for Component Detection 7th

Hardware Implementation of Machine Vision System for Compone...

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7th international conference on Emerging Research in Computing, Information, Communication and applications, ERCICA 2022

作者： Smruthi, P. Prajna, K.B. John, Jibin G. Pasha, Aslam Taj VLSI and Embedded Systems Nitte Meenakshi Institute of Technology Bengaluru India Department of Electronics and Communication Nitte Meenakshi Institute of Technology Bengaluru India Research and Technology Development Group ACE Designers Ltd Bengaluru India

ISBN: (纸本)9789811954818

Inspection of components using machine vision technologies provides solution for quality and process control. This technique is used in various applications such as automotive, pharmaceutical, food and beverage, electronics, packages, process control and special application. The basic idea is to use machine vision technology in the industries to improve the production quality, reduce the scrap product due to non-conformity by controlling the manufacturing process through machine vision and also to prevent the value addition for scrap product in the subsequent stage of manufacturing process. Thus, designing and developing a machine vision system for component identification used the image processing algorithm. Inside the component, small circles which are of 0.5 diameter are detected using Hough circle detection. Graphical user interface was developed for visual representation of the image processing. The training model of the system is developed. © 2023, The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

关键词： Graphical user interfaces

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Lightweight Approximate Multiplier with Improved Accuracy in FPGA for Error Resilient Application

Lightweight Approximate Multiplier with Improved Accuracy in...

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international conference on vlsi Design

作者： Apurba Prasad Padhy Bishnu Prasad Das Electronics and Communication Engineering Indian Institute of Technology Roorkee Roorkee India

Approximate computing finds its application in image processing, machine learning, data mining and multimedia data processing. The paper proposes a scalable and lightweight $4\times 4$ approximate multiplier, which is designed to efficiently utilize the FPGA resources. We have divided the partial product matrix and selectively chosen the input variables for the effective usage of the LUTs and carry-chain. The bit error position due to the approximation is reduced by assigning the possible lower bits to ‘1’ which reduces the maximum error magnitude from 16 to 4. The proposed $4\times 4$ approximate multiplier achieves a reduction in area, power and latency of 26.7%, 57.6% and 60.1% respectively compared to the Xilinx multiplier IP. The proposed multiplier is used as a building block to implement $8\times 8$ approximate multipliers for image sharpening applications. We achieve a high PSNR value of 69.4 dB using the $8\times 8$ approximate multiplier.

关键词： embedded systems Input variables Multimedia computing Machine learning Very large scale integration Data processing Distance measurement

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Unguided Machine Learning-Based Computation Offloading for Near-Memory Processing

Unguided Machine Learning-Based Computation Offloading for N...

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international conference on vlsi Design

作者： Satanu Maity Manojit Ghose Avinash Kumar Anol Chakraborty Ankit Chakraborty Department of Computer Science and Engineering Indian Institute of Information Technology Guwahati Assam India Department of Computer Science and Engineering Jorhat Engineering College Assam India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Recent data-intensive applications encounter memory wall bottlenecks in the traditional processor-centric computing architecture due to the need for frequent and extensive off-chip data movement. The emerging 3D-enabled near-memory processing (NMP) is a potential solution where computation can be offloaded and performed near memory, eliminating the need for expansive off-chip data transfer. Recently, some crucial works in this context have been proposed that use a supervised machine learning approach that requires a well-labeled dataset, which necessitates creating a time-consuming simulation process. Furthermore, their major focus was on profiling and offloading the entire application to the NMP side, causing a sub-optimal performance because of the low processing power on the NMP cores. This paper presents an unguided machine-learning-based approach (UCO) for computation offloading in NMP architecture that offloads only the memory-intensive regions of an application. The approach extracts several application performance characteristics and creates two clusters using them - one for the CPU side and another for the NMP side. The proposed approach's effectiveness is demonstrated through a series of comprehensive experiments with standard simulators and dataintensive benchmark applications. The results indicate that UCO improves performance (1.31x and 1.10x), saves energy (16% and 12%), and reduces off-chip data transfer (78% and 73%) compared to conventional and state-of-the-art approaches.

关键词： Learning systems Energy consumption embedded systems Instruments Computer architecture Machine learning Very large scale integration Benchmark testing Data transfer Standards

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Evaluating the Impact of Transition Delay Faults in GPUs

Evaluating the Impact of Transition Delay Faults in GPUs

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international conference on vlsi Design

作者： Josie E. Rodriguez Condia Matteo Sonza Reorda Department of Control and Computer Engineering (DAUIN) Politecnico di Torino

This work proposes a method to evaluate the effects of transition delay faults (TDFs) in GPUs. The method takes advantage of low-level (i.e., RT- and gate-level) descriptions of a GPU to evaluate the effects of transition delay faults in GPUs, thus paving the way to model them as errors at the instruction level, which can contribute to the resilience evaluations of large and complex applications. For this purpose, the paper describes a setup that efficiently simulates transition delay faults. The results allow us to compare their effects with stuck-at-faults (SAFs) and perform an error classification correlating these faults as instruction-level errors. We resort to an open-source model of a GPU (FlexGripPlus) and a set of workloads for the evaluation. The experimental results show that, according to the application code style, TDFs can compromise the operation of an application from 1.3 to 11.63 times less than SAFs. Moreover, for all the analyzed applications, a considerable percentage of sites of the Integer (5.4% to 51.7%), Floating-point (0.9% to 2.4%), and Special Function unit (17.0% to 35.6%) can become critical if affected by a SAF or TDF. Finally, a correlation between the fault's impact from both fault models and the instructions executed by the applications reveals that SAFs in the functional units are more prone (from 45.6% to 60.4%) to propagate errors at the software level for all units than TDFs (from 17.9% to 58.8%).

关键词： embedded systems Correlation Codes Graphics processing units Very large scale integration Logic gates Software

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A Common Mode Insensitive Process Tolerant Sense Amplifier Design for In Memory Compute applications in 65nm LSTP Technology

A Common Mode Insensitive Process Tolerant Sense Amplifier D...

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international conference on vlsi Design

作者： Belal Iqbal Anuj Grover Harsh Rawat Indraprastha Institute of Information Technology Delhi New Delhi STMicroelectronics Greater Noida

Data transfer between processor and memory hierarchy constrains throughput of applications like Convolutional Neural Networks (CNNs) due to Von-Neumann bottleneck. In-Memory Compute (IMC) bypasses this bottleneck and enables much higher throughputs at constrained power budgets. Mixed Signal IMC SRAM architectures involve multiple wordline selection to enhance throughput and energy efficiency. Consequently bitlines discharge to much lower levels than a conventional SRAM. Conventional Sense Amplifiers (SAs) associated with bitlines are designed to operate at high common mode voltage and their offset increases as common mode voltage is reduced. In this work, we propose a common mode insensitive SA (CMI-SA) that has offset and delay that are independent of common mode voltage. The CMI-SA proposed in this work has a 3-sigma offset of 20–25 mV and a output delay of 200ps across a common mode range of 0.4V to 1.2V in an industrial 65nm Low Standby Power (LSTP) technology.

关键词： Power demand embedded systems Random access memory Voltage Very large scale integration Throughput Data transfer

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Biometric-based Finger-Vein Authenticating Device

Biometric-based Finger-Vein Authenticating Device

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2022 international conference on Edge Computing and applications, ICECAA 2022

作者： Prajwala, M.V. Sridevi, S. M.Tech VLSI & Embedded systems CMR Institute of Technology Bengaluru India Department of ECE CMR Institute of Technology Bengaluru India

ISBN: (数字)9781665482325

ISBN: (纸本)9781665482325

Personal data contained in consumer electronics devices are getting more and more valuable as the industry has been developing. Authentication is regarded as a leading technology in the field of security due to their various advantages, such as their ability to provide users with a secure and convenient way of accessing their information. Utilizing biometric methods involves using features like a person's face, voice, iris, hand geometry, fingerprint pattern, or veins on the back of their hands. The features used in the approaches may not always ensure confidentiality because they are observable on the outside of the human body. One must be overly secure with those information, as it highlights physical characteristics. This paper proposes the implementation of the finger-vein authentication device explained in three stages, with the first stage as image capturing, the second stage as feature extraction, and the third stage as authentication, using the OpenCV-python tool. © 2022 IEEE.

关键词： Authentication

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Proceedings of 2022 1st IEEE international conference on Industrial Electronics: Developments and applications, ICIDeA 2022

Proceedings of 2022 1st IEEE International Conference on Ind...

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1st IEEE international conference on Industrial Electronics: Developments and applications, ICIDeA 2022

ISBN: (纸本)9781665421492

The proceedings contain 44 papers. The topics discussed include: real-time dog detection and alert system using Tensorflow lite embedded on edge device;square wave generator using second generation current controlled conveyor (CCCII);ensembled transfer learning models for real time face recognition;a detailed review on battery cooling systems for electric vehicles;applications of machine learning in healthcare: an overview;vlsi implementation of accuracy configurable Radix-4 adder for digital image processing applications;a universal controller for grid-forming inverters in microgrid during islanding for low transient current;on projection of safe operation for grid-following inverters - grid parameter estimation;dynamic load inrush current mitigation in islanded microgrids powered by grid-forming inverters;a comparative review on electric vehicles and hybrid vehicles;and implementation of multi bit error detection and correction using low density parity check codes.

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