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检索条件"任意字段=Internation Conference on Embedded Systems and Applications/International Conference on VLSI"

共 884 条记录，以下是81-90 订阅

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Dynamic Scheduling for Event-Driven embedded Industrial applications

Dynamic Scheduling for Event-Driven Embedded Industrial Appl...

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IFIP international conference on Very Large Scale Integration (vlsi-SoC)

作者： Hossein Taji José Miranda Miguel Peón-Quirós Szabolcs Balasi David Atienza Embedded Systems Laboratory (ESL) EPFL Switzerland EcoCloud EPFL Switzerland Nespresso Switzerland

This paper addresses the optimization of embedded platforms to meet the computing and real-time requirements of cyber-physical systems and IoT applications, including embedded intelligence. In this context, schedulers are vital in enhancing processor utilization in industrial contexts. Although existing research has focused primarily on the schedulability of periodic tasks, event-driven tasks better represent these new embedded intelligence scenarios in the real world. This work explores static and dynamic scheduling policies within a general scenario and a specific case study based on an actual industrial application. The proposed dynamic scheduler has been integrated into the FreeRTOS kernel and has been employed to conduct all of our experiments on industrial products within the smart home domain. Our results show that, while we can respect real-time requirements, our proposed dynamic scheduling can improve the performance of event-driven applications by reducing missed task deadlines by up to 60 %. Moreover, we have also developed a lightweight version of our dynamic scheduler for industrial products that reduces average timing overhead for task selection and insertion by up to 34.7 % and memory overhead for task creation and list scheduling by up to 74.7 % compared to state-of-the-art static alternatives.

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Analyzing the Low Power Techniques in SRAM Cells at 45nm Node Technology

Analyzing the Low Power Techniques in SRAM Cells at 45nm Nod...

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international conference on vlsi systems, Architecture, Technology and applications (vlsi-SATA)

作者： Sandeep Dhariwal Aby K Thomas Reeba Korah Manasi S Dept. of ECE Alliance University Bengaluru India

ISBN: (数字)9798350362268

ISBN: (纸本)9798350362275

This paper presents Gated Vdd and MTCMOS techniques to achieve low power from the simulated static random-access memory (SRAM) cells. These techniques are implemented on 4 $T$ , 5 $T$ and 6 $T$ memory circuits based on CMOS logic. A significant research work is already in progress in the field of electronics embedded with memory with low power technology for system on chip ( $S$ oC). One of the most popular memory cells is 6 $T$ SRAM for microprocessor and micro controller architectures for low power applications. This research paper discusses CMOS based SRAM circuits and the parameters considered are power dissipation and delay. Along with 6 $T$ , the other two memory cells (4 $T$ and 5 $T$ ) are also simulated with modifications of the low power techniques. Delay and power dissipation are analyzed for the conventional designs and modified designs with low power methodology. Low power techniques like Gated Vdd and MTCMOS (Multi Threshold CMOS), have been instrumental in reducing the power consumption at 45nm node technology. All the designs are simulated and compared to ponder on best outcome. Comparative analysis shows that the MTCMOS based SRAM cells (specially 6 $T$ ) represent overall a better choice for reduced power dissipation and delay.

关键词： Noise systems architecture Logic gates Very large scale integration SRAM cells CMOS technology Delays

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FARAD: Automated Formal Verification of Approximate Restoring Array Dividers

FARAD: Automated Formal Verification of Approximate Restorin...

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international conference on vlsi Design

作者： Chandan Kumar Jha Khushboo Qayyum Muhammad Hassan Rolf Drechsler Institute of Computer Science University of Bremen Germany Cyber-Physical Systems DFKI GmbH Germany

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Approximate circuits have shown immense potential in the area of error-resilient applications. These circuits have tailored specifications depending on the resilience of an application towards the introduction of approximation. Formal verification is essential to guarantee the approximate circuit matches its tailored specifications. Hence, formal verification of approximate circuits has gained traction in recent years. However, most prior works focused on relaxed equivalence checking, i.e., only ensuring that the approximate circuits are within a specified error bound of the exact circuit. Recently, it was shown that formal error analysis is insufficient to ensure the approximate circuit matches its tailored functional specifications. However, this work was only limited to adders and multipliers. Hence, in this work, we propose a method called FARAD, that guarantees the approximate restoring array divider matches its functional specification. We use the functional specification of the approximate divider to generate the correctors. These correctors are then inserted in the approximate divider to generate the corrected divider. The corrected divider can then be formally verified by performing equivalence checking against a golden reference exact divider. If the corrected divider is equivalent to the golden reference divider, the approximate divider matches its functional specification. We generated more than half a million approximate dividers and verified them using FARAD.

关键词： embedded systems Error analysis Circuits Very large scale integration Adders Formal verification Resilience

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LogicWiSARD: Memoryless Synthesis of Weightless Neural Networks 33

LogicWiSARD: Memoryless Synthesis of Weightless Neural Netwo...

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33rd international conference on Application-specific systems, Architectures and Processors (ASAP)

作者： Miranda, Igor D. S. Arora, Aman Susskind, Zachary Villon, Luis A. Q. Katopodis, Rafael F. Dutra, Diego L. C. de Araujo, Leandro S. Lima, Priscila M., V Franca, Felipe M. G. John, Lizy K. Breternitz Jr, Mauricio Univ Fed Reconcavo Bahia Cruz das Almas Brazil UT Austin Austin TX USA Univ Fed Rio de Janeiro Rio de Janeiro Brazil Univ Fed Fluminense Niteroi RJ Brazil ISCTE Lisbon Portugal

ISBN: (数字)9781665483087

ISBN: (纸本)9781665483087

Weightless neural networks (WNNs) are an alternative pattern recognition technique where RAM nodes function as neurons. As both training and inference require mostly table lookups, few additions, and no multiplications, WNNs are suitable for high-performance and low-power embedded applications. This work introduces a novel approach to implement WiSARD, the leading WNN state-of-the-art architecture, completely eliminating memories and arithmetic circuits and utilizing only logic functions. The approach creates compressed minimized implementations by converting trained WNN nodes from lookup tables to logic functions. The proposed LogicWiSARD is implemented in FPGA and ASIC technologies to illustrate its suitability for edge inference. Experimental results show more than 80% reduction in energy consumption when the proposed LogicWiSARD model is compared with a multilayer perceptron network (MLP) of equivalent accuracy. Compared to previous work on FPGA implementations for WNNs, convolutional neural networks, and binary neural networks, the energy savings of LogicWiSARD range between 32.2% and 99.6%.

关键词： Weightless neural networks WiSARD FPGA vlsi

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A Wide Dynamic Range Differential Drive CMOS Rectifier for μWatts RF Energy Harvesting systems

A Wide Dynamic Range Differential Drive CMOS Rectifier for ...

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international conference on vlsi Design

作者： Chaya Hegde Arun Mohan Saroj Mondal Roy P. Paily Department of Electrical Electronics and Communication Engineering Indian Institute of Technology Dharwad Karnataka Department of Electronics and Electrical Engineering Indian Institute of Technology Guwahati Guwahati

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

This paper presents a fully self-biased differential drive rectifier with a wider dynamic range for low-power energy harvesting applications. The proposed rectifier incorporates a self-bias scheme to minimize reverse conduction losses without increasing forward conduction losses. This in turn increases the dynamic range (DR), over which high power conversion efficiency (PCE) is achieved. The proposed rectifier is realized in a 65-nm standard CMOS technology, and post-layout results achieve a 60.5% peak PCE at −8.9 dBm input power and a dynamic range of ~ 14 dB. The post layout simulation results show 74% improvement in DR compared to the conventional cross-coupled rectifier at 953 MHz with a $10\ \mathbf{k}\Omega$ load.

关键词： Radio frequency Simulation Rectifiers Dynamic range Very large scale integration CMOS technology Topology Energy harvesting Power conversion Standards

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AdapTTA: Adaptive Test-Time Augmentation for Reliable embedded ConvNets 29

AdapTTA: Adaptive Test-Time Augmentation for Reliable Embedd...

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29th IFIP/IEEE international conference on Very Large Scale Integration (vlsi-SoC)

作者： Mocerino, Luca Rizzo, Roberto G. Peluso, Valentino Calimera, Andrea Macii, Enrico Politecn Torino Dept Control & Comp Engn I-10129 Turin Italy

ISBN: (纸本)9781665426145

Convolutional Neural Networks (ConvNets) are trained offline using the few available data and may therefore suffer from substantial accuracy loss when ported on the field, where unseen input patterns received under unpredictable external conditions can mislead the model. Test-Time Augmentation (TTA) techniques aim to alleviate such common side effect at inference-time, first running multiple feed-forward passes on a set of altered versions of the same input sample, and then computing the main outcome through a consensus of the aggregated predictions. Unfortunately, the implementation of TTA on embedded CPUs introduces latency penalties that limit its adoption on edge applications. To tackle this issue, we propose AdapTTA, an adaptive implementation of TTA that controls the number of feed-forward passes dynamically, depending on the complexity of the input. Experimental results on state-of-the-art ConvNets for image classification deployed on a commercial ARM Cortex-A CPU demonstrate AdapTTA reaches remarkable latency savings, from 1.40x to 2.21x, and hence a higher frame rate compared to static TTA, still preserving the same accuracy gain.

关键词： Adaptive systems Program processors embedded systems Image edge detection Very large scale integration Data models Complexity theory

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Implementation of Efficient Serial Architecture for Prince Block Cipher with Enhanced Security

Implementation of Efficient Serial Architecture for Prince B...

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2023 international conference on System, Computation, Automation and Networking, ICSCAN 2023

作者： Teja, Pusam Ravi Sasamal, Trailokya Nath School of Vlsi Design and Embedded Systems Nit Kurukshetra Haryana India Nit Kurukshetra Department of Electronics and Communication Engineering Haryana India

ISBN: (纸本)9798350315127

The Internet of Things (IoT) has seen a tremendous rise in usage over the past few years in a variety of fields. Many restrictions, including power consumption and resource scarcity, have evolved as a result of the proliferation of IoT applications. An increasingly important requirement for system dependability is the security of linked devices.. They were created and proposed a number of light-weight cryptography techniques for these. In this paper PRINCE cipher is implemented in serial approach to replace the PRESENT cipher which uses less power when compared with PRESENT cipher along with the use of DLFSR for generating the key and s-box values. The PRINCE cipher using serial approach is Implemented Utilizing the Vivado 16.2 design package from Xilinx in Verilog level along with the PRESENT cipher. The PRINCE cipher is the improvement in terms of power consumption of $195{{\ mW}}$ when compared with the PRESENT cipher which uses 242 $\text{mW}$. The serial approach in PRINCE cipher uses the 16 bits of data path encryption instead of all the 64 bits at a time in this paper by efficient hardware serial architecture approach. Comparatively to other hardware applications already in use, PRINCE provides faster throughput of 572 Mbps when compared with 338 Mbps from PRESENT cipher. The keys generation and s-box values are generated with Dynamic LFSR(linear feedback shift register) to enhance the security of PRINCE cipher from brute force attacks.. © 2023 IEEE.

关键词： Electric power utilization

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Design and Implementation of BIST Architecture for low power vlsi applications using Verilog

Design and Implementation of BIST Architecture for low power...

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Smart systems for applications in Electrical Sciences (ICSSES), international conference on

作者： Aadesh Gonda Bharathi S. H VLSI and Embedded Systems REVA University Bangalore (School of ECE) REVA University Bangalore

The proposed BIST architecture focuses on minimizing power consumption during the testing phase while maintaining high fault coverage. It leverages the capabilities of the Verilog hardware description language to model and simulate the design. The research investigates various power reduction techniques, including test pattern compression, selective clock gating, and power-aware test scheduling, to optimize power consumption during testing. This research paper presents the design and implementation of a Built-In Self-Test (BIST) architecture specifically tailored for low-power Very Large-Scale Integration (vlsi) applications. The increasing demand for energy-efficient electronic devices and the proliferation of portable systems have necessitated the development of power-aware design techniques. BIST, a onchip testing technique, plays a crucial role in ensuring the quality and reliability of integrated circuits. The implementation is performed on a field-programmable gate array (FPGA) platform, demonstrating the feasibility and practicality of the proposed design. The research contributes to the field of low-power vlsi design by providing a comprehensive BIST architecture that effectively reduces power consumption during testing. The proposed design is compatible with standard Verilog synthesis and is readily applicable to a wide range of low-power vlsi applications. The findings from this study can guide designers in developing energy-efficient and reliable integrated circuits, promoting sustainability, and extending battery life in portable devices.

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Design and Mitigation Techniques of Radiation Induced SEEs on Open-Source embedded Static RAMs 1

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29th IFIP WG 10.5/IEEE international conference on Very Large Scale Integration (vlsi-SoC)

作者： Azimi, Sarah De Sio, Corrado Portaluri, Andrea Sterpone, Luca Politecn Torino Dipartimento Automat & Informat Turin Italy

ISBN: (数字)9783031168185

ISBN: (纸本)9783031168185;9783031168178

Static RAM modules are widely adopted in high performance systems. Single Event Effects (SEEs) resilient memories are required in many embedded systems applied in automotive and aerospace applications to increase their overall resiliency against SEEs. The current SEE resilient SRAM modules are obtained by applying radiation-hardened by design solutions which leads to elevated area overhead and difficulty to tune the resiliency capability with respect to the particle's radiation profile. To overcome these limitations, we propose a methodology for the analysis and mitigation of embedded SRAMs generated by the OpenRAM memory compiler. A technology-oriented radiation analysis tool is presented to support the interaction of the charged radiation particles with the SRAM layout and depict the sensitive transistors of the SRAM memory. A selective duplication of the sensitive transistors has been applied to the 6T-SRAM cell designed at the layout level. The designed cell is included in the OpenRAM compiler and used to generate amitigated 8 Kb SRAM-bank, a DMA interface is also added to the bank in order to evaluate the interface capabilities. We evaluated the SEEs sensitivity by comparative simulation-based radiation analysis observing a reduction more than 6 times with respect to the original 6T-SRAM cell for the SEE sensitivity at high energy heavy ions particles, with negligible degradation of operations margins and power consumption and area overhead of less than similar to 4%. The performance of the developed OpenRAM module has been also evaluated considering its application on a neural network behavioral model that demonstrate the feasibility of the proposed solution on large scale memory block circuitry.

关键词： Radiation effects Single event effects SRAM memory Transistor layout

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A Novel Dual Output Schmitt Trigger Using Second Generation Voltage Controlled Conveyer 2

A Novel Dual Output Schmitt Trigger Using Second Generation ...

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2nd IEEE international conference on Intelligent Technologies, CONIT 2022

作者： Anand, Abhinav Pandey, Rajeshwari Delhi Technological University Vlsi Design and Embedded Systems Delhi India Delhi Technological University Dept. of Electronics and Communication Delhi India

ISBN: (数字)9781665484077

ISBN: (纸本)9781665484077

This paper presents a comprehensive study on a particular kind of conveyor called second-generation voltage conveyor (VCII). This building block is based on voltage conveying concept and is the dual of second-generation current conveyor (CCII). It has been seen that VCII is a very useful block in those configurations where CCII is limited, in terms of number of active blocks. Second generation voltage conveyers (VCII) are being potentially explored to implement variety of applications in the analog domain. The results of this work are helpful in choosing the best building block design for VCII to implement a novel approach to designing Schmitt trigger using second generation voltage conveyers. © 2022 IEEE.

关键词： Comparators (optical)

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