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international Technical conference on circuits/systems, Computers, and Communications (ITC-CSCC)

作者： Fukumura, Ryuto Yasutake, Yoshihiro Inenaga, Kentaro Ishida, Toshikazu Kyushu Sangyo Univ Grad Sch Informat Sci Fukuoka Japan Kyushu Sangyo Univ Fac Sci & Engn Fukuoka Japan

ISBN: (纸本)9798350379068;9798350379051

In recent years, the rapid progress of information technology has made it essential for engineers to understand the operating principles of computers that form the technological foundation. Therefore, we have proposed a system for computer architecture education called the Kyutech Easily Reconstructive Naked Educational (KERNEL) Computer. KERNEL is a model computer designed specifically for educational purposes, allowing users to write assembly code and providing a visually intuitive representation of the CPU's internal processing during code execution. The purpose of this study is to implement the KERNEL system as an application where the CPU behavior is simulated and graphically displayed to aid learners' understanding. This paper describes the system's design and implementation, using the developed application as a use case example.

关键词： computer architecture education simulation system design

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Increasing the Efficiency of Hierarchical Fault simulation through Functional Fault Clustering 67

Increasing the Efficiency of Hierarchical Fault Simulation t...

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67th IEEE international Midwest Symposium on circuits and systems (MWSCAS)

作者： Modala, Nikhil Sagar Balasubramanian, Lakshmanan Parekhji, Rubin Ozev, Sule Arizona State Univ Sch ECEE Tempe AZ 85281 USA Texas Instruments Banglore Bengaluru India

ISBN: (纸本)9798350387186;9798350387179

Due to increasing defect rates and increasing complexity of mixed-signal circuits, evaluation of fault coverage for a given input, also known as fault simulation, has become essential. Established fault models in the analog domain are based on detailed transistor-level netlists. Existing fault simulation tools inject and analyze fault responses at this level of detail. However, extending fault simulation to large circuits, especially when digital signals and/or frequency translation is involved, can be difficult due to the nature of simulations. Designers work with models at higher abstraction levels where simulations are more efficient. Hierarchical fault simulation intends to bridge the gap between transistor-level fault simulations and the evaluation of fault manifestation at the system level. Hierarchical fault simulation aims to capture fault response behavior at the sub-block level and propagate this response to the system level using high-level models. In this way, the efficiency of fault simulations can be increased considerably without sacrificing the accuracy. In this paper, we aim to increase the fault simulation efficiency further by dropping some faults to be simulated through functional equivalency at the sub-block level. We use a fault clustering approach that is based on the fault response model parameters and simulate only a representative fault model for each cluster. The method is applied to a comparator model that is used in a flash Analog-to-Digital Converter (ADC) design. Experimental results show that the hierarchical fault simulation time can be reduced by a factor of 8-10 without sacrificing the fault simulation accuracy.

关键词： Fault response modeling fault injection machine learning based hierarchical approach analog circuits

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Physical Design of RISC-V based system-on-Chip using OpenLane 20

Physical Design of RISC-V based System-on-Chip using OpenLan...

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20th Asia-Pacific conference on circuits and systems

作者： Fauzan, Muhammad Yanuarsyah, Raihan Fadhil Hibatullah, Muhammad Hanif Arisaputra, Radithya Syafalni, Infall Sutisna, Nana Adiono, Trio Ikeda, Makoto Bandung Inst Technol Sch Elect Engn & Informat Bandung Indonesia Bandung Inst Technol Univ Ctr Excellence Microelect Bandung Indonesia Univ Tokyo Sch Engn Syst Design Lab Tokyo Japan Univ Tokyo Grad Sch Engn Tokyo Japan

ISBN: (纸本)9798350378788;9798350378771

Open-source tools for designing integrated circuits are crucial for electrical engineering students. However, more references are necessary to promote the tools to the academic environments. This paper presents design and implementation of a PicoSoC (Pico system-on-Chip) using the OpenLane automated VLSI flow. The PicoSoC comprises several modules, including the PicoRV32 CPU, UART and SPI peripherals, and memory blocks. The design methodology encompasses RTL simulation, macro hardening, core hardening, full-chip hardening, and gate-level simulation. The results indicate successful physical design and functional verification, demonstrating that the gate-level simulation outputs align with those from RTL simulation. The work is useful for designing the physical layout of digital circuits, SoC architecture development, and also promoting open-source IC design tools in academic environments.

关键词： PicoSoC OpenLane PicoRV32 RTL simulation Gate Level simulation VLSI Design Physical Design

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Application of Coupled Battery Model of Thermal and Electrical Equivalent circuits to Realize Long-life Battery Energy Storage system

Application of Coupled Battery Model of Thermal and Electric...

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international Technical conference on circuits/systems, Computers, and Communications (ITC-CSCC)

作者： Kondo, Atsumi Itou, Yoshimitsu Toshiba Co Ltd Battery Div Battery Engn Dept Battery Engn Grp 2 Kawasaki Kanagawa Japan Toshiba Co Ltd Battery Div Battery Syst Engn Dept Battery Syst Engn Grp 2 Kawasaki Kanagawa Japan

ISBN: (纸本)9798350379068;9798350379051

This paper introduces Battery Management system (BMS), which is the core function of BESS (Battery Energy Storage system) for microgrid demand adjustment and power storage functions. To obtain long-life BESS, battery degradation estimation should be performed, and appropriate cooling method for the end-of-life performance should be selected. In the limited design and development periods, simulation models with short calculating time and practical accuracy are required. This paper proposes a coupled model of Electrical equivalent Circuit Model (ECM) which simulates battery degradation, and a thermal circuit model which simulates heat transfer in modules to select appropriate cooling methods. By representing the anisotropic thermal conductivity within the battery cell and the heat transfer around the battery module as thermal resistances and composing the thermal resistances corresponding to the components within the battery module, it succeeds to reduce the model size and calculation time. In this proposed model, the number of required function blocks has been reduced by 98.6 % compared to the number of conventional battery module model on MathWorks Simulink (R) and Simscape (R). The calculation time is also reduced by 98.9 % of the conventional battery module model under the same Personal Computer environment. In the verification of proposed model, with the test current operational pattern in which the RMS C rate is 1.6 (C), the State of Charge (SOC) is ranged from 60 % to 90 %, and is repeated for 1,000 days, the maximum error rate between the measured and simulated State of Health Resistance (SOHR) with this model is 5.0 %.

关键词： Battery Energy Storage system (BESS) Battery Management system Module Degradation simulation Equivalent Electrical Circuit Model (ECM) Thermal Circuit

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simulation of transients in an autonomous power system considering the generator and transformer magnetic core saturation

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ENERGY REPORTS 2023年 9卷 444-451页

作者： Glazyrin, Gleb Mitrofanov, Nikolay Rusina, Anastasia Fyodorova, Viktoriya Arestova, Anna Novosibirsk State Tech Univ Dept Power Stn Novosibirsk 630073 Russia Novosibirsk State Tech Univ Dept Automated Power Syst Novosibirsk 630073 Russia

The paper considers transients in an autonomous power system consisting of a generator, a transformer, and a general load. The numerical method for simulating transients includes the possibility of the asymmetry of stator windings and magnetic core saturation of a generator and a transformer. The asymmetry is usually observed under synchronous machine faults such as turn-to-turn short circuits in the stator winding. The method is based on the solution of differential equations for the equilibrium of electromotive force and voltage drops in windings in phase coordinates in combination with the rotor rotation equation. In this case, a circuit of each phase stator winding is described by an equation that considers the difference in phase parameters. The mathematical model is developed in MATLAB. The model includes an unequal number of turns in phase windings that allows simulating the turn-to-turn short circuits without considering the occurrence of additional short-circuited circuits. The analysis of simulation results was performed under no-load operating conditions and in the presence of load. The obtained results demonstrated the influence of the saturation of magnetic systems on the parameters of normal and abnormal operating conditions in the power system. (c) 2022 The Author(s). Published by Elsevier Ltd. This is an open access article under the CC BY license (http://***/licenses/by/4.0/).

关键词： Autonomous power system Synchronous machine Asymmetry Electromagnetic transients Matlab simulation

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simulation And Analysis of Bit Error Rate in Optical Fiber Communication Using Optisystem 7

Simulation And Analysis of Bit Error Rate in Optical Fiber C...

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7th international conference on Devices, circuits and systems (ICDCS)

作者： Hugar, Nikhil R. Piruthiviraj, P. Maleeha Dhinesh, V New Horizon Coll Engn Dept Elect & Commun Bengaluru India

ISBN: (纸本)9798350350470;9798350350487

This paper presents a comprehensive simulation and analysis of Bit Error Rate (BER) in optical fibre communication networks that make use of Optisystem software. [5, 6] The growing need for high-speed and reliable data transmission necessitates a thorough understanding of BER performance in optical networks. Optisystem, a powerful simulation tool, facilitates the emulation of diverse optical communication scenarios. The study focuses on the critical factors influencing BER, including optical power levels, attenuation, dispersion, noise, transmission distances, and component quality. Through Optisystem simulations, various BER measurement techniques such as eye diagrams, Bit Error Rate Testers (BERTs), and 2D graphs are employed to evaluate system performance accurately. Key aspects of this research include the utilization of Continuous Wave (CW) lasers for generating stable optical signals, modulation techniques for data pattern simulation, and the analysis of synchronization methods to ensure precise BER measurements. The outcomes of these simulations offer insights into optimizing systems for optical fiber communication lower BER, thereby enhancing data reliability and transmission efficiency. This study showcases the efficacy of Optisystem as a valuable tool for investigating and optimizing BER in optical fiber communication networks.

关键词： BER improvement EYE diagram red line graph PRBS NRZ MZ modulator

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Design on distributed real-time simulation design based on RTX 4

Design on distributed real-time simulation design based on R...

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4th international conference on Electronics, circuits and Information Engineering, ECIE 2024

作者： Lu, Nan Deng, Lewu Zhang, Lei Du, Wei Ming, Qiu Meng, Ziyuan He, Hongtao CO. LTD. ChengDu China Beihang University BeiJing China

ISBN: (纸本)9798350388312

In response to the large-scale and complex system level distributed real-time simulation problem of airplanes, this paper designs the overall structure of a distributed real-time simulation system based on RTX to facilitate the electromagnetic simulation test analysis of airplanes and their onboard subsystems. The system has a certain degree of universality and scalability, and corresponding software and hardware modules can be added or modified according to simulation test requirements, greatly improving the flexibility and efficiency of electromagnetic simulation tests. Moreover, the use of Windows collaborative RTX operating system provides assurance for the reliability and real-time performance of the simulation test system. This provides an effective and feasible method for electromagnetic simulation test analysis of large and complex systems such as airplanes. © 2024 IEEE.

关键词： Software testing

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simulation Research on Dynamic Characteristics of High-Pressure Variable Piston Pump on AMESim simulation Platform Based on Human-Computer Interaction Technology 2

Simulation Research on Dynamic Characteristics of High-Press...

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2nd IEEE international conference on Integrated circuits and Communication systems, ICICACS 2024

作者： Ma, Chao Beijing Electronic Technology Vocational College Beijing China

ISBN: (纸本)9798350317558

The dynamic characteristics of the high-pressure variable plunger pump have an important impact on the performance and efficiency of the system, but the current plunger pump has a long dynamic response time and cannot improve the steady-state error of the system well. In this article, the AMESim simulation platform based on human-computer interaction technology is used. By establishing a mathematical model of a high-pressure variable plunger pump and considering various parameters and influencing factors of its dynamic characteristics, the simulation research of its dynamic characteristics is realized. Through the simulation and analysis of the plunger pump under different working conditions, its dynamic response and performance under different working conditions are studied. Through experiments, it is concluded that the dynamic response time of the method in this article is 6-1.2s, and the system can adapt to changes in the input signal faster. © 2024 IEEE.

关键词： AMESim simulation Platform Dynamic Characteristics simulation Dynamic Response Time High-Pressure Variable Piston Pump

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Interface circuits for Piezoelectric Polyvinylidene Fluoride (PVDF) Films 21

Interface Circuits for Piezoelectric Polyvinylidene Fluoride...

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21st international system-on-Chip Design conference, ISOCC 2024

作者： Fabian, Carl Lester Rosales, Marc Hizon, John Richard Electrical and Electronics Engineering Institute University of the Philippines Diliman Philippines

ISBN: (纸本)9798350377088

This work explores the modeling of polyvinylidene fluoride (PVDF) films based on their physical characteristics. Additionally, it highlights the performance of various circuit interfaces used with PVDF films through both simulation and hardware implementation. simulation results indicate that ideal specifications are met;however, in practical applications, environmental factors must be considered as they affect the electrical characteristics of PVDF films and, consequently, the performance of the entire circuitry. © 2024 IEEE.

关键词： Timing circuits

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CCacheSim: A Circuit-Architecture Cross-Level simulation Framework for SRAM-Based In-Cache Computing system Evaluation 42

CCacheSim: A Circuit-Architecture Cross-Level Simulation Fra...

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42nd international conference on Computer Design

作者： Zhong, Baiqing Wang, Mingyu Zhang, Yicong Li, Xiaojie Yu, Zhiyi Sun Yat Sen Univ Sch Microelect Sci & Technol Guangzhou Peoples R China

ISBN: (纸本)9798350380415;9798350380408

SRAM-based Compute-In-Memory (CIM) circuits have demonstrated significant performance and energy efficiency advantages. Although numerous frameworks or tools have emerged for simulating CIM-based systems, most frameworks are tailored for specific DNN accelerators and rarely consider SRAM-CIM solutions in general processor systems because it is difficult to establish an effective mechanism to build the CIM data path to integrate the SRAM-CIM module that is tightly coupled with the cache hierarchy into the system. To address this problem, we propose a circuit-architecture cross-level simulation framework named CCacheSim for in-cache computing system. CCacheSim integrates the simulation of SRAM-CIM circuit timing and energy consumption characteristics, providing circuit-level accuracy evaluation support for in-cache computing system simulations. For the circuit level, the SRAM-CIM model can automatically generate a circuit-level netlist and conduct accurate simulation through corresponding configurations, thus balancing accuracy and agility for early design exploration. For the architectural level, to efficiently support the portable integration of SRAM-CIM module to in-cache computing system, a configurable hardware programming interface is implemented within the cache model to manage the interaction of the control stream between processor and cache for CIM tasks. Moreover, a request queue based access mechanism is proposed to ensure the completeness of the operands required by CIM tasks. To validate the proposed framework, CCacheSim is implemented to simulate varying configurations of in-cache computing systems and SRAM-CIM modules. The results prove that CCacheSim can conduct accurate performance and energy consumption evaluation for given processor architecture with given CIM module. CCacheSim can support flexible and effective design space exploration for in-cache computing system.

关键词： Compute-In-Memory(CIM) SRAM in-cache computing simulation framework

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