The proceedings contain 100 papers. The topics discussed include: interference-aware DNN serving on heterogeneous processors in edge systems;SuperMap: high-performance and flexible memory-mapped IO for fast storage de...
ISBN:
(纸本)9798350380408
The proceedings contain 100 papers. The topics discussed include: interference-aware DNN serving on heterogeneous processors in edge systems;SuperMap: high-performance and flexible memory-mapped IO for fast storage device;fine-grained shared cache interference analysis using basic block’s execution time;MemSort: in-memory sorting architecture;VEGA: implementing a versatile and efficient deep learning processor with graph-based ALU;vCLIC: towards fast interrupt handling in virtualized RISC-V mixed-criticality systems;persistent spiral storage;SATL: a spatial architecture rapid prototyping framework for irregular applications acceleration;and private tensor freezing for an efficient federated learning with homomorphic encryption.
The proceedings contain 88 papers. The topics discussed include: GIM: versatile GNN acceleration with reconfigurable processing-in-memory;Cerasure: fast acceleration strategies For XOR-based erasure codes;leveraging f...
ISBN:
(纸本)9798350342918
The proceedings contain 88 papers. The topics discussed include: GIM: versatile GNN acceleration with reconfigurable processing-in-memory;Cerasure: fast acceleration strategies For XOR-based erasure codes;leveraging firmware reverse engineering for stealthy sensor attacks via binary modification;a compressed and accurate sparse deep learning based workload-aware timing error model;transcend adversarial examples: diversified adversarial attacks to test deep learning model;REMU: enabling cost-effective checkpointing and deterministic replay in FPGA-based emulation;ACET: an adaptive clock scheme exploiting comprehensive timing slack for reconfigurable processors;and ImprLM: an improved logarithmic multiplier design approach via iterative linear-compensation and modified dynamic segment.
Recently, since the miniaturization of transistors is approaching physical limitation, processor performance improvement is slow down. Anymore, Moore's Law cannot be expected. Therefore, we have been developing a ...
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ALU is the fundamental building block of many processors like Central Processing Unit(CPU), Floating point Unit (FPU's), Graphical Processing Unit(GPU's). ALUs are used in digital computers, and they are a com...
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Persistent Memory (PM) offers both byte-address ability and non-volatility, making it well-suited for accelerating B+-Tree indexes. However, existing persistent B+-Tree indexes face significant performance challenges ...
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The increasing complexity of satellite tasks and functions imposes higher demands on the generalization and modularization of onboard computer software design. While the introduction of the Linux operating system addr...
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The fly back converter (FBC) is a popular choice for low-power applications such as Televisions, Standby supply of power for computers, Mobile device chargers, unmanned aerial vehicles, Lighting system due to its perf...
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The rise of portable devices in our everyday lives has made power optimization a critical focus in contemporary vlsi technology. In recent years, static random-access memory (SRAM) has gained popularity due to its sup...
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The design of a 32-bit datapath allows computer architect to simulate possible extents for RISC based processors to other form of operations needed for complex applications. The study aims to analyse the device accura...
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ISBN:
(纸本)9798350370058;9798350370164
The design of a 32-bit datapath allows computer architect to simulate possible extents for RISC based processors to other form of operations needed for complex applications. The study aims to analyse the device accuracy and its functionality such that Application Specific-FPGA (AS-FPGA) can be constructed for future use or applications and become part of a fully functional device. In order to have a fully functional datapath and control unit, the operations intended for such application must have an accurate data value to be used in the data processing;instructions in the arithmetic and logic operations, flag bits, memory, and register files that are directed by the control unit and is controlled using code bit as part of the machine code. The design must have functional units such as the control unit, program counter, instruction memory, register file, sign extender module, multiplexers, arithmetic logic unit (ALU), and the data memory. The study was successfully designed a 32-bit single-cycle datapath and simulate RISC based instructions in XILINX-ISE and successfully implemented the design in the DE0-nano FPGA targeting the Cyclone-IV FPGA. The testing for accuracy and functionality with the two approach resulted to an overall success rate which means that both approach in the simulation and implementation correspond with the same output.
Multiplexer is a basic block of many processors or ready to use board like FPGA's. This work explores multiplexer design with different technology and logic style for improvement in performance. Conventional CMOS ...
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