Multi-port cache is used in disk arrays to realize interface processors connecting in switch and to make disk arrays high band and high expandability. To improve the performance of disk arrays, a good cache replacemen...
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ISBN:
(纸本)076952432X
Multi-port cache is used in disk arrays to realize interface processors connecting in switch and to make disk arrays high band and high expandability. To improve the performance of disk arrays, a good cache replacement algorithm is needed in the cache. In this paper, we propose a new algorithm named the write-prior partitioning least recently used (WPP-LRU) algorithm, which distinguishes the ports and distinguishes the write blocks from the read blocks in the cache. The LRU algorithm is only used to the read blocks in each port and some especial operations are performed for all write blocks in the cache. A simulation model is developed and the simulation results show that the WPP-LR U algorithm can improve the performance of disk arrays by reducing the hit service time remarkably while it keeps the same hit ratio as the standard LRU The WPP-LRU algorithm has a good expandability because some good algorithms can be used in the read blocks of each port to improve the hit ratio, such as the LRU-K algorithm, the 2-Q algorithm and so on, and this will not change the idea of the WPP-LR U algorithm.
The development of educational technology in the 'Internet +' era fully embodies the philosophy of life-long education, but also brought opportunities and challenges to the development of continuing education....
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With the improvement of the research and development level of mechanical control systems, its application scope has also been continuously expanded. Simply relying on traditional mechanical control methods and product...
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In the computer field, graphics and image processing technology has occupied a relatively key core position in computertechnology. Image processing not only provides convenience for people's daily life, but also ...
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This study delves into the transformative potential of EEG-based hand gesture recognition for enhancing human-computer interaction. Through sophisticated classification techniques, specifically ensemble methods, EEG s...
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ISBN:
(纸本)9798350386813;9798350386820
This study delves into the transformative potential of EEG-based hand gesture recognition for enhancing human-computer interaction. Through sophisticated classification techniques, specifically ensemble methods, EEG signals are analyzed to accurately identify hand gestures. The research highlights the Bagged SVM classifier's remarkable efficiency, reaching an accuracy rate of 96.8%. This achievement emphasizes the practicality and reliability of EEG signals for creating intuitive user interfaces, with promising applications in virtual reality and assistive technology. By effectively linking neural signals to computational interpretations, the study marks a significant leap in neurotechnology and human-computer interfaces, setting new standards for future research and development in EEG-based gesture recognition systems.
Rapid growth in computer graphics has created a vacuum of opportunity. As the industry expands to fulfill new needs, activity is often marked by fragmented efforts to define common ground by establishing standards. Th...
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Rapid growth in computer graphics has created a vacuum of opportunity. As the industry expands to fulfill new needs, activity is often marked by fragmented efforts to define common ground by establishing standards. This paper examines the development of several computer graphics standards, reviews their initial application, and highlights comparative areas. It is a tool by which readers can gain a broad overview of several ongoing standard developments.
The semiconductor industry keeps seeking for reducing the design time and efforts in modern integrated circuit implementation, which often incorporates billions of transistors. Among the entire design flow, back-end d...
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ISBN:
(纸本)9781665423243
The semiconductor industry keeps seeking for reducing the design time and efforts in modern integrated circuit implementation, which often incorporates billions of transistors. Among the entire design flow, back-end design involving the physical implementation takes a significant portion of the design time. Recent advances in GPU acceleration bring new opportunities to speedup the design closure. In this tutorial, we review the efforts in literature and current status on accelerating the back-end design automation algorithms. We summarize the challenges in the key design stages such as placement, routing, and timing anaylsis, and provide several case studies on how to enable massive parallelism in practice.
Artificial intelligence is a computer science discipline formed on the basis of information network and data processing technology, which involves various fields such as economy and politics. It is highly intelligent ...
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The development and popularization of big data technology bring more convenience to users, it also bring a series of computer network security problems. Therefore, this paper will briefly analyze the network security ...
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