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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

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Algorithmic and memory optimizations on multiple application mapping onto FPGAs 17

Algorithmic and memory optimizations on multiple application...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sidiropoulos, Harry Koutras, Ioannis Soudris, Dimitrios Siozios, Kostas Natl Tech Univ Athens Sch Elect & Comp Engn Zografos Greece Aristotle Univ Thessaloniki Dept Phys Thessaloniki Greece

ISBN: (纸本)9781538634370

Field Programmable Gate Arrays (FPGAs) offer a low power flexible accelerator alternative due to their inherent parallelism. Reprogrammability, although its their key feature, it is used almost exclusively on design time due to the constrains imposed by the modern CAD tools that require even days to run and tens of GB of RAM. In order to effectively utilize FPGAs on run time we propose a novel methodology and the supporting toolflow that enable efficient mapping of multiple applications onto heterogeneous FPGAs. With the use of a floorplanning step, memory optimizations and custom memory allocators, we alleviate the constrains imposed by CAD tools, and provide a proof of concept that application mapping onto FPGAs can be done on run time. Experimental results prove the efficiency of the introduced solution, as we achieve application's mapping 40x faster on average compared to a state-of-art approach, without performance degradation and with 12x on average reduced memory usage.

关键词： Field programmable gate arrays Tools Kernel Random access memory Memory management Optimization Hardware Field programmable gate arrays random access machine Store management computer hardware Mapping onto Runtime Kernel Memory Memory design year

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Platform-aware Dynamic Data Type Refinement Methodology for Radix Tree Data Structures 15

Platform-aware Dynamic Data Type Refinement Methodology for ...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Papastergiou, Thomas Papadopoulos, Lazaros Soudris, Dimitrios Natl Tech Univ Athens Sch Elect & Comp Engn GR-10682 Athens Greece

ISBN: (纸本)9781467373111

Modern embedded systems are now capable of executing complex and demanding applications that are often based on large data structures. The design of the critical data structures of the application affects the performance and the memory requirements of the whole system. Dynamic Data Structure Refinement methodology provides optimizations, mainly in list and array data structures, which are based on the application's features and access patterns. In this work, we extend various aspects of the methodology: First, we integrate radix tree optimizations. Then, we provide a set of platform-aware data structure implementations, for performing optimizations based on the hardware features. The extended methodology is evaluated using a wide set of synthetic and real-world benchmarks, in which we achieved performance and memory trade-offs up to 29.6%. Additionally, Pareto optimal data structure implementations that were not available by the previous methodology, are identified with the extended one.

关键词： Data structures memory requirements Root Radix Base of a number system tree data structures embedded systems data types Refining Not Available computer hardware

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MPSoCSim: An extended OVP Simulator for modeling and Evaluation of Network-on-Chip based heterogeneous MPSoCs 15

MPSoCSim: An extended OVP Simulator for Modeling and Evaluat...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Wehner, Philipp Rettkowski, Jens Kleinschmidt, Tobias Goehringer, Diana Ruhr Univ Bochum Bochum Germany

ISBN: (纸本)9781467373111

In this paper a SystemC simulator for Network-on-Chip (NoC) based Multiprocessor systems-on-Chip (MPSoCs) is presented. The simulator currently supports mesh topology with wormhole switching and several routing algorithms such as XY-, a minimal West-First and an adaptive West-First algorithm. The impact of routing algorithms regarding performance can be analyzed by means of the presented simulator. In order to simulate a heterogeneous MPSoC, ARM processors and MicroBlazes can be attached to the NoC. Processor and peripheral models used within the test platforms are provided by Imperas/OVP. Moreover, traffic generators are available to analyze the system. An additional SystemC component enables the readout of simulation time from within the application. For evaluation of the simulator multiple platforms and applications were put under test and compared with a hardware implementation. The comparison shows that the simulator improves the development of MPSoCs by early estimation of system requirements.

关键词： MPSoC simulator Network-on-Chip heterogeneous MPSoC routing algorithms OVP

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A Unifying Logic Encryption Security Metric 18

A Unifying Logic Encryption Security Metric

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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sisejkovic, Dominik Leupers, Rainer Ascheid, Gerd Metzner, Simon Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Hensoldt Cyber GmbH Ottobrunn Germany

ISBN: (纸本)9781450364942

The globalization of the IC supply chain has brought forth the era of fabless companies. Due to security issues during design and fabrication processes, various security concerns have risen, ranging from IP piracy and reverse engineering to hardware Trojans. Logic encryption has emerged as a mitigation against these threats. However, no generic metrics for quantifying the security of logic encryption algorithms has been reported so far, making it impossible to formally compare diferent approaches. In this paper, we propose a unifying metric, capturing the key security aspects of logic encryption algorithms. The metric is evaluated on state-of-the- art algorithms and benchmarks.

关键词： Hardware security security metrics obfuscation logic encryption

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Adaptive Runtime Exploiting Sparsity in Tensor of Deep Learning Neural Network on Heterogeneous systems 17

Adaptive Runtime Exploiting Sparsity in Tensor of Deep Learn...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Peng, Kuo-You Fu, Sheng-Yu Liu, Yu-Ping Hsu, Wei-Chung Natl Taiwan Univ New Taipei Taiwan

ISBN: (纸本)9781538634370

Deep neural networks have been widely applied in many areas, such as computer vision, natural language processing and information retrieval. However, due to the high computation and memory demands, deep learning applications have not been adopted in edge learning. In this paper, we exploit the sparsity in tensors to reduce the computation overheads and memory demands. Unlike other approaches which rely on hardware accelerator designs or sacrifice model accuracy for the performance by pruning parameters, we adaptively partition and deploy the workload to heterogeneous devices to reduce computation and memory requirements and increase computing efficiency. We had implemented our partitioning algorithms in Google's TensorFlow and evaluated on an AMD Kaveri system, which is an HSA-based heterogeneous computing system. Our method has effectively reduced the computation time, cache accesses, and cache miss rates, without impacting the accuracy of the learning models. Our approach achieves 66% and 88% speedup for the lenet-5 model and the lenet-1024-1024 model, respectively. For reducing memory traffic, our approach reduces 71% instruction cache references, 32% data cache references. Our system has also improved cache miss rate from 1.6% to 0.5% during the training of the lenet-1024-1024 model.

关键词： Neurons Computational modeling Training Sparse matrices Machine learning Heterogeneous networks Tensile stress Heterogeneous networks Sparse matrix Tensile stress Computational modeling Tensor HETEROGENEOUS SYSTEM Functional training Neurons Memory Memory Partitioning algorithms Machine Learning cache miss Training Artificial Intelligence

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ESL Power Estimation using Virtual Platforms with Black Box Processor Models 15

ESL Power Estimation using Virtual Platforms with Black Box ...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Schuermans, Stefan Onnebrink, Gereon Leupers, Rainer Ascheid, Gerd Chen, Xiaotao Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Huawei Technol Co Ltd Bridgewater NJ USA

ISBN: (纸本)9781467373111

Processor models for electronic system level (ESL) simulations are usually provided by their vendors as binary object code. Those binaries appear as black boxes, which do not allow to observe their internals. This prevents the application of most existing ESL power estimation methodologies. To remedy this situation, this work presents an estimation methodology for the case of black box models. The evaluation for the ARM Cortex-A9 processor shows that the proposed approach is able to achieve a high accuracy. In comparison to hardware power measurements obtained from the OMAP4460 chip on the PandaBoard, the ESL estimation error is below 5%.

关键词： English as Second Language PROCESSOR BLACK-BOX power estimation Power measurement Vendors Boxes Buxus sempervirens

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Multi-objective topology optimization for networked embedded systems

Multi-objective topology optimization for networked embedded...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Streichert, Thilo Haubelt, Christian Teich, Juergen Univ Erlangen Nurnberg D-8520 Erlangen Germany

ISBN: (纸本)1424401550

In this paper, a new methodology is presented for topology optimization of networked embedded systems as they occur in automotive and avionic systems and partially in wireless sensor networks. By introducing a model which is (1.) suitable for heterogeneous networks with different communication bandwidths, (2.) modeling of routing restrictions, and (3.) flexible binding of tasks onto processors, current design issues of networked embedded systems can be investigated. On the basis of this model, the presented methodology firstly allocates the required resources which can be communication links as well as computational nodes and secondly binds the functionality onto the nodes and the data dependencies onto the links such that no routing restrictions will be violated or capacities on communication links will be exceeded. By applying Evolutionary Algorithms, we are able to consider multiple objectives simultaneously during the optimization process and allow for a subsequent unbiased decision making. An experimental evaluation as well as a demonstration of a case study from the field of automotive electronics will show the applicability of the presented approach.

关键词： Heterogeneous networks

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Performance evaluation of memory management configurations in linux for an OS-level design space exploration

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international conference on embedded computer systems - architectures, modeling and simulation

作者： Park, Sangsoo Shin, Heonshik Univ Michigan Dept Elect Engn & Comp Sci 2260 Hayward St Ann Arbor MI 48109 USA Seoul Natl Univ Sch Comp Sci Seoul South Korea

ISBN: (纸本)9783540736226

The objective of this paper is to analyze how the memory management configuration in Linux influences run-time performance of embedded systems. Extensive experiments confirm that the configuration of the memory management subsystem significantly affects the overall execution time, the memory performance, and the system call overhead. Our quantitative experimental results will help embedded systems designers to understand the effect of memory management configurations on the applications within a system, and contribute to the design of more efficient systems with an OS-level design space exploration.

关键词： computer operating systems

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Domain-specific modeling of power aware distributed real-time embedded systems

Domain-specific modeling of power aware distributed real-tim...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Madl, Gabor Dutt, Nikil Univ Calif Irvine Ctr Embedded Comp Syst Irvine CA 92697 USA

ISBN: (纸本)3540364102

This paper provides two contributions to the research on applying domain-specific modeling languages to distributed real-time embedded (DRE) systems. First, we present the ALDERIS platform-independent visual language for component-based system development. Second, we demonstrate the use of the ALDERIS language on a helicopter autopilot DRE design. The ALDERIS language is based on the concept of platform-based design, and explicitly captures asynchronous event-driven component interactions as well as the underlying platform for the computation. Unlike most modeling languages, ALDERIS has formally defined semantics providing a way for the formal verification of dense real-time properties and energy consumption.

关键词： embedded systems

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Efficient Hardware Implementation of Data-Flow Parallel embedded systems

Efficient Hardware Implementation of Data-Flow Parallel Embe...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Quinton, Patrice Chana, Anne-Marie Derrien, Steven Univ Europeenne Bretagne ENS Cachan Bretagne F-35170 Bruz France

ISBN: (纸本)9781467322973;9781467322966

Many modern computing systems deal with streams of data, which have to be processed in parallel in order to be handled in real-time. This is in particular the case for some kind of cyber physical systems, which process data provided by physical devices. We consider here an approach to generate efficient hardware for-a particular class of-such systems, which relies upon the polyhedral model. Flexible parallel components, described by the ALPHA functional language, are modelled and assembled using a scheduling method which combines the synchronous data-flow principle of balance equations, and the polyhedral scheduling technique. The modelling of flexible components relies on a simple, affine-periodic, delayable and stretchable time model, which allows a full system to be assembled and synthesized by combining the component hardware descriptions with automatically generated wrappers. We illustrate this method on a simplified WCDMA system and we discuss the relationship of this approach with stream languages, latency-insensitive design, and multidimensional data-flow systems.

关键词： computer hardware Flexible components Parallel Lines Hydrologic models streams embedded systems Equation Cyber-physical systems assemblies rivers Functional programming WRAPPERS

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