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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

共 2730 条记录，以下是151-160 订阅

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On Tokens and Signals: Bridging the Semantic Gap between Dataflow Models and Hardware Implementations 14

On Tokens and Signals: Bridging the Semantic Gap between Dat...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Tripakis, Stavros Limaye, Rhishikesh Ravindran, Kaushik Wang, Guoqiang Univ Calif Berkeley Berkeley CA 94720 USA Aalto Univ Espoo Finland Natl Instruments Corp Berkeley CA USA

ISBN: (纸本)9781479937707

Dataflow models serve as useful abstractions of digital hardware in signal processing and other application domains. But when can one say that a certain dataflow model faithfully captures a given piece of hardware? To answer this question we develop a formal conformance relation between the heterogeneous formalisms of (1) finite state machines with synchronous semantics, used to model hardware, and (2) asynchronous processes communicating via queues, used as a formal model for dataflow. The conformance relation preserves performance properties such as worst-case throughput and latency.

关键词： data flow token computer hardware signals Semantics Queue signal processing

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Application Runtime Estimation for AURIX embedded MCU Using Deep Learning 22nd

Application Runtime Estimation for AURIX Embedded MCU Using ...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Fricke, Florian Scharoba, Stefan Rachuj, Sebastian Konopik, Andreas Kluge, Florian Hofstetter, Georg Reichenbach, Marc BTU Cottbus Senftenberg Cottbus Germany Friedrich Alexander Univ Erlangen Nurnberg Erlangen Germany Elekt Fahrwerksyst GmbH Gaimersheim Germany

ISBN: (纸本)9783031150746;9783031150739

Estimating execution time is a crucial task during the development of safety-critical embedded systems. Processor simulation or emulation tools on various abstraction levels offer a trade-off between accuracy and runtime. Typically, this requires detailed knowledge of the processor architecture and high manual effort to construct adequate models. In this paper, we explore how deep learning may be used as an alternative approach for building processor performance models. First, we describe how to obtain training data from recorded execution traces. Next, we evaluate various neural network architectures and hyperparameter values. The accuracy of the best network variants is finally compared to two simple baseline models and a mechanistic model based on the QEMU emulator. As an outcome of this evaluation, a model based on the Wavenet architecture is identified, which outperforms all other approaches by achieving a mean absolute percentage error of only 1.63%.

关键词： embedded processor Performance estimation Artificial neural networks

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Fast Parallel simulation of a Manycore Architecture with a Flit-level On-chip Network Model 18

Fast Parallel Simulation of a Manycore Architecture with a F...

引用

18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Kang, Shin-haeng Kang, Jintaek Ha, Soonhoi Seoul Natl Univ Seoul South Korea

ISBN: (纸本)9781450364942

The reliance on simulation for the design of a new architecture continues to increase as the complexity of the architecture increases with more cores integrated and a complex communication fabric. A good compromise between the simulation speed and accuracy should be made in order to explore the wide architectural design space at the early design phase. In this work, we present a novel manycore simulator that achieves fast and scalable performance with a trace-driven parallel simulation technique. Since the communication delay affects the simulation accuracy heavily, the proposed simulator supports a high-speed accurate on-chip network model, which can capture link/buffer congestions. Its development is motivated by an industry project to design a new manycore architecture with 96 cores with a NoC architecture. Experimental results show that the proposed simulator could run real parallel benchmark applications with more than 450 Kcycles/sec/core. It marks a Pareto-optimal simulator between speed and accuracy, compared with existent simulators.

关键词： Manycore Network-on-chip Parallel simulation

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RETHROTTLE: Execution Throttling in the REDEFINE SoC Architecture

RETHROTTLE: Execution Throttling in the REDEFINE SoC Archite...

引用

international conference on embedded computer systems -architectures, modeling and simulation

作者： Satrawala, A. N. Nandy, S. K. Indian Inst Sci SERC CAD Lab Bangalore 560012 Karnataka India

ISBN: (纸本)9781424445011

REDEFINE is a reconfigurable SoC architecture that provides a unique platform for high performance and low power computing by exploiting the synergistic interaction between coarse grain dynamic dataflow model of computation (to expose abundant parallelism in applications) and runtime composition of efficient compute structures (on the reconfigurable computation resources). We propose and study the throttling of execution in REDEFINE to maximize the architecture efficiency. A feature specific fast hybrid (mixed level) simulation framework for early in design phase study is developed and implemented to make the huge design space exploration practical. We do performance modeling in terms of selection of important performance criteria, ranking of the explored throttling schemes and investigate effectiveness of the design space exploration using statistical hypothesis testing. We find throttling schemes which give appreciable (24.8%) overall performance gain in the architecture and 37% resource usage gain in the throttling unit simultaneously.

关键词： Hybrid simulation Reconfigurable SoC Dataflow Throttling Performance Evaluation Ranking

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Exploring the Semantic Gap in Compiling embedded DSLs 18

Exploring the Semantic Gap in Compiling Embedded DSLs

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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Zangerl, Peter Jordan, Herbert Thoman, Peter Gschwandtner, Philipp Fahringer, Thomas Univ Innsbruck Innsbruck Austria

ISBN: (纸本)9781450364942

Optimizing compilers provide valuable contributions to the quality of processed code. The vast majority of application developers rely on those capabilities to obtain binary code efficiently utilizing processing resources. However, compiler proficiency is frequently misjudged by application developers. While for some constellations the effectiveness of those optimizations is grossly underestimated, for others, mostly involving higher-level semantic concepts of embedded DSLs, the compilers' influence on the code quality tends to disappoint. In this paper, we provide examples for the effectiveness and ineffectiveness of state-of-the-art optimizing compilers in improving application code. Based on those observations we characterize the differences between positive and negative examples and provide an in-depth explanation for the short-comings of optimizing compilers. Furthermore, we present a semantic-aware compiler architecture rectifying those deficiencies and outline several example use cases demonstrating our architecture's ability to contribute to the efficiency and the capabilities of embedded DSLs.

关键词： Semantics

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Thermal Characterization of Next-Generation Workloads on Heterogeneous MPSoCs 17

Thermal Characterization of Next-Generation Workloads on Het...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Iranfar, Arman Terraneo, Federico Simon, William Andrew Dragic, Leon Piljic, Igor Zapater, Marina Fornaciari, William Kovac, Mario Atienza, David Swiss Fed Inst Technol Lausanne Embedded Syst Lab Lausanne Switzerland Politecn Milan Dipartimento Elettron Informaz & Bioingegneria Milan Italy Univ Zagreb Fac Elect Engn & Comp Zagreb Croatia

ISBN: (纸本)9781538634370

Next-generation High-Performance Computing (HPC) applications need to tackle outstanding computational complexity while meeting latency and Quality-of-Service constraints. Heterogeneous Multi-Processor systems-on-Chip (MPSoCs), equipped with a mix of general-purpose cores and reconfigurable fabric for custom acceleration of computational blocks, are key in providing the flexibility to meet the requirements of next-generation HPC. However, heterogeneity brings new challenges to efficient chip thermal management. In this context, accurate and fast thermal simulators are becoming crucial to understand and exploit the trade-offs brought by heterogeneous MPSoCs. In this paper, we first thermally characterize a next-generation HPC workload, the online video transcoding application, using a highly-accurate Infra-Red (IR) microscope. Second, we extend the 3D-ICE thermal simulation tool with a new generic heat spreader model capable of accurately reproducing package surface temperature, with an average error of 6.8% for the hot spots of the chip. Our model is used to characterize the thermal behaviour of the online transcoding application when running on a heterogeneous MPSoC. Moreover, by using our detailed thermal system characterization we are able to explore different application mappings as well as the thermal limits of such heterogeneous platforms.

关键词： Transcoding Heating systems Thermal management Heat sinks Streaming media Thermal sensors Quality of service transcoding THERMAL SENSOR Streaming Video Heating systems heat sinks Thermal management Quality of service High Performance Computing infrared microscopy Workload

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Multi-Constraint Multi-Processor Resource Allocation 15

Multi-Constraint Multi-Processor Resource Allocation

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international conference on embedded computer systems architectures modeling and simulation

作者： Behrouzian, Amir R. B. Goswami, Dip Basten, Twan Geilen, Marc Ara, Hadi Alizadeh Eindhoven Univ Technol Eindhoven Netherlands TNO Embedded Syst Innovat Eindhoven Netherlands

ISBN: (纸本)9781467373111

This work proposes a Multi-Constraint Resource Allocation (MuCoRA) method for applications from multiple domains onto multi-processors. In particular, we address a mapping problem for multiple throughput-constrained streaming applications and multiple latency-constrained feedback control applications onto a multi-processor platform running under a Time-Division Multiple-Access (TDMA) policy. The main objective of the proposed method is to reduce resource usage while meeting constraints from both these two domains (i.e., throughput and latency constraints). We show by experiments that the overall resource usage for this mapping problem can be reduced by distributing the allocated resource (i.e., TDMA slots) to the control applications over the TDMA wheel instead of allocating consecutive slots.

关键词： Resource allocation multi-processors throughput constraints latency constraints control applications streaming applications synchronous dataflow

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Challenges in Automotive Cyber-physical systems Design

Challenges in Automotive Cyber-physical Systems Design

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Goswami, Dip Schneider, Reinhard Masrur, Alejandro Lukasiewycz, Martin Chakraborty, Samarjit Voit, Harald Annaswamy, Anuradha Tech Univ Munich Inst Real Time Comp Syst Munich Germany TUM CREATE Ctr Elect Singapore Singapore Tech Univ Munich Inst Automat Control Munich Germany MIT Cambridge MA 02139 USA

ISBN: (纸本)9781467322973;9781467322966

systems with tightly interacting computational (cyber) units and physical systems are generally referred to as cyber-physical systems. They involve an interplay between embedded systems, control theory, real-time systems and software engineering. A very good example of cyber-physical systems design arises in the context of automotive architectures and software. Modern high-end cars have 50-100 processors or electronic control units (ECUs) that communicate over a network of buses such as CAN and FlexRay. In such complex settings, traditional control-theoretic approaches - where control engineers are only concerned with high-level plant and controller models - start breaking down. This is because implementation-level realities such as message delay, jitter, and task execution times are not adequately considered when designing the controller. Hence, it is becoming necessary to adopt a more holistic, cyber-physical systems design approach where the semantic gap between high-level control models and their actual implementations on multiprocessor automotive platforms is quantified and consciously closed. In this paper we give several examples on how this may be done and the current research challenges in this area that are being faced by the academia and the industry.

关键词： Cyber-physical systems automotive engineering Motor buses embedded systems current research Engineers electronic control unit execution time computer software Controllers

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An FPGA-Accelerated Testbed for Hardware Component Development in MIMO Wireless Communication systems

An FPGA-Accelerated Testbed for Hardware Component Developme...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Borlenghi, Filippo Auras, Dominik Witte, Ernst Martin Kempf, Torsten Ascheid, Gerd Leupers, Rainer Meyr, Heinrich Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst D-52056 Aachen Germany

ISBN: (纸本)9781467322973;9781467322966

FPGA-based prototyping is nowadays common practice in the functional verification of hardware components since it allows to cover a large number of test cases in a shorter time compared to HDL simulation. In addition, an FPGA-based emulator significantly accelerates the simulation with respect to bit-true software models. This speed-up is crucial when the statistical properties of a system have to be analyzed by Monte Carlo techniques. In this paper we consider a multiple-input multiple-output (MIMO) wireless communication system and show how integrating an FPGA accelerator in the software simulation framework is key to enable the development of complex hardware components in the receiver, from algorithm all the way to chip testing. In particular, we focus on a MIMO detector implementation based on the depth-first sphere decoding algorithm. The speed-up of up to 3 orders of magnitude achieved by hardware-accelerated simulation compared to a pure software testbed enables an extensive fixed-point exploration. Furthermore, it allows a unique characterization of the system communication performance and the MIMO detector run-time characteristics, which vary for different configuration parameters and operating scenarios and hence require a thorough investigation.

关键词： multiple input multiple output systems Wireless communication systems CASING INSPECTION computer hardware configuration parameter simulating Speeding

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Prototyping efficient interprocessor communication mechanisms

Prototyping efficient interprocessor communication mechanism...

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international conference on embedded computer systems - architectures, modeling and simulation

作者： Papaefstathiou, Vassilis Pnevmatikatos, Dionisios Marazakis, Manolis Kalokairinos, Giorgos Ioannou, Aggelos Papamichael, Michael Kavadias, Stamatis Mihelogiannakis, Giorgos Katevenis, Manolis Institute of Computer Science FORTH Vasilika Vouton Heraklion GR 711 10 Greece

ISBN: (纸本)9781424410583

Parallel computing systems are becoming widespread and grow in sophistication. Besides simulation, rapid system prototyping becomes important in designing and evaluating their architecture. We present an efficient FPGA-based platform that we developed and use for research and experimentation on high speed interprocessor communication, network interfaces and interconnects. Our platform supports advanced communication capabilities such as Remote DMA, Remote Queues, zero-copy data delivery and flexible notification mechanisms, as well as link bundling for increased performance. We report on the platform architecture, its design cost, complexity and performance (latency and throughput). We also report our experiences from implementing benchmarking kernels and a user-level benchmark application, and show how software can take advantage of the provided features, but also expose the weaknesses of the system.

关键词： Benchmarking

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