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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

共 2730 条记录，以下是181-190 订阅

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Systematic data structure exploration of multimedia and network applications realized embedded systems

Systematic data structure exploration of multimedia and netw...

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Papadopoulos, L. Baloukas, C. Zompakis, N. Soudris, D. Democritus Univ Thrace Dept Elect & Comp Engn VLSI Design & Testing Ctr GR-67100 Xanthi Greece

ISBN: (纸本)9781424410583

In the last years, there is a trend towards network and multimedia applications to be implemented in portable devices. These applications usually contain complex dynamic data structures. The appropriate selection of the dynamic data type (DDT) combination of an application affects the performance and the energy consumption of the whole system. Thus, DDT exploration methodology is used to perform trade-offs between design factors, such as performance and energy consumption. In this paper we provide a new approach to the DDT exploration procedure, based on a new library of DDTs which remedies the limitations of an existing and allows the DDT optimization of a wide range of application domains. Using the new library, we performed DDT exploration in network and multimedia benchmarks and achieved performance and energy consumption improvements up to 85% and 43% respectively.

关键词： Energy utilization

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SystemQ: A queuing-based approach to architecture performance evaluation with SystemC

SystemQ: A queuing-based approach to architecture performanc...

引用

5th international Workshop on embedded computer systems - architectures, modeling,, and simulation

作者： Sonntag, S Gries, M Sauer, C Infineon Technol Wireline Commun Munich Germany Infineon Technol Corp Res Munich Germany

ISBN: (纸本)354026969X

Platform architectures for modem embedded systems are increasingly heterogeneous and parallel. Early design decisions, such as the allocation of hardware resources and the partitioning of functionality onto architecture building blocks, become even more complex and important for the resulting design quality. To effectively support designers during the concept phase we base our design flow SystemQ on queuing systems. We show how by starting with a performance model the system's behavior and structure can be refined systematically. SystemQ is implemented in SystemC and seamlessly supports the refinement of SystemQ models down to established transaction and RT levels. Compared with existing approaches, SystemQ's formalism exposes transaction scheduling as one key aspect of the system's performance and allows the modeling of time and resource workload-dependent behavior. A case study underpins the usefulness of SystemQ's approach by evaluating a network access platform at three refinement levels.

关键词： embedded systems

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Resource conflict detection in simulation of function unit pipelines

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Jaaskelainen, Pekka Guzma, Vladimir Takala, Jarmo Tampere Univ Technol Dept Informat Technol POB 553 FIN-33101 Tampere Finland

ISBN: (纸本)9783540736226

Processor simulators are important parts of processor design toolsets in which they are used to verify and evaluate the properties of the designed processors. While simulating architectures with independent function unit pipelines using simulation techniques that avoid the overhead of instruction bit-string interpretation, such as compiled simulation, the simulation of function unit pipelines can become one of the new bottlenecks for simulation speed. This paper evaluates commonly used models for function unit pipeline resource conflict detection in processor simulation: a resource vector based-model, and an finite state automata (FSA) based model. In addition, an improvement to the simulation initialization time by means of lazy initialization of states in the FSA-based approach is proposed. The resulting model is faster to initialize and provides equal simulation speed when compared to the actively initialized FSA. Our benchmarks show at best 23 percent improvement to the initialization time.

关键词： Program processors

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Parallel Implementation of Real-Time Semi-Global Matching on embedded Multi-Core architectures

Parallel Implementation of Real-Time Semi-Global Matching on...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Arndt, Oliver Jakob Becker, Daniel Banz, Christian Blume, Holger Leibniz Univ Hannover Inst Microelect Syst D-30167 Hannover Germany Corporate Techn D-81739 Munich Germany

ISBN: (纸本)9781479901036

embedded real-time algorithms are often realized with dedicated hardware, exhibiting high production costs and low programming flexibility thereafter. For instance, semi-global matching for stereo image processing, including complex data flows, traditionally runs on customized hardware modules. Combining the processing and memory capabilities of multiple individual cores, emerging embedded multi-core technologies address these problems. However, considering concurrency issues (e. g., data races and lock contentions), parallel programming requires experienced programmers and technology-specific techniques (e. g., synchronization libraries) and tools (e. g., parallel profilers), which are often not available on embedded platforms. In this work, we introduce a parallel version of a semi-global matching algorithm and demonstrate within this case study runtime optimizations necessary to meet real-time requirements. We also show structured steps of the applied parallelization workflow, illustrating an efficient migration strategy to multi-core platforms using runtime information (e. g., profiles and hardware counters). Finally, to evaluate the resulting performance characteristics, we compare the runtime behavior of the parallel version running on a Freescale P4080 processor with reference values taken on an Intel i7, a field-programmable logic device, an extended general purpose processor and a GPU.

关键词： concurrency control embedded systems image matching multiprocessing systems parallel architectures parallel programming performance evaluation

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Evaluation of Approximate Operators Case Study: Sobel Filter Application Executed On An Approximate RISC-V Platform 18

Evaluation of Approximate Operators Case Study: Sobel Filter...

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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Ndour, Genevieve Jost, Tiago Trevisan Molnos, Anca Durand, Yves Tisserand, Arnaud Univ Grenoble Alpes CEA LETI Grenoble France Univ Rennes 1 CNRS INRIA IRISA Rennes France Univ Bretagne Sud CNRS Labs STICC UMR 6285 Lorient France

ISBN: (纸本)9781450364942

Approximate computing techniques have been proposed to decrease the energy consumption or improve the performance of computation. Several designs of approximate arithmetic operators are proposed in the literature, suggesting that the operators' energy can be reduced up to 46%. This paper puts existing work in perspective by studying the impact of these operators in a processor targeting the embedded systems. We augment a RISC-V processor with approximate addition and multiplication that support a variable bit-width in the range of 1 to 16 bits. We investigate the error-energy trade-off for a Sobel filter application. The results indicate that, for an acceptable output image degradation, 7.5% of the energy is saved. We conclude that the benefits of using approximate operators in embedded systems processors, have yet to be proved.

关键词： embedded systems approximate computing operators energy

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A comparative study of different FFT architectures for Software Defined Radio

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Mittal, Shashank Khan, Md. Zafar Ali Srinivas, M. B. Int Inst Informat technol Ctr VLSI & Embedded Syst Technol Hyderabad 500032 Andhra Pradesh India

ISBN: (纸本)9783540736226

Fast Fourier Transform (FFT) is the most basic and essential operation performed in Software Defined Radio (SDR). Thus designing regular, reconfigurable, modular, low hardware and timing-complexity FFT computation block is very important. A single FFT block should be configurable for varying length FFT computation and also for computation of different transforms like Discrete cosine/sine transform (DCT/DST) etc. In this paper, the authors analyze area, timing complexity and noise to signal Ratio (NSR) of Bruun's FFT w.r.t. classical FFT from a SDR perspective. It is shown that architecture of Bruun's FFT is ideally suited for SDR and may be used in preference over classical FFT for most practical cases. A detailed comparison of Bruun's and classical FFT hardware architectures for same NSR is carried out and results of FPGA implementation are discussed.

关键词： computer architecture

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Memory architecture evaluation for video encoding on enhanced embedded processors

Memory architecture evaluation for video encoding on enhance...

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Iranpour, Ali Kuchcinski, Krzysztof Lund Univ Dept Comp Sci SE-22100 Lund Sweden

ISBN: (纸本)3540364102

In this paper we investigate the impact of different memory configurations on performance and energy consumption of the video encoding applications, MPEG-4 and H.264. The memory architecture is integrated with SIMD extended embedded processor, proposed in our previous work. We explore both dedicated memories and multilevel cache-architectures and perform exhaustive simulations. The simulations have been conducted using highly optimized proprietary video encoding code for mobile handheld devices. Our simulation results show that the performance improvement of dedicated memories on video encoding applications is not very significant. The multilevel cache-based architecture processes approximately 17 frames/s compared to 1922 frames/s for 512 KB dedicated on-chip zero-wait state memory. Thus it is difficult to justify using dedicated memory for this kind of embedded systems, when energy consumption and cost of implementation are also considered.

关键词： Image coding

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Combining on-hardware prototyping and high-level simulation for DSE of multi-ASIP systems

Combining on-hardware prototyping and high-level simulation ...

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Meloni, Paolo Pomata, Sebastiano Raffo, Luigi Piscitelli, Roberta Pimentel, Andy D. Univ Cagliari Dept Elect & Elect Engn I-09124 Cagliari Italy Univ Amsterdam Comp Syst Architecture Grp Amsterdam Netherlands

ISBN: (纸本)9781467322973;9781467322966

Modern heterogeneous multi-processor embedded systems very often expose to the designer a large number of degrees of freedom, related to the application partitioning/mapping and to the component-and system-level architecture composition. The number is even larger when the designer targets systems based on configurable Application Specific Instruction-set Processors, due to the fine customizability of their internal architecture. This poses the need for effective and user-friendly design tools, capable to deal with the extremely wide system-level design space exposed by multi-processor architecture and, at the same time, with an extended variety of processing element architectural configurations, to be evaluated in detail and in reasonable times. As a possible solution, within the MADNESS project [1], an integrated toolset has been proposed, combining the benefits of novel fast FPGA-based prototyping techniques with those provided by high-level simulation. In the toolset, the resulting evaluation platform serves as an underlying layer for a Design Space search algorithm. The paper presents the individual tools included in the toolset and their interaction strategy. The approach is then evaluated with a design space exploration case study, taking as a target application a video compression kernel. The integrated toolset has been used to produce a Pareto front of evaluated system-level configurations.

关键词： DSE gene Designers Multiprocessor Processor architectures PROTOTYPE Video compression Building construction ARCHITECTURE customizability

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Optimal Mapping of Inferior Olive Neuron simulations on the Single-Chip Cloud computer 14

Optimal Mapping of Inferior Olive Neuron Simulations on the ...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Rodopoulos, Dimitrios Chatzikonstantis, Giorgos Pantelopoulos, Andreas Soudris, Dimitrios De Zeeuw, Chris I. Strydis, Christos NTUA MICROprocessors & Digital Syst LAB Athens Greece Erasmus MC Dept Neurosci Rotterdam Netherlands

ISBN: (纸本)9781479937707

Biologically accurate neuron simulations are increasingly important in research related to brain activity. They are computationally intensive and feature data and task parallelism. In this paper, we present a case study for the mapping of a biologically accurate inferior-olive (InfOli), neural cell simulator on an many-core research platform. The Single-Chip Cloud computer (SCC) is an experimental processor created by Intel Labs. The target neurons provide a major input to the cerebellum and are involved in motor skills and space perception. We exploit task-and data-partitioning, scaling the simulation over more than 40,000 neurons. The voltage-and frequency-scaling capabilities of the chip are explored, achieving more than 20% energy savings with negligible performance degradation. Four platform configurations are evaluated and a mapping with balanced workload and constant voltage and frequency is formally derived as optimal.

关键词： Dynamic Frequency and Voltage Scaling Inferior Olive Neurons Pareto Optimal Single-Chip Cloud computer

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A State-Based modeling Approach for Fast Performance Evaluation of embedded System architectures

A State-Based Modeling Approach for Fast Performance Evaluat...

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22nd IEEE international Symposium on Rapid System Prototyping (RSP)

作者： Le Nours, Sebastien Barreteau, Anthony Pasquier, Olivier Univ Nantes IREENA EA1770 Polytech Nantes F-44000 Nantes France

ISBN: (纸本)9781457706608

models are means to assist system architects in the evaluation process of hardware/software architectures and then to cope with the still increasing complexity of embedded systems. Efficient methods are necessary to correctly model system architectures and to make possible early performance evaluation and fast exploration of the design space. In this paper, we present the use of a specific modeling approach to improve evaluation of non-functional properties of embedded systems. The contribution is about a computation method defined to improve modeling of properties used for assessment of architecture performances. This method favors creation of abstract transaction level models and leads to significantly reducing simulation time but still preserving accuracy of results. The benefits of the proposed approach for evaluation of performances of system architectures are highlighted through analysis of two specific case studies.

关键词： Analytical models Computational modeling computer architecture Context modeling embedded systems Load modeling Performance evaluation abstract transaction level models embedded system architectures embedded systems hardware architectures performance evalu

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