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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Eusse, Juan Fernando Williams, Christopher Murillo, Luis Gabriel Leupers, Rainer Ascheid, Gerd Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst ICE Aachen Germany

ISBN: (纸本)9781479937707

Application Specific Instruction Set Processors (ASIPs) seek for an optimal performance/area/energy trade-off for a given algorithm. In all current design methodologies an architectural model must be first manually created based on designers experience. These models are increasingly refined until the design constraints are met, through several time consuming algorithmic/architecture co-exploration iterations. This paper presents a novel performance estimation approach that shortens the design cycle of existing methodologies by providing an early assessment of the impact of customizations on the achievable performance. The approach does so by eliminating the need for a completely specified architecture, without limiting designer's freedom and without simulating the application repeatedly. Overall, our approach reduces the number of necessary co-exploration iterations, thus increasing design productivity. We validate our approach via two different case studies: a butterfly-enabled ASIP for Fast Fourier Transform computation and a Connected Components Labeling ASIP for computer vision.

关键词： Performance Evaluation ASIP gene design constraints connected component Design flow Customization Designers PROCESSOR images computer vision iterative methods

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A Data-Driven Approach to Lightweight DVFS-Aware Counter-Based Power modeling for Heterogeneous Platforms 22nd

A Data-Driven Approach to Lightweight DVFS-Aware Counter-Bas...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Mazzola, Sergio Benz, Thomas Forsberg, Bjoern Benini, Luca Swiss Fed Inst Technol Integrated Syst Lab IIS Zurich Switzerland Univ Bologna DEI Bologna Italy

ISBN: (纸本)9783031150746;9783031150739

Computing systems have shifted towards highly parallel and heterogeneous architectures to tackle the challenges imposed by limited power budgets. These architectures must be supported by novel power management paradigms addressing the increasing design size, parallelism, and heterogeneity while ensuring high accuracy and low overhead. In this work, we propose a systematic, automated, and architecture-agnostic approach to accurate and lightweight DVFS-aware statistical power modeling of the CPU and GPU sub-systems of a heterogeneous platform, driven by the sub-systems' local performance monitoring counters (PMCs). Counter selection is guided by a generally applicable statistical method that identifies the minimal subsets of counters robustly correlating to power dissipation. Based on the selected counters, we train a set of lightweight, linear models characterizing each sub-system over a range of frequencies. Such models compose a lookup-table-based system-level model that efficiently captures the non-linearity of power consumption, showing desirable responsiveness and decomposability. We validate the system-level model on real hardware by measuring the total energy consumption of an NVIDIA Jetson AGX Xavier platform over a set of benchmarks. The resulting average estimation error is 1.3%, with a maximum of 3.1%. Furthermore, the model shows a maximum evaluation runtime of 500 ns, thus implying a negligible impact on system utilization and applicability to online dynamic power management (DPM).

关键词： Power modeling Energy estimation Performance counters Heterogeneous systems Linear models

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Combining Task- and Data-Level Parallelism for High-Throughput CNN Inference on embedded CPUs-GPUs MPSoCs 1

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20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Minakova, Svetlana Tang, Erqian Stefanov, Todor Leiden Univ LIACS Leiden Netherlands

ISBN: (数字)9783030609399

ISBN: (纸本)9783030609399;9783030609382

Nowadays Convolutional Neural Networks (CNNs) are widely used to perform various tasks in areas such as computer vision or natural language processing. Some of the CNN applications require high-throughput execution of the CNN inference, on embedded devices, and many modern embedded devices are based on CPUs-GPUs multiprocessor systems-on-chip (MPSoCs). Ensuring high-throughput execution of the CNN inference on embedded CPUs-GPUs MPSoCs is a complex task, which requires efficient utilization of both task-level (pipeline) and data-level parallelism, available in a CNN. However, the existing Deep Learning frameworks utilize only task-level (pipeline) or only data-level parallelism, available in a CNN, and do not take full advantage of all embedded MPSoC computational resources. Therefore, in this paper, we propose a novel methodology for efficient execution of the CNN inference on embedded CPUs-GPUs MPSoCs. In our methodology, we ensure efficient utilization of both task-level (pipeline) and data-level parallelism, available in a CNN, to achieve high-throughput execution of the CNN inference on embedded CPUs-GPUs MPSoCs.

关键词： Convolutional Neural Networks Dataflow models SDF CSDF Mapping Hight throughput

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Reuse-oriented design of embedded systems

International Conference on Knowledge-Based Intelligent Elec...

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international conference on Knowledge-Based Intelligent Electronic systems, Proceedings, KES 2000年 2卷 691-694页

作者： Monjau, Dieter Sporer, Mathias Chemnitz Univ of Technology Chemnitz Germany

This paper describes an object-oriented model and a reuse-oriented methodology for the co-design of embedded computer systems. Our approach is based on a hierarchy of classes which describes all possible specifications of systems of a certain domain, the behavior of hard- and software-components, and the target-architectures. The content of this knowledge base (re-usable, formalized descriptions) is determined by the analysis of known systems. We present solutions for a specification methodology, the modeling of heterogeneous systems by task graphs, and the mapping process from specified requirements down to hard- or software components in a target architecture. This approach is illustrated by functions of the domain of robot controls.

关键词： embedded systems

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Development and Design of a Platform for Arbitration and Sharing Control Applications -a DESERVE approach- 14

Development and Design of a Platform for Arbitration and Sha...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Perez, Joshue Gonzalez, David Nashashibi, Fawzi Tango, Fabio Pallaro, Nereo Dunand, Gwenael Rolfsmeier, Andre INRIA Le Chesnay France Ctr Ric FIAT Orbassano Italy Intempora Issy Les Moulineaux France dSpace Paderborn Germany

ISBN: (纸本)9781479937707

In this paper, a description of the ADAS development platform in DESERVE project framework is presented. This work is framed within the Sub Project 2 (Development platform) of DESERVE project, and it is divided in 6 different and complementary lines of work. Most of the functions described in the tools and development systems, perception layer and the platform system architecture show the modularity and scalability of our proposal. Moreover, based on vehicle modelling, driver behaviour and intention, a first approach for arbitration and control strategies, which can anticipate the priorities on the control in emergency situations, is described. Furthermore, some simulations will allow the virtual testing for the future implementation in demonstrators. The presented work is the core of DESERVE project, and it is developed in parallel with Driver behaviour and HMI activities (SP3). This work presents some of the achievements in SP2, mainly the application platform integration in one of the demonstrators, along with the arbitration and sharing control, based on intelligent techniques (Fuzzy logic). simulation shows the feasibility of proposal. This approach will be tested, integrated and validated in a real vehicle in the next stages of the project.

关键词： ADAS embedded systems Arbitration Control Virtual testing modelling

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Data Mining in System-Level Design Space Exploration of embedded systems 1

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20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Richthammer, Valentina Scheinert, Tobias Glass, Michael Ulm Univ Inst Embedded Syst Real Time Syst Ulm Germany

ISBN: (数字)9783030609399

ISBN: (纸本)9783030609399;9783030609382

With increasingly complex applications and architectures, the task of determining Pareto-optimal implementations at the system level becomes a challenge even for state-of-the-art Design Space Exploration (DSE) methodologies. In this field, nature-inspired techniques such as Evolutionary Algorithms (EAs) are frequently employed, since they are well-suited to the multi-objective and hard-constrained nature of the DSE optimization problem. On the other hand, meta-heuristic approaches are problem-agnostic and are often observed to converge relatively quickly. Furthermore, this type of optimization lacks explainability, i.e. the way in which the optimization algorithm arrives at improved solutions as well as the individual contributions of design decisions to the resulting quality of a solution are not at all clear - and are consequently not utilized during DSE as of yet. To remedy this, we propose the integration of automated data-mining techniques into state-of-the-art DSE flows. Data mining is, thereby, used for (a) the automatic extraction and generation of previously untapped information from the optimization process to be (b) incorporated into the DSE to enhance optimization quality. We present a variety of ways to extract and include relevant knowledge during DSE, as well as (c) several possibilities to gain insight into the interdependence between decision variables and optimization objectives. Experimental results for benchmark systems for large-scale many-cores to networked embedded systems demonstrate the potential of the proposed techniques to improve the quality of the optimized implementations at no DSE-time overhead.

关键词： Design automation Knowledge discovery

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A polymorphic register file for matrix operations

A polymorphic register file for matrix operations

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Ciobanu, CǍtǍlin Kuzmanov, Georgi Gaydadjiev, Georgi Ramirez, Alex Computer Engineering Laboratory Electrical Engineering Department Delft University of Technology Netherlands Barcelona Supercomputing Center Universitat Politècnica de Catalunya Spain

ISBN: (纸本)9781424479382

Previous vector architectures divided the available register file space in a fixed number of registers of equal sizes and shapes. We propose a register file organization which allows dynamic creation of a variable number of multidimensional registers of arbitrary sizes referred to as a Polymorphic Register File. Our objective is to evaluate the performance benefits of the proposed organization. simulation results using real applications (Floyd and CG) suggest speedups of up to 3 times compared to the Cell SPU for Floyd and 2 times compared to a one dimensional vectorized version of the sparse matrix vector multiplication. Moreover, in the same experimental context, a large reduction in the number of executed instructions of up to 3000 times for Floyd and 2000 times for sparse matrix vector multiplication is achieved. ©2010 IEEE.

关键词： Vectors

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A Fine-Granularity Image Pyramid Accelerator for embedded Processors 1

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20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Tsai, Chun-Jen Wang, Chiang-Yi Natl Chiao Tung Univ Dept Comp Sci Hsinchu Taiwan

ISBN: (数字)9783030609399

ISBN: (纸本)9783030609399;9783030609382

Image-pyramid generator is an important component for many computer vision applications. Due to the complexity of image scaling operations, embedded application processors usually generate three- or four-level image pyramids for vision applications. In this paper, we present an image pyramid accelerator for embedded processors that generates image pyramids of up to 24-levels of down-sampled resolutions for the input image. Since image pyramids are crucial for the coarse-to-fine analysis of many computer vision problems, more resolution levels in the image pyramid can improve the parameter-estimation accuracy. Furthermore, the down-sampling filters used in the proposed design is based on a long-tap Sine-windowed Sinc function filter. Therefore, it preserves more image details than other low-complexity filters such as the bilinear or the bicubic interpolation filter. The proposed circuit is verified on an FPGA development board with a Xilinx Kintex-7 device and will be made open-source. The experimental results show that the design is very promising for real-time computer vision applications.

关键词： Image pyramid Down-sampling filter computer vision Coarse-to-fine processing Hardware-software codesign

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Compilation and simulation tool chain for memory aware energy optimizations

Compilation and simulation tool chain for memory aware energ...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Verma, Manish Wehmeyer, Lars Pyka, Robert Marwedel, Peter Benini, Luca Univ Dortmund Dept Comp Sci 12 D-44221 Dortmund Germany Univ Bologna DEIS I-40136 Bologna Italy

ISBN: (纸本)3540364102

Memories are known to be the energy bottleneck of portable embedded devices. Numerous memory aware energy optimizations have been proposed. However, both the optimization and the validation are performed in an ad-hoe manner as a coherent optimizing compilation and simulation framework does not exist as yet. In this paper, we present such a framework for performing memory hierarchy aware energy optimization. Both the compiler and the simulator are configured from a single memory hierarchy description. Significant savings of up to 50% in the total energy dissipation are reported.

关键词： Program compilers

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HARPA: Solutions for Dependable Performance under Physically Induced Performance Variability 15

HARPA: Solutions for Dependable Performance under Physically...

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international conference on embedded computer systems architectures modeling and simulation

作者： Rodopoulos, Dimitrios Corbetta, Simone Massari, Giuseppe Libutti, Simone Catthoor, Francky Sazeides, Yiannakis Nicopoulos, Chrysostomos Portero, Antoni Cappe, Etienne Vavrik, Radim Vondrak, Vit Soudris, Dimitrios Sassi, Federico Fritsch, Agnes Fornaciari, William NTUA ECE ICCS MicroLab Athens Greece SSET Imec Leuven Belgium Katholieke Univ Leuven ESAT Leuven Belgium UCY multiCAL Nicosia Cyprus DEIB POLIMI Milan Italy IT4Innovations VSB TUO Poruba Czech Republic Thales Grp La Defense France Henesis Srl Parma Pr Italy

ISBN: (纸本)9781467373111

Transistor miniaturization, combined with the dawn of novel switching semiconductor structures, calls for careful examination of the variability and aging of the computer fabric. Time-zero and time-dependent phenomena need to be carefully considered so that the dependability of digital systems can be guaranteed. Already, architectures contain many mechanisms that detect and correct physically induced reliability violations. In many cases, guarantees on functional correctness come at a quantifiable performance cost. The current paper discusses the FP7-612069-HARPA project of the European Commission and its approach towards dependable performance. This project provides solutions for performance variability mitigation, under the run time presence of fabric variability/aging and built-in reliability, availability and serviceability (RAS) techniques. In this paper, we briefly present and discuss modeling and mitigation techniques developed within HARPA, covering many abstractions of digital system design: from the transistor to the application layer.

关键词： Degradation Dynamic Voltage and Frequency Scaling embedded Computing High Performance Computing Performance Vulnerability Factor Resource Management Variability

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