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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

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Intelligent agents and BIST/BISR - working together in distributed systems

Intelligent agents and BIST/BISR - working together in distr...

引用

IEEE international Test conference

作者： L. Miclea E. Szilard A. Benso Department of Automation Technical University of Cluj Napoca Cluj-Napoca Romania Dipartimento di Automatica e Informatica Politecnico di Turino Torino Italy

This paper presents an attempt of using intelligent agents for testing and repairing a distributed system, whose elements may or may not have embedded BIST (built-in self-test) and BISR (built-in self-repair) facilities. The agents are software modules that perform monitoring, diagnosis and repair of the faults. Together they form a society whose members communicate, set goals and solve tasks. To demonstrate the idea we used the Zeus agent development environment. Two examples of distributed systems are presented in order to illustrate the cooperative model for fault diagnosis and repair.

关键词： Intelligent agent Built-in self-test System testing Automatic testing Fault diagnosis computerized monitoring Software standards Computational modeling computer simulation Automation

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Design and evaluation of a multimedia computing architecture based on a 3D graphics pipeline

Design and evaluation of a multimedia computing architecture...

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international conference on Application Specific systems (ASAP), architectures and Processors

作者： C.Y. Chung R.A. Managuli Yongmin Kim University of Washington Seattle WA USA

With the innovation and integration of media objects in multimedia applications, the importance of architectural support for different types of media objects, e.g., image, video and graphics, in one platform has significantly increased. While several approaches based on vector or VLIW (very long instruction word) architectures, e.g., Vector-IRAM and Imagine, have been pursued, they are not as effective as dedicated graphics pipelines for high-performance 3D graphics. We have explored a new programmable computing architecture based on a 3D graphics pipeline, which utilizes dedicated hardware resources in the 3D graphics pipeline for other types of multimedia computing. Adding programmable flexibility to a graphics pipeline for texture mapping has proven to be effective, e.g., pixel shader. However, due to the diversity of imaging and video processing applications, there are several challenges associated with converting a fixed graphics pipeline to a flexible multimedia computing engine. In this paper, we identify the additional architectural requirements, introduce the proposed architecture with extension details, and present the results of the performance evaluation. With cycle-accurate simulation of several benchmark functions, we have verified that the proposed architecture outperforms a modem powerful media processor in imaging and video processing by a factor of 1.3 to 7.5. The 3D graphics performance would not change much because the additional pipeline stages for the extension result in longer pipeline latency but similar throughout.

关键词： Multimedia computing computer architecture Graphics Pipelines VLIW Technological innovation Hardware Engines Computational modeling Modems

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Image coding/reconstruction and matching using a parallel distributed Hebbian architecture

Image coding/reconstruction and matching using a parallel di...

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international Joint conference on Neural Networks (IJCNN)

作者： K.P. Lam Department of Systems Engineering & Engineering Management Chinese University of Hong Kong New Territories Hong Kong China

A high-gain, post-annealing, generalized Hebbian algorithm is proposed and observed to have chaotic learning behavior. It lends itself readily to a highly efficient parallel distributed architecture for principal components computation. The work is extended to a convergence accelerator that uses the chaotic pattern learned during the first few epochs for an iterative weight-change procedure. Applications of using the parallel architecture for image encoding, reconstruction, and matching are described. Successful simulation results in yielding good quality reconstructed images and photo/sketch matching are reported.

关键词： Image coding Image reconstruction Chaos Iterative algorithms computer architecture Concurrent computing Distributed computing Convergence Parallel architectures Computational modeling

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Controlling hopping height of a pneumatic monopod

Controlling hopping height of a pneumatic monopod

引用

IEEE international conference on Robotics and Automation (ICRA)

作者： K. Harbick G.S. Sukhatme Robotics Research Laboratories Department of Computer ScienceRobotic Embedded Systems Laboratory University of Southern California Los Angeles CA USA

We describe a model-based height controller for a hopping robot with a pneumatically powered leg. The controller explicitly models variation in the leg angle and height. Using an explicit model of the physics of the pneumatic spring and some symmetry assumptions, we derive the desired leg-length setting to regulate apex hopping height using a PD controller. simulation experiments of hopping in the sagittal plane show reasonable height regulation. For low-speed running, we take advantage of the small variations in the leg angle about the vertical, and demonstrate that the original symmetry assumptions may be relaxed by restricting the leg angle to /spl pi//2. simulations show that the restricted model outperforms the original model by a small but significant amount.

关键词： Leg Springs Velocity control Legged locomotion Power system modeling Control systems Laboratories Physics Navigation Foot

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A merged multiplier-accumulator for high speed signal processing applications

A merged multiplier-accumulator for high speed signal proces...

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international conference on Acoustics, Speech, and Signal Processing (ICASSP)

作者： Ayman A. Fayed Magdy A. Bayoumi The Center for Advanced Computer Studies University of Louisiana Lafayette Lafayette LA USA

In an attempt to improve the speed of signal processing VLSI systems, a new architecture for high speed Multiply Accumulate Units is proposed. The architecture is based on Binary trees constructed using 4-2 compressor circuits. Increasing the speed of operation is achieved by taking advantage of the available free input lines of the 4-2 compressors, which result from the parallelogram shape of the generated partial products, and using the bits of the accumulated value to fill in these gaps. This results in merging the accumulation operation within the multiplication process. An 8-bit Multiplier Accumulator prototype circuit using the proposed architecture is prototyped in 0.35 micron double metal CMOS technology and simulated using hspice. simulation results at 3.3 V show that the proposed architecture has a delay of 4.26 ns with a 16.8 delay savings. At 150 MHz operating frequency, the power consumption is 324 mWatts with a 23.04% power saving compared to other architectures not using the merging technique.

关键词： CMOS technology Logic gates Prototypes CMOS integrated circuits Digital filters Adders Semiconductor device modeling

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Full-system timing-first simulation 02

Full-system timing-first simulation

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Proceedings of the 2002 ACM SIGMETRICS international conference on Measurement and modeling of computer systems

作者： Carl J. Mauer Mark D. Hill David A. Wood University of Wisconsin---Madison

ISBN: (纸本)9781581135312

computer system designers often evaluate future design alternatives with detailed simulators that strive for functional fidelity (to execute relevant workloads) and performance fidelity (to rank design alternatives). Trends toward multi-threaded architectures, more complex micro-architectures, and richer workloads, make authoring detailed simulators increasingly difficult. To manage simulator complexity, this paper advocates decoupled simulator organizations that separate functional and performance concerns. Furthermore, we define an approach, called timing-first simulation, that uses an augmented timing simulator to execute instructions important to performance in conjunction with a functional simulator to insure correctness. This design simplifies software development, leverages existing simulators, and can model micro-architecture timing in *** describe the timing-first organization and our experiences implementing TFsim, a full-system multiprocessor performance simulator. TFsim models a pipelined, out-of-order micro-architecture in detail, was developed in less than one person-year, and performs competitively with previously-published simulators. TFsim's timing simulator implements dynamically common instructions (99.99% of them), while avoiding the vast and exacting implementation efforts necessary to run unmodified commercial operating systems and workloads. Virtutech Simics, a full-system functional simulator, checks and corrects the timing simulator's execution, contributing 18-36% to the overall run-time. TFsim's mostly correct functional implementation introduces a worst-case performance error of 4.8% for our commercial workloads. Some additional simulator performance is gained by verifying functional correctness less often, at the cost of some additional performance error.

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A structured approach to embedded control systems implementation

A structured approach to embedded control systems implementa...

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IEEE international conference on Control Applications

作者： Broenink, JF Hilderink, GH Univ Twente Control Lab Fac EE NL-7500 AE Enschede Netherlands

ISBN: (纸本)0780367332

The method presented here, aims at supporting the development of control software for embedded control systems. The method considers the implementation process as a stepwise refinement from physical system models and control laws to efficient control computer code, and that all phases are verified by simulation. simulation is also used as verification tool during physical-system modeling and control law development. Data flow diagrams are used to describe the control software throughout the whole implementation process. Since we aim at heterogeneous distributed processors as target hardware, we use a link driver library based on the CSP channel concept. Communication peculiarities are encapsulated by the link drivers.

关键词： embedded control systems multiparadigm modeling software implementation

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Workshop on systems, architectures, modeling and simulation, SAMOS 2001

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Workshop on systems, architectures, modeling, and simulation, SAMOS 2001

ISBN: (纸本)3540433228

The proceedings contain 18 papers. The special focus in this conference is on System-Level Design, simulation, Compiler and Mapping Technology. The topics include: Consistency analysis of reconfigurable dataflow specifications;a methodology to design programmable embedded systems;flexibility/cost-tradeoffs of platform-based systems;towards efficient design space exploration of heterogeneous embedded media systems;an overview of methodologies and tools in the field of system-level design;translating imperative affine nested loop programs into process networks;structured scheduling of recurrence equations;exact partitioning of affine dependence algorithms;generation of distributed loop control;processor architectures for multimedia applications;microcoded reconfigurable embedded processors;a reconfigurable functional unit for trimedia/CPU64;caches with compositional performance;design of an adaptive architecture for energy efficient wireless image communication;design of cam-e-leon, a run-time reconfigurable web camera;a 2D addressing mode for multimedia applications and a java-enabled DSP.

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System level design with SPADE: an M-JPEG case study

System level design with SPADE: an M-JPEG case study

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international conference on computer Aided Design (ICCAD 2001)

作者： Lieverse, P Stefanov, T van der Wolf, P Deprettere, E Delft Univ Technol Delft Netherlands

ISBN: (纸本)0780372476

In this paper we present and evaluate the SPADE (System level Performance Analysis and Design space Exploration) methodology through an illustrative case study. SPADE is a method and tool for architecture exploration of heterogeneous signal processing systems. In this case study we start from an M-JPEG application and use SPADE to evaluate alternative multi-processor architectures for implementing this application. SPADE follows the Y-chart paradigm for system level design;application and architecture are modeled separately and mapped onto each other in an explicit design step. SPADE permits architectures to be modeled at an abstract level using a library of generic building blocks, thereby reducing the cost of model construction and simulation. The case study shows that SPADE supports efficient exploration of candidate architectures;models can be easily constructed, modified and simulated in order to quickly evaluate alternative system implementations.

关键词： system level design design space exploration application modeling architecture modeling M-JPEG

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1st international Workshop on embedded Software, EMSOFT 2001

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1st international Workshop on embedded Software, EMSOFT 2001

ISBN: (纸本)3540426736

The proceedings contain 34 papers. The special focus in this conference is on embedded Software. The topics include: Heterogeneous modeling support for embedded systems design;hierarchical hybrid modeling of embedded systems;some synchronization issues when designing embedded systems from components;synchronous programming techniques for embedded systems;from requirements to validated embedded systems;usage scenarios for an automated model compiler;from asynchrony to synchrony and back;verification of embedded software;a network-centric approach to embedded software for tiny devices;storage allocation for real-time, embedded systems;interface theories for component-based design;a time-triggered language for embedded programming;directions in functional programming for real-time applications;rate-based resource allocation models for embedded systems;the temporal specification of interfaces in distributed real-time systems;system-level types for component-based design;embedded software implementation tools for fully programmable application specific systems;compiler optimizations for adaptive EPIC processors;embedded software market transformation through reusable frameworks;an end-to-end methodology for building embedded systems;an implementation of scoped memory for real-time java;bus architectures for safety-critical embedded systems;using multiple levels of abstractions in embedded software design;hierarchical approach for design of multi-vehicle multi-modal embedded software;adaptive and reflective middleware for distributed real-time and embedded systems;modeling real-time systems;a toolset for constructing and analyzing component based embedded systems;embedded software in network processors;design of autonomous, distributed systems;formalizing software architectures for embedded systems;reliable and precise WCET determination for a real-life processor and embedded systems and real-time programming.

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