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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

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A study on transmitting MPEG-I video over a FDDI network

A study on transmitting MPEG-I video over a FDDI network

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： J.K.-Y. Ng Computing Studies Department Hong Kong Baptist University Hong Kong China

This paper presents two schemes to improve the transmission of real-time MPEG-I video over a FDDI network. Multiple classes of MPEG-I video will be used in the study and what makes this simulation study different from the others is the different kinds of MPEG-I video data we used. These data are captured from real video programmes and we categorized these video clips according to their workload characteristics. The performance of the FDDI network is examined in terms of the maximum number of MPEG-I video streams got transmitted over the network without missing their deadlines. This simulation study observed that by employing the Intentional-delay scheme, we can improve the performance by an average of 35%. From another set of simulation experiment, when applying the Frame-grouping scheme for MPEG-I transmission, we can improve the performance up to 150%.

关键词： FDDI Video compression Streaming media Computational modeling Transform coding computer networks Bit rate MPEG standards Protocols Channel allocation

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Toward adaptable distributed real-time computer systems

Toward adaptable distributed real-time computer systems

引用

IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： M.D. Baba H. Ekiz A. Kutlu E.T. Powner School of Engineering Institute Technology MARA Shah Alam Selangor Darul Ehsan Malaysia School of Engineering University of Sussex Brighton UK

A distributed real-time computer system consists of several processing nodes which are interconnected by communication channel. For a safety critical application the real-time computer system should maintains timely and dependable services despite component failures or environmental changes. In this paper we present a framework of an adaptable distributed real-time computer system which can adjusts its operating strategies in response to changing application environments or variation in the fault patterns. The proposed adaptable real-time system (ARTS) is based on the integration of the scheduling strategy using imprecise technique (IT) with the fault tolerance mechanism. In our simulation study the performance of an ARTS of a controller area network (CAN) based distributed system is evaluated as to whether the timing constraints of the automotive benchmark signals can be satisfied for normal, overload, and degraded operational modes. Our investigation also shows that the quality of service maintained by the ARTS can be further improve by varying the workload.

关键词： Real time systems Distributed computing Subspace constraints Application software Communication channels Safety computer applications Processor scheduling Fault tolerant systems Computational modeling

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Adaptive routing in k-ary n-cube multicomputers

Adaptive routing in k-ary n-cube multicomputers

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international conference on Parallel and Distributed systems (ICPADS)

作者： C.S. Yang Y.M. Tsai Y.L. Tsai Institute of Computer and Information Engineering National Sun Yat-Sen University Kaohsiung Taiwan Vocational Training Center Department of Labor Affairs Kaohsiung Municipal Government Taiwan

Wormhole routing makes the communication latency insensitive of the network diameter and reduces the buffer size of each router. It has been widely adopted in many new generation distributed memory multiprocessor systems (DMMPs). The concept of virtual system is invented for deadlock-free routing design. Using a great deal of virtual channels is quite expensive to be implemented in practice and is not limitless. In this paper experimental results are given to evaluate the tradeoff between network congestion delay and throughput. Some results show that the congestion delay does not reduce visibly when the number of virtual channels is greater than that of internal channels by 2. A reasonable number of virtual channels can be derived from the results. A virtual networks system using only four virtual networks, two virtual channels in each direction, is presented. It shows that the minimum number of virtual networks to support a partially adaptive, minimal and deadlock free routing in k-ary n-cubes is just four. It uses only four virtual networks but can get a high degree of adaptiveness and high traffic capacity. simulation results are presented to verify the performance.

关键词： Routing Delay System recovery Costs Communication switching Intelligent networks Multiprocessing systems Throughput Computational modeling Parallel architectures

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Parsim - message PAssing computer SIMulator

Parsim - message PAssing computeR SIMulator

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Proceedings of the IEEE 1st international conference on Algorithms and architectures for Parallel Processing. Part 1 (of 2)

作者： Symons, Anthony Narasimhan, V.Lakshmi Univ of Queensland

The task of predicting the performance of an application on a new platform given its performance on a particular computer system is fairly difficult. Significant degree of exhaustive modeling of both algorithms and architectures is required before a reasonable prediction can be attempted. This paper describes a general purpose simulator for message passing multiprocessors (Parsim), which facilitates systems modeling. Besides monitoring a number of system parameters, Parsim permits easy reconfiguration of topology and algorithm mappings. Parsim has been used to predict the performance of a number of different algorithms such as Fast Fourier Transform, Livermore loops and integer programming, on a variety of topologies such as transputer hypercubes, transputer meshes and a cluster of workstations on an ethernet backbone.

关键词： computer simulation

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Model-embedded on-line problem solving environment for chemical engineering

Model-embedded on-line problem solving environment for chemi...

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Proceedings of the 1995 1st IEEE international conference on Engineering of Complex computer systems

作者： Karsai, Gabor Sztipanovits, Janos Franke, Hubertus Padalkar, Samir DeCaria, Frank Vanderbilt Univ Nashville United States

The building of custom monitoring, control, simulation and diagnostics applications for complex chemical plants necessitates the integration of models into the problem solving process. This paper describes a system and its practical applications that supports this activity. It is based on the Multigraph Architecture, which is a generic framework for building these model-based systems. The paper discusses the modeling paradigms used, how the applications are generated, and some practical, existing applications.

关键词： Online systems

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international conference and Exhibition on High-Performance Computing and Networking, 1995

International Conference and Exhibition on High-Performance ...

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international conference and Exhibition on High-Performance Computing and Networking, HPCN Europe 1995

ISBN: (纸本)9783540593935

The proceedings contain 153 papers. The special focus in this conference is on Parallel Programming and Tools. The topics include: Exploiting massively parallel architectures for the solution of diffusion and propagation problems;summarising an experiment in parallel programming language design;language, compiler and parallel database support for I/O intensive applications;using optimistic execution techniques as a parallelisation tool for general purpose computing;system management tools for SHPC systems;multi-operation multi-machine scheduling;a PVM tool for automatic test generation on parallel and distributed systems;obtaining high performance data transmission in the internet;parallel processing on heterogeneous networks for GIS applications;block loss reduction in ATM networks;characterizing the resource demands of TCP/IP;implementing communication latency hiding in high-latency computer networks;modeling speedup of SPMD applications on the lntel paragon;a hierarchical approach to workload characterization for parallel systems;performance analysis of cray t3d and connection machine CM-5;numerically intensive computing as a benchmark for parallel computer architectures;a preliminary performance evaluation of the quadrics architecture with the DARPA image understanding benchmark;an integrated approach to performance and testing analysis for parallel systems;structured parallelisation of the flow simulation package TRIWAQ;high-performance computing and networking for climate research;parallel solution strategies for triangular systems arising from oil reservoir simulations;parallelisation of surface-related multiple elimination;a parallel semi-implicit method for 3D nonlinear magnetohydrodynamics and the pandore data-parallel compiler and its portable runtime.

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Performance comparison of real-time architectures using simulation

Performance comparison of real-time architectures using simu...

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IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Heejo Lee K. Toda Jong Kim K. Nishida E. Takahashi Y. Yamaguchi Department of Computer Science & Engineering Pohang University of Science and Technology Pohang South Korea Electro Technical Laboratory Tsukuba Japan

This paper presents a performance comparison of real-time system architectures. A discrete event-driven, task-based simulator is developed for evaluating the performance of parallel and distributed real-time systems. Real-time system components such as processor, network architectures, and scheduling policy are included in the simulator. simulation results show that priority-based communication and scheduling are more suitable for real-time systems than FIFO-based. The strategy of having a dedicated processor, which produces no effect on task execution by scheduling and packet/interrupt handling, is proven to enhance schedulability and predictability. This paper suggests a method for finding an appropriate real-time architecture for users having real-time requirements through the performance prediction of real-time systems.

关键词： Real time systems Discrete event simulation Job shop scheduling Processor scheduling Computational modeling Predictive models computer architecture computer aided manufacturing computer simulation computer science

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RASSP signal processing architectures

RASSP signal processing architectures

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conference on Advanced Signal Processing Algorithms

作者： SHIRLEY, F BASSETT, B LETELLIER, JP LOCKHEED SANDERS INC NASHUANH 03061

ISBN: (纸本)0819419222

The rapid prototyping of application specific signal processors (RASSP) program is an ARPA/tri-service effort to dramatically improve the process by which complex digital systems, particularly embedded signal processors, are specified, designed, documented, manufactured, and supported. The domain of embedded signal processing was chosen because it is important to a variety of military and commercial applications as well as for the challenge it presents in terms of complexity and performance demands. The principal effort is being performed by two major contractors, Lockheed Sanders (Nashua, NH) and Martin Marietta (Camden, NJ). For both, improvements in methodology are to be exercised and refined through the performance of individual 'Demonstration' efforts. The Lockheed Sanders' Demonstration effort is to develop an infrared search and track (IRST) processor. In addition, both contractors' results are being measured by a series of externally administered (by Lincoln Labs) six-month Benchmark programs that measure process improvement as a function of time. The first two Benchmark programs are designing and implementing a synthetic aperture radar (SAR) processor. Our demonstration team is using commercially available VME modules from Mercury computer to assemble a multiprocessor system scalable from one to hundreds of Intel i860 microprocessors. Custom modules for the sensor interface and display driver are also being developed. This system implements either proprietary or Navy owned algorithms to perform the compute-intensive IRST function in real time in an avionics environment. Our Benchmark team is designing custom modules using commercially available processor ship sets, communication submodules, and reconfigurable logic devices. One of the modules contains multiple vector processors optimized for fast Fourier transform processing. Another module is a fiberoptic interface that accepts high-rate input data from the sensors and provides video-rate output data to a

关键词： RAPID PROTOTYPING embedded SIGNAL PROCESSORS RASSP ARCHITECTURE SELECTION simulation VHDL VIRTUAL PROTOTYPE INSTRUCTION SET ARCHITECTURE PRODUCT METRICS

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modeling and efficient distributed simulation of multistage interconnection networks

Modeling and efficient distributed simulation of multistage ...

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IEEE international conference on Algorithms and architectures for Parallel Processing (ICAP)

作者： Yong Meng Teo Seng Chuan Tay Department of Information Systems & Computer Science National University of Singapore Singapore Singapore

ISBN: (纸本)0780320182

Multistage interconnection networks are used in a number of application areas such as parallel computers and high-speed communication systems. As the performance of these systems lies on an efficient design of the interconnection network, a thorough analysis of the network's performance is important. Mathematical analysis so far provides inadequate results and simulation analysis using a uniprocessor usually requires extremely long run time to evaluate large networks. This paper addresses the use of parallel simulation techniques to speedup the simulation of multistage interconnection networks. The conventional null-message approach for resolving deadlock problem in conservative simulation may cause livelock if lookahead is not guaranteed. We propose a deadlock/livelock free scheme using null messages, but without the guaranteed lookahead, to coordinate the simulation, and different partitioning techniques for mapping of the simulation program onto multicomputers. A flushing mechanism is also used to resolve the null-message explosion problem. Our analysis shows that the proposed flushing mechanism effectively reduces the number of null messages from exponential to linear.< >

关键词： Multiprocessor interconnection networks Computational modeling System recovery Application software computer networks Concurrent computing Performance analysis Mathematical analysis Analytical models Explosions

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Benchmarking parallel simulation algorithms

Benchmarking parallel simulation algorithms

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IEEE international conference on Algorithms and architectures for Parallel Processing (ICAP)

作者： L. Barriga R. Ronngren R. Ayani Dept. of Teleinformatics R. Inst. of Technol. Stockholm Sweden Department of Teleinfonnatics Computer Systems Laboratory Royal Institute of Technology Stockholm Sweden

Parallel simulation has been an active research area for more than a decade. The parallel simulation community needs a common benchmark suite for performance evaluation of parallel simulation environments. Performance evaluation of a parallel simulation environment is harder than evaluating a parallel processing system, since the underlying system is nor only composed of architecture and operating system, but also of simulation kernel. Thus, simulation kernel designers often confront a twofold task: (i) to evaluate how efficiently their simulation kernel runs on certain architectures; and (ii) to evaluate how simulation problems scale using this kernel In this paper we advocate an incremental benchmarking methodology that focuses on the evaluation of a parallel simulation system which is based on Time Warp. We start from a reduced set of ping models that can effectively estimate the various overheads, contention and latencies of Time Warp running on a multiprocessor. The benchmark suite has been used to locate several sources of overhead in an existing Time Warp implementation. Using this benchmark suite we also compare the performance of the improved version of the Time Warp implementation with the original one.

关键词： Computational modeling Discrete event simulation computer simulation Kernel Concurrent computing Parallel processing Operating systems Very large scale integration

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