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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

共 2730 条记录，以下是251-260 订阅

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Characterizing communication behavior of dataflow programs using trace analysis 14

Characterizing communication behavior of dataflow programs u...

引用

14th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2014

作者： Janneck, Jorn W. Casale Brunet, Simone Mattavelli, Marco Department of Computer Science Lund University Sweden EPFL SCI STI MM Ecole Polytechnique Fédérale de Lausanne Switzerland

ISBN: (纸本)9781479937707

This paper investigates the relationship between two ways of analyzing streaming systems: trace analysis for dataflow programs with firing, and network calculus for network flows. While the former focuses on the structure of the dataflow computation while idealizing the interaction with the environment, the latter characterizes the temporal properties of flows of data, largely abstracting from the computations that connect them. In this work, we show how a trace analysis can be used to derive a description of communication behavior of a dataflow program in terms of network calculus, which is then applied to answering a question about the buffer sizing. The example being studied is an MPEG-4 video decoder. © 2014 IEEE.

关键词： Calculations

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Efficient Runtime Support for embedded MPSoCs

Efficient Runtime Support for Embedded MPSoCs

引用

13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Theodoropoulos, Dimitris Pratikakis, Polyvios Pnevmatikatos, Dionisios Fdn Res & Technol Hellas FORTH Inst Comp Sci Comp Architecture & VLSI Syst Lab GR-70013 Iraklion Greece

ISBN: (纸本)9781479901036

Recently, many software runtime systems have been proposed that allow developers to efficiently map applications to contemporary consumer electronic devices and high-performance academic processing platforms. Most of these runtime systems employ advanced scheduling techniques for automatic task assignment to all available processing elements. However, they focus on a particular environment and architecture, and it is not easy to port them to reconfigurable embedded MPSoCs. As a consequence, in the embedded community, researchers implement hardwired application-specific task schedulers, which can not be used by other embedded MPSoCs. To address this problem, in this paper we propose a lightweight runtime software framework for reconfigurable shared-memory MPSoCs, that integrate a master embedded processor connected to slave cores. Similarly to many of the aforementioned advanced runtime systems, we adopt a task-based programming model that uses simple, pragma-based annotations of the application software, in order to dynamically resolve task dependencies. Our runtime system supports heterogeneity in the hardware resources, and is also low-overhead to account for possible limitations in their processing capabilities and available on-chip memory. To evaluate our proposal, we have prototyped an MPSoC with seven slaves to a Xilinx ML605 FPGA board. We run three micro-benchmarks that achieve a performance speedup of 3.8x, 7x and 5.8x, and energy consumption of 27%, 14% and 18% respectively, compared to a single-core baseline system with no runtime support.

关键词： runtime support embedded MPSoCs FPGAs

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Rapid implementation and optimisation of DSP systems on SoPC heterogeneous platforms

Rapid implementation and optimisation of DSP systems on SoPC...

引用

5th international Workshop on embedded computer systems - architectures, modeling, and simulation

作者： McAllister, J Woods, R Reilly, D Fischaber, S Hasson, R Queens Univ Belfast ECIT Belfast BT3 9DT Antrim North Ireland

ISBN: (纸本)354026969X

The emergence of programmable logic devices as processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimization of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working implementation on a heterogeneous multiprocessor/field programmable gate array platform, or a standalone system on programmable chip solution. Two particular focuses for Abhainn are the automated but configurable realisation of inter-processor communuication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimization. This paper outlines the approaches employed in both these particular instances.

关键词： embedded systems

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Dynamic Re-Vectorization of Binary Code 15

Dynamic Re-Vectorization of Binary Code

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Hallou, Nabil Rohou, Erven Clauss, Philippe Ketterlin, Alain INRIA Rennes Team ALF Rennes France Univ Strasbourg CNRS Team CAMUS INRIAICube Lab Strasbourg France

ISBN: (纸本)9781467373111

In many cases, applications are not optimized for the hardware on which they run. Several reasons contribute to this unsatisfying situation, including legacy code, commercial code distributed in binary form, or deployment on compute farms. In fact, backward compatibility of ISA guarantees only the functionality, not the best exploitation of the hardware. In this work, we focus on maximizing the CPU efficiency for the SIMD extensions and propose to convert automatically, and at runtime, loops vectorized for an older version of the SIMD extension to a newer one. We propose a lightweight mechanism, that does not include a vectorizer, but instead leverages what a static vectorizer previously did. We show that many loops compiled for x86 SSE can be dynamically converted to the more recent and more powerful AVX;as well as, how correctness is maintained with regards to challenges such as data dependences and reductions. We obtain speedups in line with those of a native compiler targeting AVX. The re-vectorizer is implemented inside a dynamic optimization platform;it is completely transparent to the user, does not require rewriting binaries, and operates during program execution.

关键词： binary code computer hardware binary form single instruction multiple datastream Leverage compilers Legacy accuracy class Loops backward compatibility deployment

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Thermal optimization for micro-architectures through selective block replication

Thermal optimization for micro-architectures through selecti...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Diamantopoulos, Dionisios Siozios, Kostas Xydis, Sotiris Soudris, Dimitrios School of Electrical and Computer Engineering National Technical Univeristy Athens Greece

ISBN: (纸本)9781457708008

Increased power densities result to higher on-chip temperatures, which in turn creates numerous problems tightly firmed to reliability issues. This problem is expected to become even more severe for deep-submicron technologies. In this paper, we propose a thermal-aware exploration framework at the microarchitecture level for temperature hotspots elimination through selective resource replication. Experimental results based on the LEON3 processor synthesized with a 45 nm technology library, shown that the proposed methodology leads to designs with fewer hotspots, while the maximal temperatures at these hotspots are also reduced. Specifically, temperature reduction of 17 Kelvin degrees is feasible, which leads to improvement against aging phenomena about 14%, with a controllable overhead in silicon area about 15%, as compared to conventional architecture design. © 2011 IEEE.

关键词： computer architecture

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TCEMC: A co-design flow for application-specific multicores

TCEMC: A co-design flow for application-specific multicores

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Jääskeläinen, Pekka O. Salminen, Erno O. De La Lama, Carlos S. Takala, Jarmo H. Martinez, Jose Ignacio Tampere University of Technology Department of Computer Systems Tampere Finland Universidad Rey Juan Carlos Department of Computer Architecture Móstoles Madrid Spain

ISBN: (纸本)9781457708008

Contemporary embedded systems are often designed as Multiprocessor System-on-Chips (MPSoC) which include multiple processors and other peripherals on a single chip. In contrast to general purpose multiprocessors, the design of an embedded MPSoC is usually customized to the requirements of the application domain. The need for fast time to market of new embedded MPSoC designs calls for a rapid design flow of the included customized processors. This paper proposes a Multicore Application-Specific Instruction Set Processor (MCASIP) co-design flow that exploits parallel programming languages as the application description format. The designer can capture the parallelism of the algorithm and exploit specialized instructions using a single high-level programming language. Parallelism of the designed MCASIP architectures can be scaled both at instruction and task levels, enabling easy exploration of the MCASIP design space. This paper describes the design flow and its key technical challenges, and demonstrates its scalability potential. The presented preliminary results show promise for an efficient multiprocessor design methodology. © 2011 IEEE.

关键词： embedded systems

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Model-Driven Robot-Software Design using integrated Models and Co-simulation

Model-Driven Robot-Software Design using integrated Models a...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Broenink, Jan F. Ni, Yunyun Robotics and Mechatronics group CTIT institute faculty of Electrical Engineering Mathematics and Computer Science University of Twente The Netherlands

ISBN: (纸本)9781467322973

The work presented here is on a methodology for design of hard real-time embedded control software for robots, i.e. mechatronic products. The behavior of the total robot system (machine, control, software and I/O) is relevant, because the dynamics of the machine influences the robot software. Therefore, we use two appropriate Models of Computation, which represent continuous-time equations for the machine / robot part, and discrete event / discrete time equations for the control software part. To compute (simulate) such combined models, co-simulation of these models is used. The design work can be done as a stepwise refinement process, whereby each step is verified via co-simulation. This in general yields a shorter design time, and a better quality product. The tools pass model-specific information between each other via parametrized tokens in the generated, high-level code to get a better separation of design steps. This allows for better quality of the models and more reuse, thus enhancing the efficiency of model-driven design for the (industrial) end user. The method is illustrated with a case study using the tools, some of which are at the prototype level. Especially the structuring of the models and regularly doing simulations (of which some can be 'repeated' as real experiments), is beneficial, shortening the development time and producing better models. Future work is to test the method on more complex cases, and to extend the method by detailing out the electronics and mechanics sub design flows.

关键词： Robot hard real-time machine IO Robot software computer software Software design computer programs MACHINE TOOL CONTROL Robot System Microelectromechanical devices Equation discrete-time

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Analyzing the performance and energy impact of 3D memory integration on embedded DSPs

Analyzing the performance and energy impact of 3D memory int...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Chang, Daniel W. Kim, Nam S. Schulte, Michael J. Department of Electrical and Computer Engineering University of Wisconsin Madison Madison WI United States Austin TX United States

ISBN: (纸本)9781457708008

Recently, three-dimensional integration technology has allowed researchers and designers to explore novel architectures for computing systems. Due to the memory-intensive nature of signal processing systems, DSPs can greatly benefit from 3D memory integration technology realized by vertically stacking high-density memory below processing cores. In this paper, we analyze the energy and performance impacts of 3D memory integration in DSP systems by exploring a wide variety of memory configurations the technology enables. Our analysis demonstrates that a 3D memory hierarchy can increase performance by an average of 20.6% while decreasing energy by 6.7% when compared to our baseline 2D memory hierarchy, with a processor similar to a Texas Instrument C67x DSP. This proposed memory architecture also allows us to scale the voltage and frequency to decrease energy consumption by an average of 23% without decreasing performance. © 2011 IEEE.

关键词： Memory architecture

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embedded computer systems: architectures, modeling, and simulation 1

引用

丛书名： Lecture Notes in computer Science

1000年

作者： Cristina Silvano Christian Pilato Marc Reichenbach

ISBN: (数字)9783031460777

ISBN: (纸本)9783031460760

This book constitutes the proceedings of the 22st international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2021, which took place in July 2022 in Samos, Greece. The 11 full papers and 7 short papers presented in this volume were carefully reviewed and selected from 45 submissions. The conference covers a wide range of embedded systems design aspects, including machine learning accelerators, and power management and programmable dataflow systems.

关键词： computer System Implementation Control Structures and Microprogramming Software Engineering/Programming and Operating systems Input/Output and Data Communications

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An embedded platform with duty-cycled radio and processing subsystems for wireless sensor networks

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Jin, Zhong-Yi Schurgers, Curt Gupta, Rajesh UCSD Dept. of Computer Science and Eng. UCSD Dept. of Electrical and Computer Eng.

ISBN: (纸本)9783540736226

Wireless sensor nodes are increasingly being tasked with computation and communication intensive functions while still subject to constraints related to energy availability. On these embedded platforms, once all low power design techniques have been explored, duty-cycling the various subsystems remains the primary option to meet the energy and power constraints. This requires the ability to provide spurts of high MIPS and high bandwidth connections. However, due to the large overheads associated with duty-cycling the computation and communication subsystems, existing high performance sensor platforms are not efficient in supporting such an option. In this paper, we present the design and optimizations taken in a wireless gateway node (WGN) that bridges data from wireless sensor networks to Wi-Fi networks in an on-demand basis. We discuss our strategies to reduce duty-cycling related costs by partitioning the system and by reducing the amount of time required to activate or deactivate the high-powered components. We compare the design choices and performance parameters with those made in the Intel Stargate platform to show the effectiveness of duty-cycling on our platform. We have built a working prototype, and the experimental results with two different power management schemes show significant reductions in latency and average power consumption compared to the Stargate.

关键词： embedded systems

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