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CamSim: A Distributed Smart Camera Network Simulator

CamSim: A Distributed Smart Camera Network Simulator

引用

IEEE international conference on Self-Adaptive and Self-Organizing systems Workshops, SASOW

作者： Lukas Esterle Peter R. Lewis Horatio Caine Xin Yao Bernhard Rinner Institute of Networked and Embedded Systems Alpen-Adria Universität Klagenfurt and Lakeside Labs Austria CERCIA University of Birmingham United Kingdom

Smart cameras allow pre-processing of video data on the camera instead of sending it to a remote server for further analysis. Having a network of smart cameras allows various vision tasks to be processed in a distributed fashion. While cameras may have different tasks, we concentrate on distributed tracking in smart camera networks. This application introduces various highly interesting problems. Firstly, how can conflicting goals be satisfied such as cameras in the network try to track objects while also trying to keep communication overhead low? Secondly, how can cameras in the network self adapt in response to the behavior of objects and changes in scenarios, to ensure continued efficient performance? Thirdly, how can cameras organise themselves to improve the overall network's performance and efficiency? This paper presents a simulation environment, called CamSim, allowing distributed self-adaptation and self-organisation algorithms to be tested, without setting up a physical smart camera network. The simulation tool is written in Java and hence allows high portability between different operating systems. Relaxing various problems of computer vision and network communication enables a focus on implementing and testing new self-adaptation and self-organisation algorithms for cameras to use.

关键词： Cameras Smart cameras Computational modeling conferences Algorithm design and analysis Distributed algorithms

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The impact of the AC922 Architecture on Performance of Deep Neural Network Training

The impact of the AC922 Architecture on Performance of Deep ...

引用

international conference on High Performance Computing & simulation (HPCS)

作者： Paweł Rościszewski Michał Iwański Paweł Czarnul Faculty of Electronics Telecommunications and Informatics Gdańsk University of Technology Poland IBM Systems IBM Poland

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

Practical deep learning applications require more and more computing power. New computing architectures emerge, specifically designed for the artificial intelligence applications, including the IBM Power System AC922. In this paper we confront an AC922 (8335-GTG) server equipped with 4 NVIDIA Volta V100 GPUs with selected deep neural network training applications, including four convolutional and one recurrent model. We report performance results depending on batch sizes and GPU selection and compare them with the results from another contemporary workstation based on the same set of GPUs - NVIDIA® DGX Station ™ . The results show that the AC922 performs better in all tested configurations, achieving improvements up to 10.3%. Profiling indicates that the improvement is due to the efficient I/O pipeline. The performance differences depend on the specific model, rather than on the model class (RNN/CNN). Both systems offer good scalability up to 4 GPUs. In certain cases there is a significant difference in performance depending on exactly which GPUs are used for computations.

关键词： Training Servers computer architecture Bandwidth Computational modeling Benchmark testing Machine learning

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Methodology for modeling visual flowchart control programs using net condition/event systems formalism in distributed environments

Methodology for modeling visual flowchart control programs u...

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： A. Lobov J.L.M. Lastra R. Tuokko V. Vyatkin Institute of Production Enginrering Tampere University of Technology Tampere Finland Department of Engineering Science Martin Luther University of Halle-Wittenberg Halle Germany

This paper addresses formal validation of distributed logic controllers represented in Visual Flowchart Language (VFL) that is a high-level programming language used in industrial automation. Traditional validation approaches based on simulation become obsolete in reconfigurable manufacturing systems where complex machines have decentralized control and are built by reuse of components. The source code based validation is also important for OEMs to unify their development procedures from embedded systems to machine controllers. For modeling the VFL design we used net condition/event systems (NCES) - a modular formalism developed for modeling systems with distributed states such as closed-loop control systems in distributed mechatronic devices. The methodology was implemented in software tools automatically generating the model's modules given the controller's source code. Then the hierarchical NCES model is assembled into a place/transition net that is subjected to model checking. The proposed approach facilitates integration of formal validation into software/hardware development in control systems' engineering.

关键词： Flowcharts Automatic control Distributed control Control systems Reconfigurable logic Logic programming computer languages Electrical equipment industry Industrial control Manufacturing industries

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Energy Conscious Simultaneous Voltage Scaling and On-chip Communication Bus Synthesis

Energy Conscious Simultaneous Voltage Scaling and On-chip Co...

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IFIP international conference on Very Large Scale Integration (VLSI-SoC)

作者： Sujan Pandey Tudor Murgan Manfred Glesner Institute of Microelectronics Systems Darmstadt University of Technology Darmstadt Germany

Due to the ever increasing trend of system complexity and technology scaling, synthesizing on-chip communication architecture appears to be a challenging task for the system designers. The traditional approaches are mostly based on the simulation of an entire system. However, the resulting architecture may not fulfil the requirements such as the performance, energy, size etc. and the computational cost of simulation based techniques is infeasible when exploring a large design space. This paper presents a simultaneous on-chip communication bus synthesis and voltage scaling approach, which is modeled in NLP (nonlinear programming) and finds an energy efficient minimum number of bus(es) and an optimal size of bus width by simultaneously performing resource selection, scheduling, binding and voltage scaling of an on-chip bus. The voltages (supply and body bias) are scaled to reduce the total energy consumption of a bus by exploiting the slack of each on-chip module. The experimental results conducted on real-life examples, demonstrate the synthesis of an energy efficient communication bus with total energy saving up to 57.1% by scaling its supply and body bias voltages

关键词： Voltage computer architecture Topology System-on-a-chip Computational modeling Energy consumption Energy efficiency Computational efficiency Libraries embedded system

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Wireless Sensor Networks: Trends, Power Consumption and Simulators

Wireless Sensor Networks: Trends, Power Consumption and Simu...

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Asia international conference on modeling & simulation

作者： Khawla Lahmar Rym Cheour Mohamed Abid University of Sfax National School of Engineers of Sfax Computer & Embedded Systems Sfax Tunisia

WSN technology involves a set of challenges ranging from determining resource characteristics of the wireless network, when and how to optimise energy and how much processing to do in each node, to principles for management of entire sensor networks and how the data produced by sensor networks can be managed, used and presented. A simulation environment seemed to be then essential, since the test of the hardware and software is hard and difficult. Beyond cost and time savings, the simulator offers the great opportunity to extend the potential and the features of WSN. As there are many simulators, we make an attempt in this paper to specify the important ones related to energy consumption. In fact, we discuss the performance, reliability and usefulness of each of them to better see the disadvantages of these simulators and their strong points to be able to develop a better model.

关键词： Wireless sensor networks Power demand Energy consumption Hardware Batteries Wireless communication computer architecture

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The FAST methodology for high-speed SoC/computer simulation 07

The FAST methodology for high-speed SoC/computer simulation

引用

Proceedings of the 2007 IEEE/ACM international conference on computer-aided design

作者： Derek Chiou Dam Sunwoo Joonsoo Kim Nikhil Patil William H. Reinhart D. Eric Johnson Zheng Xu The University of Texas at Austin The University of Texas at Austin and Freescale Semiconductor Inc.

ISBN: (纸本)9781424413829

This paper describes the FAST methodology that enables a single FPGA to accelerate the performance of cycle-accurate computer system simulators modeling modern, realistic SoCs, embedded systems and standard desktop/laptop/server computer systems. The methodology partitions a simulator into (i) a functional model that simulates the functionality of the computer system and (ii) a predictive model that predicts performance and other metrics. The partitioning is crafted to map most of the parallel work onto a hardware-based predictive model, eliminating much of the complexity and difficulty of simulating parallel constructs on a sequential *** conventions and libraries have been designed to make creating, modifying, using and measuring such simulators straightforward. We describe a prototype FAST system: a full-system, RTL-level cycle-accurate-capable computer system simulator that executes the x86 ISA, boots unmodified Linux and executes unmodified x86 applications. The prototype runs two to three orders of magnitude faster than the fastest Intel and AMD RTL-level cycle-accurate x86 software-based simulators and about six to seven times faster than RTL simulation.

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SiXton's curse — Simulator X demonstration

SiXton's curse — Simulator X demonstration

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IEEE Annual international Symposium Virtual Reality

作者： Martin Fischbach Dennis Wiebusch Anke Giebler-Schubert Marc Erich Latoschik Stephan Rehfeld Henrik Tramberend Intelligent Graphics Group University of Bayreuth Germany Beuth University of Applied Sciences Berlin Germany

We present SiXton 's Curse-a computer game-to illustrate the ben efits of a novel simulation platform. Simulator X [2] targets vir tual, augmented, and mixed reality applications as well as computer games. The game simulates a medieval village called SiXton that can be explored and experienced using gestures and speech for in put. SiXton's Curse utilizes multiple independent components for physical simulation, sound and graphics rendering, artificial intelli gence, as well as for multi-modal interaction (MMI). The compo nents are already an integral part of Simulator X's current version. Building on Hewitt's actor model, the Simulator X platform enables the developer to easily exploit the capabilities of modern hardware architectures. A state variable concept is implemented on top of the actor model to grant uniform and easy access to global states and values by using the internal mechanisms of the actor model. Communication via an asynchronous messaging in terface reduces component coupling. The scalability of the actor model provides a uniform concurrency paradigm on different levels of granularity as well as exchangeability of architectural elements and components.

关键词： Bridges Solid modeling computers Artificial intelligence Rendering (computer graphics) Interactive systems

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MTJ-PUF with Input Decoder and Evaluation of Machine Learning Resistance

MTJ-PUF with Input Decoder and Evaluation of Machine Learnin...

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international Technical conference o Circuits/systems, computers and Communications (ITC-CSCC)

作者： Takumi Kikuchi Kimiyoshi Usami Graduate School of Engineering and Science Shibaura Institute of Technology Tokyo Japan Department of Computer Science and Engineering Shibaura Institute of Technology Tokyo Japan

ISBN: (数字)9798350379051

ISBN: (纸本)9798350379068

LSIs are embedded in a wide range of products and have become an indispensable part of our lives. As a result, security has become more important than ever. Physically Unclonable Functions (PUFs), one of the LSI individual authentication techniques, have attracted attention in recent years. This is because they have potential to provide strong security by generating unique identifiers based on entropy produced during manufacturing. However, PUFs are vulnerable to machine learning (ML) modeling attacks. In this paper, we propose an approach to add an input-decoder to the Magnetic Tunnel Junction (MTJ) based latch PUF circuit to improve resistance against modeling attacks. We evaluated the vulnerability of the proposed MTJ-PUF to modeling attacks using the support vector machine (SVM), linear regression (LR), and multilayer perceptron (MLP). Results demonstrated that the prediction accuracy of each modeling attack is close to the ideal value of 50%, whereas the prediction accuracy of the conventional MTJ-PUF reaches 100% with the same number of training data. This indicates that the proposed input-decoder MTJ-PUF is resistant to ML attacks. Evaluation through simulation demonstrated that the proposed PUF achieved a uniqueness of 50%, uniformity of 49.9%, and reliability of 100%.

关键词： Resistance Support vector machines Accuracy Logic circuits Machine learning Decoding Security

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GCMR: A GPU Cluster-Based MapReduce Framework for Large-Scale Data Processing

GCMR: A GPU Cluster-Based MapReduce Framework for Large-Scal...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Yiru Guo Weiguo Liu Bin Gong Gerrit Voss Wolfgang Muller-Wittig Sch. of Comput. Sci. & Technol. Shandong Univ. Jinan China Fraunhofer IDM@NTU Nanyang Technol. Univ. Singapore Singapore

MapReduce is a very popular programming model to support parallel and distributed large-scale data processing. There have been a lot of efforts to implement this model on commodity GPU-based systems. However, most of these implementations can only work on a single GPU. And they can not be used to process large-scale datasets. In this paper, we present a new approach to design the MapReduce framework on GPU clusters for handling large-scale data processing. We have used Compute Unified Device architectures (CUDA) and MPI parallel programming models to implement this framework. To derive an efficient mapping onto GPU clusters, we introduce a two-level parallelization approach: the inter node level and intra node level parallelization. Furthermore in order to improve the overall MapReduce efficiency, a multi-threading scheme is used to overlap the communication and computation on a multi-GPU node. Compared to previous GPU-based MapReduce implementations, our implementation, called GCMR, achieves speedups up to 2.6 on a single node and up to 9.1 on 4 nodes of a Tesla S1060 quad-GPU cluster system for processing small datasets. It also shows very good scalability for processing large-scale datasets on the cluster system.

关键词： Graphics processing units Instruction sets Computational modeling computer architecture Acceleration Writing Data processing

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GPGPU accelerated real-time potential field based formation control for Unmanned Aerial Vehicles

GPGPU accelerated real-time potential field based formation ...

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international conference on Unmanned Aircraft systems (ICUAS)

作者： Omer Cetin Guray Yilmaz Turkish Air Force Academy Aeronautics and Space Technologies Institute Turkey Turkish Air Force Academy Computer Engineering Department Turkey

One of the research topics for the autonomous UAVs is formation flight control that provides two or more aircraft flies together under a discipline. For aerial vehicles the advantages of performing formation flight include fuel saving, improved efficiency in air traffic control and cooperative task allocation. Besides the benefits of the autonomous formation flight it has some difficulties like providing collision avoidance in narrow flight zone. Furthermore an autonomous formation flight must provide dynamic routines like getting formation position or changing formation schemes. Potential field based autonomous control is one of the commonly used control techniques providing dynamic and precise control. The bottleneck for the potential field based control is computation power needs especially for global path planning for dynamic, high resolution and large sized fields. GPGPU is one of the parallel computing architectures that provide programming massively parallel SIMD applications on GPUs. In this work GPGPU accelerated real-time potential field based formation control approach is designed and examined under simulation environment for UAVs. In order to reveal the precise and dynamic control features high-resolution potential field based global path planning models have been developed in real-time successfully.

关键词： Mathematical model Computational modeling Vectors Equations Real-time systems Aerodynamics Vehicle dynamics

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