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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

共 2686 条记录，以下是2611-2620 订阅

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Trace-driven simulation of decoupled architectures

Trace-driven simulation of decoupled architectures

引用

Annual Hawaii international conference on System Sciences (HICSS)

作者： S. Manoharan N.P. Topham A.W.R. Crawford Advanced Computer Research Institute Lyon France Department Of Computer Science University of Edinburgh Edinburgh UK

The development of accurate trace-driven simulation models has become a key activity in the design of new high-performance computer systems. Trace-driven simulation is fast, enabling analysis of the behaviour of large application and benchmark programs on a new computer system. We describe a trace-driven simulation engine for a decoupled processor architecture. We report on two ways of generating efficient execution traces of real programs for this engine: profiler-assisted and compiler-assisted, and also on the use of synthetic traces. Results are reported for execution on the simulation engine of traces from Linpack and one of the Perfect Club benchmarks, as well as synthesized traces.< >

关键词： Computational modeling Analytical models Engines Gold computer architecture computer simulation Application software Program processors Benchmark testing Process design

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Practical techniques for distributed real-time simulation

Practical techniques for distributed real-time simulation

引用

IEEE National conference on Aerospace and Electronics (NAECON)

作者： S.A. Walters Science Applications International Corporation USA

Real-time aircraft and avionics simulation computing is the foundation of systems used for testing embedded avionics software, for flight training simulation, and for engineering research simulation. Distribution of the simulation software over a set of smaller, inexpensive computers, in lieu of a traditional mainframe has been shown to dramatically reduce the cost of building a real-time simulation architecture. A true distributed architecture is also more cost effective than the latest generation of multiprocessor mainframes. The Advanced Multi-Purpose Support Environment (AMPSE), developed by the Avionics Logistics Branch of the Wright Laboratory (WL/AAAF) on the embedded computer Resources Support Improvement Program (ESIP), is an architecture and design methodology for distributed real-time simulation. It is a generic architecture that emphasizes modularity, reconfigurability, expandability, and software reuse. Other recent attempts at distributed real-time simulation systems have encountered significant performance difficulties due to inefficiencies in the approaches used for inter-processor communications and for scheduling and coordination of the distributed software execution. The systems engineering effort by WL/AAAF during AMPSE development focused on a careful design of these mechanisms. The resulting system achieves outstanding real-time performance through very efficient software scheduling and inter-processor communications while retaining a very modular, flexible, and reusable architectural approach.< >

关键词： Computational modeling Aerospace electronics computer architecture Real time systems Aerospace simulation computer simulation embedded computing Distributed computing Costs Communication system software

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Conservative and optimistic distributed simulation in massively parallel computers: a comparative study

Conservative and optimistic distributed simulation in massiv...

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international conference on Massively Parallel Computing systems

作者： J.M. Alonso A.A. Frutos R.B. Palacio DepartmentArquitectura y Tecnología de Computadores UPV/EHU San Sebastian Spain Department Electrónica University de Castilla-La Mancha Santander Spain

The main algorithms for sequential and parallel discrete event simulations are introduced. A set of different simulators is evaluated and compared using a transputer-based multicomputer: sequential, parallel conservative and parallel optimistic. For the proposed model, the conservative simulator shows better speedups. The obtained results show that a significant improvement on execution time can be obtained using parallel systems, but only if the model under simulation have some properties like coarse grain size and high degree of self-synchronisation.< >

关键词： Computational modeling computer simulation Concurrent computing Distributed computing Discrete event simulation Clocks Grain size Parallel architectures Optimization methods Synchronization

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Fuzzy controller design to drive an induction motor

Fuzzy controller design to drive an induction motor

引用

IEEE international conference on Fuzzy systems (FUZZ-IEEE)

作者： G. D'Angelo M. Lo Presti G. Rizzotto Universita degli Studi di Catania Catania Sicilia IT Fuzzy Logic Res. Group Catania Univ. Italy S.G.S. Thomson Microelectronics Corporate Advanced System Architectures Agrate-Brianza Italy

This paper describes the simulation results of an induction motor speed control based on fuzzy logic theory. Voltage impress control technique has been applied to medium power induction motor. An automatic approach to extract control rules allows us to reduce the design time. computer simulations have been carried out in order to test the performances of the whole control system. Then a hardware implementation of the fuzzy controller is proposed by means of a dedicated fuzzy processor: WARP (weight associative rule processor).< >

关键词： Fuzzy control Induction motors Automatic control Computational modeling Velocity control Fuzzy logic Voltage control computer simulation System testing Performance evaluation

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A simulation study of hardware-oriented DSM approaches

A simulation study of hardware-oriented DSM approaches

引用

IEEE Region 10 international conference TENCON

作者： A. Grujic M. Tomasevic V. Milutinovic Department of Computer Engineering School of Electrical Engineering University of Belgrade Belgrade Serbia Department of Computer Engineering Institute Mihajlo Pupin University of Belgrade Belgrade Serbia

Representative hardware implementations of the distributed shared memory (DSM) concept are comparatively evaluated in this study-two NUMA (Dash and SCI) and two COMA (KSR1 and DDM) architectures. Analysis was oriented towards the comparison of approaches, rather than their implementations. For that purpose, a hierarchical two-level cluster-based system with a uniform bus-based cluster structure on the first level is assumed. The DSM mechanisms of four approaches were simulated on the second level. A simulation methodology based on synthetic address traces was applied. The comparison was carried out for a large variety and a broad range of system-oriented, application-oriented and technology-oriented parameters. The results have shown the somewhat better efficiency of COMA protocols (because of the dynamic migration of responsibility for shared data) and the large impact of the available interconnection network bandwidth on system scalability (an almost linear speedup is achieved with ring-based systems).< >

关键词： Hardware Distributed computing computer architecture Scalability Concurrent computing Delay Computational modeling Bandwidth Message passing Power system modeling

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A high speed parallel architecture for fuzzy inference and fuzzy control of multiple processes

A high speed parallel architecture for fuzzy inference and f...

引用

IEEE international conference on Fuzzy systems (FUZZ-IEEE)

作者： A. Jaramillo-Botero Y. Miyake Faculty of Engmeering Pontificia Universidad Javeriana Cali Colombia Faculty of Engineering Chiba University Chiba Japan

A hardware processing architecture and an associated graphical compiler for fuzzy inference and control of multiple antecedents and output variables is presented. The hardware architecture, running as a fuzzy co-processor for IBM PC (or compatible) platforms, uses as core elements the FP9000 rules chips and FP9001 defuzzifier chips. The claimed response for these processors is in the order of 0.714 /spl mu/s per fuzzy inference without defuzzification, and 1.6 /spl mu/s per fuzzy inference including center of gravity defuzzification. The architecture proposed permits fuzzy inference simulation under PC master control, as well as direct fuzzy control of output processes. The system relies on the partial flexibility of the fuzzy chips (fuzzy rule parameters are programmable through a digital interface), their embedded parallel processing, and the analog processing speeds, in order to achieve high speed simulation and real-time control response. An object oriented graphical compiler designed to permit intuitive definitions and tuning of linguistic labels within membership functions, as well as plant control systems modeling, is currently under development. The compiler interacts directly with the PCs i80X86 and the fuzzy parallel engine (in a master-slave configuration), and generates, at users request, intermediate flat ANSI C type code for portability.< >

关键词： Parallel architectures Fuzzy control Hardware Object oriented modeling Fuzzy systems Coprocessors Gravity Parallel processing Real time systems Control system synthesis

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Performance evaluation of a software architecture for real-time call processing

Performance evaluation of a software architecture for real-t...

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international conference on Communication systems

作者： Ting-Chao Hou Department ofElectrical Engineering National Chung Cheng University Taiwan

ISBN: (纸本)0780320468

computers running under the UNIX operating system are used as adjunct processors to a switch to share call-processing responsibilities. In this architecture, call-processing tasks inside the adjunct processors are embedded in UNIX user processes. The author built a discrete-event driven, C-based, UNIX simulation model at a level of detail that allows one to obtain the statistics of many system task overheads. The model can give an accurate estimate of the system capacity by providing the breakdown of CPU time spent in context switches, I/O, IPC system calls, and user processes. In addition, the author found that the system can be trapped in a deadlock or "livelock" situation if not properly controlled. Causes and solutions to the deadlock/livelock condition were investigated.< >

关键词： Software architecture Switches System recovery Operating systems computer architecture Computational modeling Statistics Context modeling Electric breakdown Central Processing Unit

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Performance estimation of multistreamed, superscalar processors

Performance estimation of multistreamed, superscalar process...

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Annual Hawaii international conference on System Sciences (HICSS)

作者： W. Yamamoto M.J. Serrano A.R. Talcott R.C. Wood M. Nemirosky Department of Electrical and Computer Engineering University of California Santa Barbara CA USA University of California Santa Barbara Santa Barbara CA US Dept. of Electr. & Comput. Eng. California Univ. Santa Barbara CA USA

Multistreamed processors can significantly improve processor throughput by allowing interleaved execution of instructions from multiple instruction streams. We present an analytical modeling technique to evaluate the effect of dynamically interleaving additional instruction streams within superscalar architectures. Using this technique, estimates of the instructions executed per cycle (IPC) for a processor architecture are quickly calculated given simple descriptions of the workload and hardware characteristics. To validate this technique, estimates of the SPEC89 benchmark suite obtained from the model are compared to results from a hardware simulator. Our results show that the technique produces accurate estimates with an average deviation of /spl sim/4% from the simulation results. Finally, we demonstrate that as the number of functional units increases, multistreaming is an effective technique to exploit these additional resources.< >

关键词： Hardware Analytical models Parallel processing Throughput Processor scheduling Interleaved codes computer architecture Dispatching Control systems System performance

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Automated validation of operational flight programs (OFPs) and flight training simulators

Automated validation of operational flight programs (OFPs) a...

引用

IEEE National conference on Aerospace and Electronics (NAECON)

作者： J. Van Fleet S. Flannery J. Rura Science Applications International Corporation USA

Operational flight programs (OFPs) that run in the embedded computer systems (ECSs) in modern aircraft must undergo extensive and rigorous validation testing before they are released for flight. Similar validation testing is required for the highest fidelity flight training simulators to assure that they accurately represent the behavior of the actual aircraft. This validation process, today, is largely manual. Test engineers develop and execute the test procedures by hand an the avionics test station or flight simulator. Manual testing is very time intensive, prone to errors, difficult to repeat precisely, and requires highly qualified experts. The automated validation (AutoVal) tool suite, developed by the Avionics Logistics Branch at Wright Laboratory (WL/AAAF), offers an alternative approach to testing that addresses these problems. AutoVal performs real-time testing of OFP and flight simulator software by completely automating the actions of the test engineers. It utilizes a testing-oriented command language that features user-definable macros for tailoring commands to specific applications. AutoVal reads and interprets commands stored in files or entered interactively through a command-line interface. Test engineers can generate reusable command files that configure and initialize the simulation, control the simulation flight dynamics and avionics modes, verify test results, and automatically create test logs. The most recent AutoVal research has focused on two areas: citation of an AutoVal translator that will produce MIL-STD-1815A Ada source code; and development of a learning capability that will record a test engineers actions and generate AutoVal command files.< >

关键词： Automatic testing Aerospace simulation Aerospace electronics Aerospace engineering Aircraft propulsion Software testing embedded computing System testing Computational modeling Logistics

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Proceedings of the 1993 IEEE international conference on computer Design: VLSI in computers & Processors

Proceedings of the 1993 IEEE International Conference on Com...

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Proceedings of the 1993 IEEE international conference on computer Design: VLSI in computers & Processors

ISBN: (纸本)0818642300

The conference materials contain 113 papers. The topics covered include PC architectures;embedded systems;global optimization in high-level synthesis;cache architectures;embedded systems performance analysis;design verification and modification;timing analysis and optimization;high performance general purpose machines;scan design;asynchronous design;multipliers/dividers;programmable gate array architectures;formal methods;microprocessor design;computer arithmetic;VLSI systems;binary decision diagrams;test generation and evaluation;memory systems;scheduling techniques in high-level synthesis;fine-grain parallelism;combinational logic optimization;CAD layout;field programmable gate arrays;logic synthesis;design for testability;fault simulation;fault tolerance and reliability;and signal processing.

关键词： Microprocessor chips

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