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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

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Proceedings of the 1993 IEEE international conference on computer Design: VLSI in computers & Processors

Proceedings of the 1993 IEEE International Conference on Com...

引用

Proceedings of the 1993 IEEE international conference on computer Design: VLSI in computers & Processors

ISBN: (纸本)0818642300

The conference materials contain 113 papers. The topics covered include PC architectures;embedded systems;global optimization in high-level synthesis;cache architectures;embedded systems performance analysis;design verification and modification;timing analysis and optimization;high performance general purpose machines;scan design;asynchronous design;multipliers/dividers;programmable gate array architectures;formal methods;microprocessor design;computer arithmetic;VLSI systems;binary decision diagrams;test generation and evaluation;memory systems;scheduling techniques in high-level synthesis;fine-grain parallelism;combinational logic optimization;CAD layout;field programmable gate arrays;logic synthesis;design for testability;fault simulation;fault tolerance and reliability;and signal processing.

关键词： Microprocessor chips

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ROLES OF RECURRENCE IN NEURAL CONTROL architectures 4

ROLES OF RECURRENCE IN NEURAL CONTROL ARCHITECTURES

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4th international conference on Applications of Artificial Neural Networks

作者： PUSKORIUS, GV FELDKAMP, LA FORD MOTOR CO RES LABDEARBORNMI 48124

ISBN: (纸本)0819412015

In this paper we discuss the means by which recurrent connections are used in neural control system architectures. We first consider the state feedback approach to control and the role of recurrent neural networks for plant modeling and control. In this context, we provide an explicit formulation for the computation of dynamic derivatives in recurrent neural network architectures as required for training by the dynamic gradient method. For illustration, we apply dynamic gradient methods to train recurrent neural network controllers for a series of cart-pole problems with the simultaneous objectives of pole balancing and cart centering.

关键词： Neural networks Network architectures Control systems computer architecture Artificial neural networks Feedback control Dynamical systems Nonlinear control Device simulation Complex systems

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16th IFIP Working Group 7.3 international Symposium on computer Performance modeling, Measurement and Evaluation and ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1993

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16th IFIP Working Group 7.3 international Symposium on computer Performance modeling, Measurement and Evaluation and ACM SIGMETRICS conference on Measurement and modeling of computer systems, 1993

ISBN: (纸本)9783540572978

The proceedings contain 26 papers. The special focus in this conference is on computer Performance modeling, Measurement and Evaluation. The topics include: Parallel simulation;properties and analysis of queueing network models with finite capacities;performance analysis and optimization with the power-series algorithm;multiprocessor and distributed system design;response time distributions in queueing network models;fast simulation of rare events in queueing and reliability models;an inlxoduction to modeling dynamic behavior with time series analysis;issues in trace-driven simulation;maximum entropy analysis of queueing network models;performance modeling using DSPN express;relaxation for massively parallel discrete event simulation;an overview of tes processes and modeling methodology;performance engineering of client-server systems;queueing networks with finite capacities;performance instrumentation techniques for parallel systems;a survey of bottleneck analysis in closed networks of queues;software performance engineering;performance measurement using system monitors;providing quality of service packet switched networks;dependability and performability analysis;architectures and algorithms for digital multimedia on-demand servers;analysis and control of polling systems;modeling and analysis of transaction processing systems.

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On net modeling of industrial size concurrent systems 14th

引用

14th international conference on Application and Theory of Petri Nets, 1993

作者： Cherkasova, Ludmila Kotov, Vadim Rokicki, Tomas Hewlett-Packard Laboratories 1501 Page Mill Road Palo AltoCA94303 United States Computer Science Department Stanford University StanfordCA94305 United States

ISBN: (纸本)9783540568636

The paper discusses the modeling of OLTP (Ou-Line Transaction Processing) using colored Petri nets and the Design/CPN tool. We have performed industrial-sized simulation of tens of thousands of transactions running on databases with millions of records. OLTP applications were chosen because the OLTP workloads emphasize update-intensive database services with up to thousands of concurrent transactions per second. The goal of the experiment was to develop a methodology for the net modeling of OLTP-like applications with respect to the ability of different, computer systems to meet the OLTP benchmarks requirements. The effort spent on the successful modeling of such large systems resulted in some methodological conclusions which required us to avoid straightforward approaches to the net modeling and to develop a combined technique of using nets together with embedded programming for simulation and analytical modeling. © Springer-Verlag Berlin Heidelberg 1993.

关键词： Petri nets

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Proceedings of the 1993 IEEE/ACM international conference on computer-Aided Design

Proceedings of the 1993 IEEE/ACM International Conference on...

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Proceedings of the 1993 IEEE/ACM international conference on computer-Aided Design

ISBN: (纸本)0818644923

The conference materials contain 129 papers. The topics covered include sequential fault simulation;testability and reliability in high-level synthesis;binary decision diagrams;interconnect analysis and modeling;new developments in IC testing;layout and database aspects in high-level synthesis;synthesis for lookup-based field-programmable gate arrays;efficient simulation techniques;issues in system-level timing;placement algorithms;statistical design and yield analysis;technology mapping for delay and power optimization;layout issues for multichip modules and field-programmable gate arrays;asynchronous circuit synthesis and verification;numerical device simulation;retiming;CAD issues in system design;analog modeling and test;partitioning and floorplanning;sequential logic optimization;Boolean algebraic test generation;scheduling;technology mapping;routing for FPGAs and FPICs;verification and diagnostics;application specific data path synthesis;combinatorial verification;zero-skew clock routing with delay optimization;built-in self-testing;embedded processor design;high performance interconnects;design for testability and diagnosis;buffer and memory sizing;crosstalk reduction;novel design for test techniques;modeling for high-level synthesis;discrete simulation, and topics in physical design.

关键词： Logic design

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Genie: An environment for partitioning and mapping in embedded multiprocessors

Genie: An environment for partitioning and mapping in embedd...

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international Symposium on Parallel and Distributed Processing (IPDPS)

作者： S. Yalamanchili L. Te Winkel D. Perschbacher B. Shenoy Computer Systems Research Laboratory School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA Alliant Tech Systems Inc. Hopkins MN USA

embedded multiprocessor architectures present different constraints, and therefore challenges to the problems of partitioning and mapping parallel programs. They must typically optimize throughput and/or latency while satisfying placement, memory, and processor throughput constraints. This paper describes the algorithms, organization, and application of Genie - a set of tools for the partitioning and mapping of parallel programs for embedded multiprocessor architectures under such constraints. At one end Genie is tightly coupled into a commercial software development environment - Teamwork SA/RT. At the other it presents an interface to simulation and modeling tools. A example is presented of the application of this environment to an existing real-time embedded application - autonomous underwater vehicle (AUV).< >

关键词： computer architecture Application software embedded computing Partitioning algorithms Throughput Software tools Teamwork Programming Production Circuit simulation

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Independent performance modeling of parallel architectures and algorithms

Independent performance modeling of parallel architectures a...

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international conference on Computing and Information (ICCI)

作者： E.E. Johnson Parallel Architecture Research Laboratories New Mexico State University USA

A key requirement for the effective use of multiprocessor systems in real-world applications is an ability to accurately predict the performance of a specific algorithm on a specific architecture. Such performance prediction tools assist the system designer in initially selecting, and then modifying, both the algorithm and the architecture to obtain acceptable performance. In this paper, we present a modeling approach that permits separate evaluation of algorithm and architecture performance with only a small number of "cross" parameters required to link the two models. An example application of this technique to a Gaussian elimination algorithm on two dissimilar multiprocessor architectures shows good agreement with actual performance figures obtained from measurement and simulation.< >

关键词： Parallel architectures computer architecture Computational modeling Parallel processing System performance Predictive models Multiprocessing systems Algorithm design and analysis Throughput Concurrent computing

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Quantitative comparison of architectures for digital neuro-computers

Quantitative comparison of architectures for digital neuro-c...

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international Joint conference on Neural Networks (IJCNN)

作者： P. Ienne LAMI & MANTRA Swiss Federal Institute of Technology Lausanne Switzerland

As the field of neural networks matures toward real-world applications, a strong need for hardware systems to efficiently compute larger networks arises. Comparisons between neural network-dedicated platforms are often fragmentary or qualitative. An architectural-level evaluation scheme is attempted by proposing some performance indices on idealized architecture classes. Some conclusions on the advantages and limitations of the architectures are drawn.

关键词： computer architecture Throughput computer networks Broadcasting Systolic arrays Neural network hardware Performance analysis Neural networks Computational modeling computer simulation

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Fast timing analysis for hardware-software co-synthesis

Fast timing analysis for hardware-software co-synthesis

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IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： W. Ye R. Ernst T. Benner J. Henkel Institut für Datenverarbeitungsanlagen Technische Universiät Braunschweig Brunswick Germany

At the current time, an iterative approach seems to be best suited for hardware/software partitioning in hardware/software co-synthesis with time constraints. To check the timing constraints, the iteration loop contains a timing analysis. Only computation time-intensive RT-level simulation provides sufficient timing precision for complex processor architectures. We present a hardware/software timing analysis, which comes close to the precision of an RT-level simulation in a fraction of the computation time and, thus, removes a bottleneck from iterative hardware/software co-synthesis. We present some results for our co-synthesis system COSYMA.< >

关键词： Timing Hardware Time factors Cost function Constraint optimization Computational modeling computer architecture embedded system Reduced instruction set computing Coprocessors

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Modelling of a self timed dataflow processor in VHDL

Modelling of a self timed dataflow processor in VHDL

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Annual IEEE international conference and Exhibit ASIC

作者： Shih-ien Lu Chih-Ming Chang Department of Electrical and Computer Engineering Oregon State University Corvallis OR USA

Using a signal transition approach to design computation systems has many advantages. The authors illustrate the design of a dataflow processor using the signal transition framework proposed by I.E. Sutherland (1989). Dataflow computers differ from most other parallel architectures. They are based on the concept of data-driven computation instead of the program store computation model. Since the data-driven computation model provides the execution of instructions asynchronously, it is natural to implement a dataflow processor using self-timed circuits. The authors present the design of a static dataflow processor implemented using self-timed circuits. They use VHDL to model part of the design to aid the simulation and verification process.< >

关键词： Computational modeling computer aided instruction Concurrent computing Timing computer architecture Arithmetic Signal design Circuit simulation computer simulation Digital systems

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