In this paper we discuss the means by which recurrent connections are used in neural control system architectures. We first consider the state feedback approach to control and the role of recurrent neural networks for...
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ISBN:
(纸本)0819412015
In this paper we discuss the means by which recurrent connections are used in neural control system architectures. We first consider the state feedback approach to control and the role of recurrent neural networks for plant modeling and control. In this context, we provide an explicit formulation for the computation of dynamic derivatives in recurrent neural network architectures as required for training by the dynamic gradient method. For illustration, we apply dynamic gradient methods to train recurrent neural network controllers for a series of cart-pole problems with the simultaneous objectives of pole balancing and cart centering.
The proceedings contain 26 papers. The special focus in this conference is on computer Performance modeling, Measurement and Evaluation. The topics include: Parallel simulation;properties and analysis of queueing netw...
ISBN:
(纸本)9783540572978
The proceedings contain 26 papers. The special focus in this conference is on computer Performance modeling, Measurement and Evaluation. The topics include: Parallel simulation;properties and analysis of queueing network models with finite capacities;performance analysis and optimization with the power-series algorithm;multiprocessor and distributed system design;response time distributions in queueing network models;fast simulation of rare events in queueing and reliability models;an inlxoduction to modeling dynamic behavior with time series analysis;issues in trace-driven simulation;maximum entropy analysis of queueing network models;performance modeling using DSPN express;relaxation for massively parallel discrete event simulation;an overview of tes processes and modeling methodology;performance engineering of client-server systems;queueing networks with finite capacities;performance instrumentation techniques for parallel systems;a survey of bottleneck analysis in closed networks of queues;software performance engineering;performance measurement using system monitors;providing quality of service packet switched networks;dependability and performability analysis;architectures and algorithms for digital multimedia on-demand servers;analysis and control of polling systems;modeling and analysis of transaction processing systems.
The paper discusses the modeling of OLTP (Ou-Line Transaction Processing) using colored Petri nets and the Design/CPN tool. We have performed industrial-sized simulation of tens of thousands of transactions running on...
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The conference materials contain 129 papers. The topics covered include sequential fault simulation;testability and reliability in high-level synthesis;binary decision diagrams;interconnect analysis and modeling;new d...
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ISBN:
(纸本)0818644923
The conference materials contain 129 papers. The topics covered include sequential fault simulation;testability and reliability in high-level synthesis;binary decision diagrams;interconnect analysis and modeling;new developments in IC testing;layout and database aspects in high-level synthesis;synthesis for lookup-based field-programmable gate arrays;efficient simulation techniques;issues in system-level timing;placement algorithms;statistical design and yield analysis;technology mapping for delay and power optimization;layout issues for multichip modules and field-programmable gate arrays;asynchronous circuit synthesis and verification;numerical device simulation;retiming;CAD issues in system design;analog modeling and test;partitioning and floorplanning;sequential logic optimization;Boolean algebraic test generation;scheduling;technology mapping;routing for FPGAs and FPICs;verification and diagnostics;application specific data path synthesis;combinatorial verification;zero-skew clock routing with delay optimization;built-in self-testing;embedded processor design;high performance interconnects;design for testability and diagnosis;buffer and memory sizing;crosstalk reduction;novel design for test techniques;modeling for high-level synthesis;discrete simulation, and topics in physical design.
embedded multiprocessor architectures present different constraints, and therefore challenges to the problems of partitioning and mapping parallel programs. They must typically optimize throughput and/or latency while...
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embedded multiprocessor architectures present different constraints, and therefore challenges to the problems of partitioning and mapping parallel programs. They must typically optimize throughput and/or latency while satisfying placement, memory, and processor throughput constraints. This paper describes the algorithms, organization, and application of Genie - a set of tools for the partitioning and mapping of parallel programs for embedded multiprocessor architectures under such constraints. At one end Genie is tightly coupled into a commercial software development environment - Teamwork SA/RT. At the other it presents an interface to simulation and modeling tools. A example is presented of the application of this environment to an existing real-time embedded application - autonomous underwater vehicle (AUV).< >
A key requirement for the effective use of multiprocessor systems in real-world applications is an ability to accurately predict the performance of a specific algorithm on a specific architecture. Such performance pre...
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A key requirement for the effective use of multiprocessor systems in real-world applications is an ability to accurately predict the performance of a specific algorithm on a specific architecture. Such performance prediction tools assist the system designer in initially selecting, and then modifying, both the algorithm and the architecture to obtain acceptable performance. In this paper, we present a modeling approach that permits separate evaluation of algorithm and architecture performance with only a small number of "cross" parameters required to link the two models. An example application of this technique to a Gaussian elimination algorithm on two dissimilar multiprocessor architectures shows good agreement with actual performance figures obtained from measurement and simulation.< >
作者:
P. IenneLAMI & MANTRA
Swiss Federal Institute of Technology Lausanne Switzerland
As the field of neural networks matures toward real-world applications, a strong need for hardware systems to efficiently compute larger networks arises. Comparisons between neural network-dedicated platforms are ofte...
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As the field of neural networks matures toward real-world applications, a strong need for hardware systems to efficiently compute larger networks arises. Comparisons between neural network-dedicated platforms are often fragmentary or qualitative. An architectural-level evaluation scheme is attempted by proposing some performance indices on idealized architecture classes. Some conclusions on the advantages and limitations of the architectures are drawn.
At the current time, an iterative approach seems to be best suited for hardware/software partitioning in hardware/software co-synthesis with time constraints. To check the timing constraints, the iteration loop contai...
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At the current time, an iterative approach seems to be best suited for hardware/software partitioning in hardware/software co-synthesis with time constraints. To check the timing constraints, the iteration loop contains a timing analysis. Only computation time-intensive RT-level simulation provides sufficient timing precision for complex processor architectures. We present a hardware/software timing analysis, which comes close to the precision of an RT-level simulation in a fraction of the computation time and, thus, removes a bottleneck from iterative hardware/software co-synthesis. We present some results for our co-synthesis system COSYMA.< >
Using a signal transition approach to design computation systems has many advantages. The authors illustrate the design of a dataflow processor using the signal transition framework proposed by I.E. Sutherland (1989)....
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Using a signal transition approach to design computation systems has many advantages. The authors illustrate the design of a dataflow processor using the signal transition framework proposed by I.E. Sutherland (1989). Dataflow computers differ from most other parallel architectures. They are based on the concept of data-driven computation instead of the program store computation model. Since the data-driven computation model provides the execution of instructions asynchronously, it is natural to implement a dataflow processor using self-timed circuits. The authors present the design of a static dataflow processor implemented using self-timed circuits. They use VHDL to model part of the design to aid the simulation and verification process.< >
Existing approaches to integrating neural and symbolic processing are divided into the following four categories: developing specialized, structured, localist networks for symbolic processing; performing symbolic proc...
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Existing approaches to integrating neural and symbolic processing are divided into the following four categories: developing specialized, structured, localist networks for symbolic processing; performing symbolic processing in distributed neural networks (in a holistic way); combining separate symbolic and neural network modules; and using neural networks as basic elements in symbolic architectures (the embedded approach). Research issues that need to be addressed in order to advance this field as well as to better understand the nature of intelligence and cognition are outlined.< >
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