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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

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The effects of memory latency and fine-grain parallelism on Astronautics ZS-1 performance

The effects of memory latency and fine-grain parallelism on ...

引用

Annual Hawaii international conference on System Sciences (HICSS)

作者： W. Mangione-Smith S.G. Abraham E.S. Davidson Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

The performance of the Astronautics ZS-1, a decoupled access/execute (DAE) processor, is examined. The CPU is composed of two subsystems: an access processor, which handles address generation and fixed-point operations; and an execute processor, which handles floating-point operations. These two systems communicate through a network of queues and operate in a fairly decoupled manner. This architecture exhibits a form of fine-grain parallelism, called slip, that improves performance. Some performance bounds for the ZS-1 are developed. A simple count of resource usage is sufficient to establish a good upper bound on performance for most vector loops. A dependence graph is used to form another bound that is particularly useful for nonvector loops. This two-bound model accounts for compiler characteristics, such as loop unrolling, and for hardware characteristics, such as memory latency. This model is applied to the first 12 Livermore loops and compared to simulation results for a variety of memory systems. This comparison indicates how well the ZS-1 tolerates increased memory latency as a function of slip and provides insights regarding application codes, architectures, and compiler capabilities.< >

关键词： Delay Parallel processing Central Processing Unit Hardware computer architecture Concurrent computing Application software Iterative algorithms Upper bound Computational modeling

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Study of computer architecture topology simulation using Network II.5, Simscript II.5, and ModSim II

Study of computer architecture topology simulation using Net...

引用

1989 IEEE international conference on systems, Man, and Cybernetics

作者： Munoz, Jose L. Krzych, Matthew J. Cent US Naval Underwater Syst New London CT USA

A reference guide is provided for the tool selection process, particularly when applied to computer architecture simulation. Network II.5, Simscript II.5, and ModSim II each provide the capability for assessing computer architectures although the underlying methodology behind each tool varies. Network II.5 is specifically designed for computer network simulation while Simscript II.5 and ModSim II are general-purpose simulation languages, with ModSim II supporting object-oriented programming. As a result, each has its own unique set of strengths and limitations that directly influence each model's ability to support modeling goals. The selection of a tool for a particular modeling effort is highly dependent upon these goals.

关键词： computer architecture

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A study of computer architecture topology simulation using Network II.5, Simscript II.5, and ModSim II

A study of computer architecture topology simulation using N...

引用

IEEE international conference on systems, Man and Cybernetics

作者： J.L. Munoz M.J. Krzych Naval Underwater and Systems Center New London CT USA

关键词： computer architecture Network topology Computational modeling computer simulation Object oriented modeling Proposals Prototypes Binary trees computer networks Real time systems

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CSP-based object-oriented description of parallel reconfiguration architectures

CSP-based object-oriented description of parallel reconfigur...

引用

international conference on Wafer Scale Integration

作者： D.K. Hwang W.K. Fuchs Computer Systems Group Coordinated Science Laboratory University of Illinois Urbana IL USA

An approach to object-oriented description of reconfigurable parallel architectures based on an extended communicating sequential processes (CSP) model of communication is presented. A workbench called OODRA (object-oriented design of reconfigurable architectures), has been designed and implemented, based on this approach which is suitable for the development of highly concurrent, special-purpose, reconfigurable architectures. Intended uses of OODRA include parallel algorithm/architecture functional simulation and reconfiguration algorithm simulation, with an interactive graphical interface for parallel architecture design. Visual programming and parameterized architecture family approaches to design are supported.< >

关键词： Object oriented modeling Concurrent computing Reconfigurable architectures Parallel architectures Hardware Semiconductor device modeling Algorithm design and analysis Object oriented programming computer architecture Parallel algorithms

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CAE functionality for verification of diagnostic programs

CAE functionality for verification of diagnostic programs

引用

IEEE international Test conference

作者： C. Pyron R. Sallade Test Automation DeDartment Defense Systems & Electronics Group Texas Instruments Inc. Piano TX USA

A feasibility study that has identified computer-aided engineering (CAE) features and a methodology approach that will support BIT (built-in-test) verification through fault simulation are described. With an example, the authors illustrate the evolutionary fault simulation features and the attendant methodology to support BIT verification by simulation. The simulator functionality and methodology will support the complex simulation of an embedded BIT program. These enhancements can also be effective in verification of ATE (automatic test equipment) functional tests for higher density integrated circuits and boards.< >

关键词： computer aided engineering Computational modeling Circuit simulation Circuit faults Circuit testing Fault diagnosis computer simulation Automatic test equipment Automatic testing Integrated circuit testing

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Restricted symbolic evaluation is fast and useful

Restricted symbolic evaluation is fast and useful

引用

IEEE international conference on computer-Aided Design

作者： J.L. Carter B.K. Rosen G.L. Smith V. Pitchumani IBM Research Division Yorktown Heights NY USA IBM Data Systems Division Poughkeepsie NY USA ECE Department Syracuse University Syracuse NY USA

A method is presented for simulation with two zillion and three values. The values that are propagated by the simulation include the familiar 0, 1, and X and also a collection of named unknowns and their formal negations. Each value fits into a single computer word. Applications of this restricted symbolic evaluation include design rule checking for circuits with embedded arrays and timing verification. The authors explore these two applications briefly. By carefully choosing rules for combining the two zillion and three values, and the representations of the values, it is possible to make simulation surprisingly efficient. The authors present two variants and an implementation of each. Both are fast; the faster one sometimes yields less information.< >

关键词： Computational modeling Circuit simulation Latches Logic design Data systems Application software Timing computer simulation Discrete event simulation Clocks

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Fault tolerance and reliable routing in augmented hypercube architectures

Fault tolerance and reliable routing in augmented hypercube ...

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international Phoenix conference on computers and Communications (IPCCC)

作者： M.S. Alam R. Melhem Dept. of Comput. Sci. Pittsburgh Univ. PA USA Department of Computer Science University of Pittsburgh Pittsburgh PA USA

Two schemes for augmenting hypercubes with spare nodes are presented. In both schemes, fault coverage is local in the sense that only the neighbors of the faulty nodes need to know about the faults. Routing in the presence of faults is accomplished by distributed algorithms that deliver messages reliably to their destination nodes. A message destined to a faulty node will be delivered to the spare node that replaces the faulty node. Both node and link failures may be accommodated in both schemes, and because no switches are used for reconfiguration, there is no assumptions about fault-free switches. The two schemes differ in complexity of interconnections between the spare nodes and the original cube nodes. More complex interconnections result in more flexible coverage algorithms and thus, more reliable systems. However, increased flexibility increases the complexity of the routing algorithm because more care has to be given to the possibility of messages looping in cycles and never reaching their destinations. The reliability of the fault coverage schemes and the efficiency of the routing algorithms are evaluated from simulation results.< >

关键词： Fault tolerance Routing Hypercubes Switches computer architecture Degradation computer science Distributed algorithms Computational modeling Multiprocessing systems

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Parallel processing and computational chemistry

Parallel processing and computational chemistry

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Annual international conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： P. Weiner Alliant Computer Systems Corporation Littleton MA USA

Summary form only given, as follows. With the increasing use of such methods as dynamic simulations, free energy perturbation and large-molecule ab initio calculations, chemical researchers find increasing frustration in the use of conventional computers to solve their problems. These machines are either too slow or too expensive to be practical for everyday use. However, the advent of parallel computer architectures and parallel algorithms offers a solution to this problem. In addition, the development of tools that detect dependencies and automatically create concurrent code makes the programming of these machines accessible to everyone. The author discusses these tools and their application to widely used chemical codes, such as AMBER and GAUSSIAN. The use of high performance graphics machines in computational chemistry is also discussed. An application, simultaneously running AMBER and GRAMPS, and an analysis program is shown.

关键词： Parallel processing Concurrent computing Chemistry Chemicals Computational modeling computer simulation computer architecture Parallel algorithms Automatic programming Application software

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Experimentally based parallel architecture evaluation

Experimentally based parallel architecture evaluation

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IEEE Annual international computer Software and Applications conference (COMPSAC)

作者： S.A. Fineberg Parallel Processing Laboratory School of Electrical Engineering Purdue University West Lafayette IN USA

A technique for architectural evaluation that has been used with good results and that is applicable to most experimental and commercial machines is proposed. This technique is that of careful experimentation on a bare system, i.e. one without a resident kernel, operating system, or high-level language support. The experimentation involves the implementation of simple algorithms designed to utilize the basic features of the architecture and exploit its unique features. This technique makes possible the analysis of an architecture without the complexities introduced by most operating systems and compilers and can yield insight beneficial in future language, compiler, operating system, application, and system design. Hybrid SIMD/MIMD architectures are considered as an example.< >

关键词： Parallel architectures Operating systems Hardware Partitioning algorithms Parallel processing Laboratories computer architecture Computational modeling Analytical models computer simulation

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PARET;an integrated visual tool for the study of parallel systems

PARET;an integrated visual tool for the study of parallel sy...

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IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： K.M. Nichols J.T. Edmark System Architecture Research Department AT&T Bell Labaratories Holmdel NJ USA

PARET (Parallel Architecture Research and Evaluation Tool) is an object-oriented graphical environment for the study of parallel or multiprocessor systems that provides a laboratory for investigation of alternative architectural decisions and experiments with such issues as scheduling, mapping, and routing policies. PARET is unique in providing an animated interactive visual tool for parallel systems with a modeling paradigm that is closely linked to its graphical representation. Models have the same morphology regardless of the subsystem represented or the level of detail in the model. Presently, PARET runs on SUN workstations, using color graphics, mouse input, and pop-up menus to control and observe a simulation engine. Ongoing projects using PARET include evaluation of a special-purpose multiprocessor system and use of PARET in a system to create application-specific ICs for signal processing.< >

关键词： Object oriented modeling Multiprocessing systems Parallel architectures Routing Animation Morphology Sun Workstations Graphics Mice

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