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modeling reward functions for incomplete state representations via echo state networks

Modeling reward functions for incomplete state representatio...

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international Joint conference on Neural Networks (IJCNN)

作者： K. Bush C. Anderson Department of Computer Science Colorado State University Fort Collins CO USA

This paper investigates an echo state network (ESN) (Jaeger, 2001 and Maass and Markram, 2002) architecture as the approximation of the Q-function for temporally dependent rewards embedded in a linear dynamical system, the mass-spring-damper (MSD). This problem has been solved utilizing feed-forward neural networks (FNN) when all state information necessary to specify the dynamics is provided as input (Kretchmar, 2000). Time-delayed neural networks (TDNN) solve this problem with finite-size windows of incomplete state information. Our research demonstrates that the ESN architecture represents the Q-function of the MSD system given incomplete state information as well as current feed forward neural networks given either perfect state or a temporally-windowed, incomplete state vector. The remainder of this paper is organized as follows. We introduce basic concepts of reinforcement learning and the echo state network architecture. The MSD system simulation is defined in section IV. Experimental results for learning state quality given incomplete state information are presented in section V. Results for learning estimates of all future state qualities for incomplete state information is presented in section VI. Section VII discusses the potential of the ESN for use in reinforcement learning and provides current and future directions of research.

关键词： Learning Recurrent neural networks Neural networks computer science Feedforward systems Control systems Feedforward neural networks Electronic mail computer architecture Fuzzy control

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FPGA-SPICE: A simulation-based power estimation framework for FPGAs

FPGA-SPICE: A simulation-based power estimation framework fo...

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IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： Xifan Tang Pierre-Emmanuel Gaillardon Giovanni De Micheli Integrated Systems Laboratory (LSI) Ecole Poly technique Federale de Lausanne (EPFL) Lausanne Vaud Switzerland

Mainstream Field Programmable Gate Array (FPGA) power estimation tools are based on probabilistic activity estimation and analytical power models. The power consumption of the programmable resources of FPGAs is highly sensitive to their configurations. Due to their highly flexible nature, the configurations of FPGAs routing multiplexers or Look Up Tables (LUTs) are really different from a design to another but current analytical power models cannot accurately capture the associated power differences. In this paper, we introduce a simulation-based power estimation framework for FPGAs, called FPGA-SPICE, which supports any FPGA architecture that can be described with an architectural description language. Our power estimation engine automatically generates accurate SPICE netlists according to the FPGA configurations and enables precise power analysis of FPGA architectures. SPICE testbenches can be generated at different level of complexity, denoted as full-chip-level, grid-level and component-level testbenches. Full-chip-level testbenches dump the netlists associated with the complete FPGA fabric. To reduce simulation time, FPGA-SPICE can split the full-chip-level testbenches into grid-level testbenches, each of which consisting of a complete logic block netlist, or component-level testbenches, which consider individual circuit elements, i.e., multiplexers, LUTs, flip-flops, etc., separately. We show that the grid/component-level approach can achieve 14 × speed-up with a moderate 14% accuracy loss, compared to the full-chip level. We also use FPGA-SPICE to study the power characteristics of a commercial FPGA architecture at different technology nodes. Experimental results show that the global routing architecture consumes 50% of the total power, the local routing architecture claims for 40% of the total power, and the remaining 10% comes from the LUTs and flip-flops.

关键词： Field programmable gate arrays Routing Integrated circuit modeling Estimation SPICE Table lookup

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Comparing the Consistency of User Studies Conducted in simulations and Laboratory Settings

Comparing the Consistency of User Studies Conducted in Simul...

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IEEE international conference on Robotic Computing (IRC)

作者： Jonathan Hümmer Dominik Riedelbauch Dominik Henrich Chair for Applied Computer Science III (Robotics and Embedded Systems) University of Bayreuth Bayreuth Germany

ISBN: (数字)9798331521554

ISBN: (纸本)9798331521561

Human-robot collaboration enables highly adaptive co-working. The variety of resulting workflows makes it difficult to measure metrics as, e.g. makespans or idle times for multiple systems and tasks in a comparable manner. This issue can be addressed with virtual commissioning, where arbitrary numbers of non-deterministic human-robot workflows in assembly tasks can be simulated. To this end, data-driven models of human decisions are needed. Gathering the required large corpus of data with on-site user studies is quite time-consuming. In comparison, simulation-based studies (e.g., by crowdsourcing) would allow us to access a large pool of study participants with less effort. To rely on respective study results, human action sequences observed in a browser-based simulation environment must be shown to match those gathered in a laboratory setting. To this end, this work aims to understand to what extent cooperative assembly work in a simulated environment differs from that in an on-site laboratory setting. We show how a simulation environment can be aligned with a laboratory setting in which a robot and a human perform pick-and-place tasks together. A user study (N=29) indicates that participants' assembly decisions and perception of the situation are consistent across these different environments.

关键词： Crowdsourcing Cognitive processes Atmospheric measurements Computational modeling Laboratories Human-robot interaction Particle measurements Safety Assembly Robots

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mcQEMU: Time-Accurate simulation of Multi-core platforms using QEMU

mcQEMU: Time-Accurate Simulation of Multi-core platforms usi...

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Euromicro Symposium on Digital System Design

作者： Humberto Carvalho Geoffrey Nelissen Pavel Zaykov CISTER Research Centre ISEP Polytechnic Institute of Porto Portugal Eindhoven University of Technology Eindhoven The Netherlands Honeywell International s.r.o Advanced Technology Europe Brno Czech Republic

ISBN: (数字)9781728195353

ISBN: (纸本)9781728195360

Full-system emulators allow the execution of guest operating systems and applications without the need of having access to the real target hardware. For many applications, besides the correct functional modeling, the full-system emulator shall also be time-accurate. In this paper, we present a new full-system multi-core simulator that delivers time-accurate execution and preserves the functional correctness of guest application. The proposed solution is based on QEMU. We enriched QEMU with various time models of multi-core platforms. We call this new full-system simulator mcQEMU. mcQEMU supports guest CPUs with out-of-order and in-order *** validated mcQEMU by emulating multi-core ARM processors in system mode. The time accuracy of mcQEMU is evaluated with the TACLeBench benchmark suite. From a timing prediction viewpoint, mcQEMU achieves an estimation error of only 15% in average when emulating the out-of-order ***6Quad processor by NXP. For full-system simulation, mcQEMU runs at 35 Mips for in-order architectures and 25 Mips for out-of-order ones. In user-mode simulation, mcQEMU can achieve up to 65 Mips.

关键词： Synchronization Emulation computer architecture Out of order Computational modeling Hardware

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Application of Quantum Cellular Automata in Image Steganography with an Improved Fault Tolerant Majority Voter

Application of Quantum Cellular Automata in Image Steganogra...

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IEEE international conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT)

作者： H P Bhavana Adiga R. Jayagowri VLSI Design and Embedded System B M S College of Engineering Bengaluru India

ISBN: (数字)9781538624401

ISBN: (纸本)9781538624418

Quantum Cellular Automata (QCA) is one of the powerful alternative to CMOS technology because of its low power and high speed. Because of the nano structure, Quantum dot cells are prone to get displaced or omitted during fabrication. Thus, it is very important to have the architecture of QCA gates to be resistant to such fabrication errors. Though many architectures have already been proposed for providing fault tolerance, percentage of fault tolerance provided by them is less than the architecture that we are proposing in this paper. In this paper we are proposing a new architecture to Majority Voter(MV) so as to make it fault tolerant to fabrication errors. We have also compared the proposed architecture to the existing ones for the cell misplacement effects namely single cell omission, extra cell deposition. Also, kink energy associated with the proposed architecture is calculated and is proved that the proposed architecture dissipates less power. Fault tolerant encoder and decoder are designed and simulated using the proposed fault tolerant MV. These encoders and decoders find application in Image Steganography.

关键词： Fault tolerance Fault tolerant systems computer architecture Decoding Fabrication Logic gates simulation

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Advances in Mango Leaf Disease Detection Using Deep Neural Networks

Advances in Mango Leaf Disease Detection Using Deep Neural N...

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modeling, simulation & Intelligent Computing (MoSICom), international conference on

作者： Amit Kumar Bairwa Anirudh Singh Satyam Kumar Department of AIML School of CSE Manipal University Jaipur Jaipur India

ISBN: (数字)9798331533311

ISBN: (纸本)9798331533328

In the pursuit of addressing the persistent challenges in agriculture, particularly in the realm of mango cultivation, this research paper marks the culmination of deep learning and computer vision. Focused on the imperative task of mango leaf disease detection, our study introduces innovative advancements, leveraging deep learning models. Our approach embraces a diverse ensemble of deep learning architectures, namely DenseNet121, EfficientNetB2, MobileNetV2, ResNet50, VGG16, and VGG19. Each model is meticulously trained and evaluated on an extensive dataset containing images of healthy and diseased mango leaves. The objective is to develop a robust system capable of accurate and efficient mango leaf disease identification. The results obtained from our experiments are encapsulated in a comprehensive analytics table, showcasing the performance metrics of each model. Notably, ResNet50 exhibits unparalleled accuracy at $\mathbf{9 9. 1 2 \%}$, with impressive precision, recall, and F1-score values. Our research extends beyond model evaluations, delving into the intricate nuances of each algorithm’s contributions. This critical examination serves to guide practitioners and researchers in selecting the most suitable model for their specific agricultural applications. As a testament to the practicality and real-world applicability of our research, we present a robust discussion on the implications of deploying these models in precision agriculture systems. The significance lies not only in the remarkable accuracy achieved but also in the potential for timely intervention and mitigation of economic losses associated with crop damage. It contributes to a profound understanding of the application of deep learning models in the agricultural domain.

关键词： Deep learning Precision agriculture Measurement Accuracy Biological system modeling Computational modeling Prevention and mitigation Object recognition Diseases Residual neural networks

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Optimization Techniques for Dimensionally Truncated Sparse Grids on Heterogeneous systems

Optimization Techniques for Dimensionally Truncated Sparse G...

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Euromicro conference on Parallel, Distributed and Network-Based Processing

作者： Andrei Deftu Alin Murarasu Technische Universität München Germany

Given the existing heterogeneous processor landscape dominated by CPUs and GPUs, topics such as programming productivity and performance portability have become increasingly important. In this context, an important question refers to how can we develop optimization strategies that cover both CPUs and GPUs. We answer this for fastsg, a library that provides functionality for handling efficiently high-dimensional functions. As it can be employed for compressing and decompressing large-scale simulation data, it finds itself at the core of a computational steering application which serves us as test case. We describe our experience with implementing fastsg's time critical routines for Intel CPUs and Nvidia Fermi GPUs. We show the differences and especially the similarities between our optimization strategies for the two architectures. With regard to our test case for which achieving high speedups is a "must'" for real-time visualization, we report a speedup of up to 6.2x times compared to the state-of-the-art implementation of the sparse grid technique for GPUs.

关键词： Optimization Instruction sets Graphics processing units computer architecture Vectors Programming Computational modeling

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ResNet-like Architecture with Low Hardware Requirements

ResNet-like Architecture with Low Hardware Requirements

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international conference on Pattern Recognition

作者： Elena Limonova Daniil Alfonso Dmitry Nikolaev Vladimir V. Arlazarov FRC CSC RAS Smart Engines Service LLC Moscow Russia Moscow Russia Institute for Information Transmission Problems RAS Moscow Russia

ISBN: (纸本)9781728188089;9781728188096

One of the most computationally intensive parts in modern recognition systems is an inference of deep neural networks that are used for image classification, segmentation, enhancement, and recognition. The growing popularity of edge computing makes us look for ways to reduce its time for mobile and embedded devices. One way to decrease the neural network inference time is to modify a neuron model to make it more efficient for computations on a specific device. The example of such a model is a bipolar morphological neuron model. The bipolar morphological neuron is based on the idea of replacing multiplication with addition and maximum operations. This model has been demonstrated for simple image classification with LeNet-like architectures [1]. In the paper, we introduce a bipolar morphological ResNet (BM-ResNet) model obtained from a much more complex ResNet architecture by converting its layers to bipolar morphological ones. We apply BM-ResNet to image classification on MNIST and CIFAR-10 datasets with only a moderate accuracy decrease from 99.3% to 99.1 % and from 85.3% to 85.1 %. We also estimate the computational complexity of the resulting model. We show that for the majority of ResNet layers, the considered model requires 2.1-2.9 times fewer logic gates for implementation and 15-30 % lower latency.

关键词： Training Image recognition Power demand Computational modeling Neurons computer architecture Logic gates

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A study of memory system performance of multimedia applications 01

A study of memory system performance of multimedia applicati...

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Proceedings of the 2001 ACM SIGMETRICS international conference on Measurement and modeling of computer systems

作者： Sohum Sohoni Rui Min Zhiyong Xu Yiming Hu Operating Systems and Computer Architecture Laboratory Department of Electrical & Computer Engineering and Computer Science P.O. Box 210030 University of Cincinnati Cincinnati OH

ISBN: (纸本)9781581133349

Multimedia applications are fast becoming one of the dominating workloads for modern computer systems. Since these applications normally have large data sets and little data-reuse, many researchers believe that they have poor memory behavior compared to traditional programs, and that current cache architectures cannot handle them well. It is therefore important to quantitatively characterize the memory behavior of these applications in order to provide insights for future design and research of memory systems. However, very few results on this topic have been published. This paper presents a comprehensive research on the memory requirements of a group of programs that are representative of multimedia applications. These programs include a subset of the popular MediaBench suite and several large multimedia programs running on the Linux, Windows NT and Tru UNIX operating systems. We performed extensive measurement and trace-driven simulation experiments. We then compared the memory utilization of these programs to that of SPECint95 applications. We found that multimedia applications actually have better memory behavior than SPECint95 programs. The high cache hit rates of multimedia applications can be contributed to the following three factors. Most multimedia applications apply block partitioning algorithms to the input data, and work on small blocks of data that easily fit into the cache. Secondly, within these blocks, there is significant data reuse as well as spatial locality. The third reason is that a large number of references generated by multimedia applications are to their internal data structures, which are relatively small and can also easily fit into reasonably-sized caches.

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Enabling Power Side-Channel Attack simulation on Mixed-Signal Neural Network Accelerators

Enabling Power Side-Channel Attack Simulation on Mixed-Signa...

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Omni-layer Intelligent systems (COINS), international conference on

作者： Simon Wilhelmstätter Joschua Conrad Devanshi Upadhyaya Ilia Polian Maurits Ortmanns Institute of Microelectronics University of Ulm Ulm Germany Institute for Computer Architecture and Computer Engingeering University of Stuttgart Stuttgart Germany

ISBN: (数字)9798350349597

ISBN: (纸本)9798350349603

Due to the tremendous success of Deep Learning with neural networks (NNs) in recent years and the simultaneous leap of embedded, low-power devices (e.g. wearables, smart-phones, IoT, and smart sensors), enabling the inference of those NNs in power-constrained environments gave rise to specialized NN accelerators. One paradigm followed by many of those accelerators was the transition from digital domain computing towards performing operations in the analog domain, turning them from digital to mixed-signal NN accelerators. While power-efficiency and inference accuracy have been researched with increasing interest, security and protection against a side-channel attack (SCA) have not found much attention. However, side-channels pose a major security concern by allowing an attacker to steal valuable knowledge about proprietary NNs deployed on accelerators. In order to evaluate mixed-signal NNs accelerators concerning SCA robustness, its tendency to leak information through the side-channel needs investigation. In this work, we propose a methodology for enabling side-channel analysis of mixed-signal NNs accelerators, which shows reasonable accuracy in an early development stage. The approach enables the reuse of large portions of design sources for simulation and production while providing flexibility and fast development cycles for changes to the analog design.

关键词： Accuracy Computational modeling Artificial neural networks Side-channel attacks Production Turning Robustness

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