A reference guide is provided for the tool selection process, particularly when applied to computer architecture simulation. Network II.5, Simscript II.5, and ModSim II each provide the capability for assessing comput...
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A reference guide is provided for the tool selection process, particularly when applied to computer architecture simulation. Network II.5, Simscript II.5, and ModSim II each provide the capability for assessing computerarchitectures although the underlying methodology behind each tool varies. Network II.5 is specifically designed for computer network simulation while Simscript II.5 and ModSim II are general-purpose simulation languages, with ModSim II supporting object-oriented programming. As a result, each has its own unique set of strengths and limitations that directly influence each model's ability to support modeling goals. The selection of a tool for a particular modeling effort is highly dependent upon these goals.
A reference guide is provided for the tool selection process, particularly when applied to computer architecture simulation. Network II.5, Simscript II.5, and ModSim II each provide the capability for assessing comput...
详细信息
A reference guide is provided for the tool selection process, particularly when applied to computer architecture simulation. Network II.5, Simscript II.5, and ModSim II each provide the capability for assessing computerarchitectures although the underlying methodology behind each tool varies. Network II.5 is specifically designed for computer network simulation while Simscript II.5 and ModSim II are general-purpose simulation languages, with ModSim II supporting object-oriented programming. As a result, each has its own unique set of strengths and limitations that directly influence each model's ability to support modeling goals. The selection of a tool for a particular modeling effort is highly dependent upon these goals.< >
An approach to object-oriented description of reconfigurable parallel architectures based on an extended communicating sequential processes (CSP) model of communication is presented. A workbench called OODRA (object-o...
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An approach to object-oriented description of reconfigurable parallel architectures based on an extended communicating sequential processes (CSP) model of communication is presented. A workbench called OODRA (object-oriented design of reconfigurable architectures), has been designed and implemented, based on this approach which is suitable for the development of highly concurrent, special-purpose, reconfigurable architectures. Intended uses of OODRA include parallel algorithm/architecture functional simulation and reconfiguration algorithm simulation, with an interactive graphical interface for parallel architecture design. Visual programming and parameterized architecture family approaches to design are supported.< >
A feasibility study that has identified computer-aided engineering (CAE) features and a methodology approach that will support BIT (built-in-test) verification through fault simulation are described. With an example, ...
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A feasibility study that has identified computer-aided engineering (CAE) features and a methodology approach that will support BIT (built-in-test) verification through fault simulation are described. With an example, the authors illustrate the evolutionary fault simulation features and the attendant methodology to support BIT verification by simulation. The simulator functionality and methodology will support the complex simulation of an embedded BIT program. These enhancements can also be effective in verification of ATE (automatic test equipment) functional tests for higher density integrated circuits and boards.< >
A method is presented for simulation with two zillion and three values. The values that are propagated by the simulation include the familiar 0, 1, and X and also a collection of named unknowns and their formal negati...
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A method is presented for simulation with two zillion and three values. The values that are propagated by the simulation include the familiar 0, 1, and X and also a collection of named unknowns and their formal negations. Each value fits into a single computer word. Applications of this restricted symbolic evaluation include design rule checking for circuits with embedded arrays and timing verification. The authors explore these two applications briefly. By carefully choosing rules for combining the two zillion and three values, and the representations of the values, it is possible to make simulation surprisingly efficient. The authors present two variants and an implementation of each. Both are fast; the faster one sometimes yields less information.< >
Two schemes for augmenting hypercubes with spare nodes are presented. In both schemes, fault coverage is local in the sense that only the neighbors of the faulty nodes need to know about the faults. Routing in the pre...
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Two schemes for augmenting hypercubes with spare nodes are presented. In both schemes, fault coverage is local in the sense that only the neighbors of the faulty nodes need to know about the faults. Routing in the presence of faults is accomplished by distributed algorithms that deliver messages reliably to their destination nodes. A message destined to a faulty node will be delivered to the spare node that replaces the faulty node. Both node and link failures may be accommodated in both schemes, and because no switches are used for reconfiguration, there is no assumptions about fault-free switches. The two schemes differ in complexity of interconnections between the spare nodes and the original cube nodes. More complex interconnections result in more flexible coverage algorithms and thus, more reliable systems. However, increased flexibility increases the complexity of the routing algorithm because more care has to be given to the possibility of messages looping in cycles and never reaching their destinations. The reliability of the fault coverage schemes and the efficiency of the routing algorithms are evaluated from simulation results.< >
Summary form only given, as follows. With the increasing use of such methods as dynamic simulations, free energy perturbation and large-molecule ab initio calculations, chemical researchers find increasing frustration...
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Summary form only given, as follows. With the increasing use of such methods as dynamic simulations, free energy perturbation and large-molecule ab initio calculations, chemical researchers find increasing frustration in the use of conventional computers to solve their problems. These machines are either too slow or too expensive to be practical for everyday use. However, the advent of parallel computerarchitectures and parallel algorithms offers a solution to this problem. In addition, the development of tools that detect dependencies and automatically create concurrent code makes the programming of these machines accessible to everyone. The author discusses these tools and their application to widely used chemical codes, such as AMBER and GAUSSIAN. The use of high performance graphics machines in computational chemistry is also discussed. An application, simultaneously running AMBER and GRAMPS, and an analysis program is shown.
A technique for architectural evaluation that has been used with good results and that is applicable to most experimental and commercial machines is proposed. This technique is that of careful experimentation on a bar...
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A technique for architectural evaluation that has been used with good results and that is applicable to most experimental and commercial machines is proposed. This technique is that of careful experimentation on a bare system, i.e. one without a resident kernel, operating system, or high-level language support. The experimentation involves the implementation of simple algorithms designed to utilize the basic features of the architecture and exploit its unique features. This technique makes possible the analysis of an architecture without the complexities introduced by most operating systems and compilers and can yield insight beneficial in future language, compiler, operating system, application, and system design. Hybrid SIMD/MIMD architectures are considered as an example.< >
PARET (Parallel Architecture Research and Evaluation Tool) is an object-oriented graphical environment for the study of parallel or multiprocessor systems that provides a laboratory for investigation of alternative ar...
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PARET (Parallel Architecture Research and Evaluation Tool) is an object-oriented graphical environment for the study of parallel or multiprocessor systems that provides a laboratory for investigation of alternative architectural decisions and experiments with such issues as scheduling, mapping, and routing policies. PARET is unique in providing an animated interactive visual tool for parallel systems with a modeling paradigm that is closely linked to its graphical representation. Models have the same morphology regardless of the subsystem represented or the level of detail in the model. Presently, PARET runs on SUN workstations, using color graphics, mouse input, and pop-up menus to control and observe a simulation engine. Ongoing projects using PARET include evaluation of a special-purpose multiprocessor system and use of PARET in a system to create application-specific ICs for signal processing.< >
EXIST (Exploration in Smalltalk) is an integrated environment for exploratory VLSI architectural design implemented in the Smalltalk-80 environment. It consists of a functional simulator (INSIST), a floorplanner (FLOO...
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EXIST (Exploration in Smalltalk) is an integrated environment for exploratory VLSI architectural design implemented in the Smalltalk-80 environment. It consists of a functional simulator (INSIST), a floorplanner (FLOORIST) and a database (DATABIST). EXIST contains several unique features including: editing while in simulation, manual and automated hierarchical floorplan optimization, and user-friendly interface based on the model-view controller paradigm of Smalltalk. These features make EXIST a promising environment for exploration of alternative VLSI architectures, such as RISC (reduced instruction-set computer) controllers.< >
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