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international conference on Advanced systems and Electric Technologies (IC_ASET)

作者： Amir Fares Rania Yasmine Chougui Ahlem Drif Silvia Giordano Faculty of sciences University of Setif Algeria Networks and Distributed System Laboratory Faculty of sciences University of Setif 1 Setif Algeria Networking Lab ISIN - DTI University of Applied Sciences of Southern Switzerland - SUPSI Lugano Switzerland

ISBN: (数字)9798350384895

ISBN: (纸本)9798350384901

Fake news, misinformation, and disinformation are significant cybersecurity threats worldwide, as sharing misleading or biased information can have detrimental consequences, leading individuals to act in harmful ways. It is crucial to provide fact-checking tools capable of determining the authenticity of news content, images, and videos. Despite the increasing penetration of fake news in Arabic countries, fake news detection in this context has received limited attention. This work focuses on developing an efficient approach to accurately identify fake news while also measuring the uncertainty of its predictions, a crucial aspect that has been overlooked in the field. We propose a powerful deep ensemble model that incorporates various multi-input merging techniques and different architectures. Our proposed architecture comprises a deep ensemble of three distinct models, each designed to handle specific types of inputs. The ensemble consists of Bi-Long Short Term Memory (Bi-LSTM) model utilizing embedded inputs, a Deep Neural Network (DNN) model incorporating only metadata, and a DNN model employing the Term Frequency-Inverse Document Frequency (TF-IDF) matrix. Additionally, we compute uncertainty of this detection. We further utilize a Bayesian Neural Network (BNN) architecture specifically for metadata to independently measure uncertainty and to give a qualitative evaluation of our uncertainty measure. Experimental results on a challenging dataset demonstrate that our proposed ensemble model outperforms previous works in terms of per-formance. Furthermore, by leveraging the BNN, we showcase how our ensemble architecture surpasses the standalone BNN in uncertainty accuracy. These results not only establish the validity of our proposed ensemble architecture for fake news detection, but also provide valuable information about the uncertainty associated with the model's predictions. By empowering internet users to become more critical consumers of news, these insights

关键词： Uncertainty Accuracy Computational modeling Measurement uncertainty computer architecture Artificial neural networks Predictive models

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A Micro-architecture Simulator for Multimedia Stream Processor

A Micro-architecture Simulator for Multimedia Stream Process...

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13th IEEE international conference on Electronics, Circuits and systems (ICECS'2006), vol.2

作者： Fang-Ju Lin Herming Chiueh Department of Communication Engineering College of Electrical and Computer Engineering National Chiao Tung University Hsinchu Taiwan

Recent research has proposed using stream processors for media applications. Since a programmable Stream Processor could utilize various hardware micro-architectures for diverse media applications, decision on a suitable micro-architectures to achieve efficiencies and hardware cost is critical. In this paper, a micro-architecture simulator for stream processor is implemented. The simulator evaluate the performance of media application executed on various micro-architectures, and then to analyze the utility rate of hardware and consumption of memory. By comparing the performance of media application executed on diverse micro-architectures, the optimized hardware micro-architecture can be determined for specific application and suitable micro-architecture of Stream Processor can be implemented on later VLSI for different targeting systems.

关键词： Streaming media Hardware Application software Microarchitecture Programming profession Very large scale integration Parallel processing Instruction sets Circuit simulation Computational modeling

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SmartMig: A Case for Page Migration and Self-Interleaving for On-Chip Distributed Memory systems

SmartMig: A Case for Page Migration and Self-Interleaving fo...

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IEEE international conference on High Performance Computing and Communications (HPCC)

作者： Weiwei Fu Mingmin Yuan Tianzhou Chen Qingsong Shi Li Liu Minghui Wu College of Computer Science Zhejiang University Hangzhou Zhejiang P.R. China School of Information Zhejiang Sci-Tech University Hangzhou Zhejiang P.R. China City College Zhejiang University Hangzhou Zhejiang P.R. China

ISBN: (纸本)9781479961245

This paper tries to optimize the placements of data pages, which have a strong impact on system performance. We find that both core-to-memory distance and contention on MCs and interconnects are critical. Migrating pages to their page access center can mini-mize average memory access distance, but may cause serious contention and congestion, necessitating further schemes for load balancing. Based on these observations, we propose a novel runtime mechanism called SmartMig, in which we mi-grate data pages to shorten memory access distance, while employ page self-interleaving to balance the load across the nodes. We propose models and algorithms to decide the fate of candidate pages. simulation results show that SmartMig achieves performance improvements by 26.9% and 21.0% in terms of normalized IPC and average memory access latency, which is a result of significant reduction of core-to memory distance and load in balance.

关键词： System-on-chip Educational institutions Load management Runtime Routing conferences Load modeling

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Preface

Lecture Notes in Computer Science (including subseries Lectu...

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Lecture Notes in computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 2020年 12471 LNCS卷 v页

作者： Orailoglu, Alex Jung, Matthias Reichenbach, Marc Department of Computer Science and Engineering University of California San Diego La Jolla CA United States Department of Electrical and Computer Engineering Fraunhofer IESE Kaiserslautern Germany Department of Computer Science Friedrich-Alexander University Erlangen Germany

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The Development of Multi-axis embedded CNC System Based on Dual-core Chip

The Development of Multi-axis Embedded CNC System Based on D...

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2018 international conference on computer modeling, simulation and Algorithm（CMSA2018）

作者： Xu Liu Haixin Zou Xiangfa Kong Jun Lu Shenzhen youqi lighting co.LTD. Shenzhen Institute of Information Technology Engineering Training Center School of Mechanical and Automotive Engineering South China University of Technology Guangzhou Institutes of Biomedicine and Health GIBH Chinese Academy of Sciences

At present, from the selection of the chip to the molding of the product, the embedded CNC system will encounter various problems, such as insufficient performance of the processor, hidden dangers of the physical communication scheme between the chips, insufficient reconfigurability of the platform, and transmission rate limitation and so on. This makes the development cycle of the embedded numerical control system very long. This paper combines the rapid development and mature multi-core technology of electronic products, and develops an open multi-core embedded CNC system platform based on highperformance TMS320 DM8148. The overall structure of the platform is based on a multi-core CNC system, including hardware platform construction and circuit design, dual-core and inter-core communication, and dual-core and FPGA high-speed bus communication. The reconfigurability developed by FPGA is used to develop each module in the CNC system and achieve many Axis servo driver control, and finally gives the system startup and control process, the firmware program is written to the dual-core CNC system for actual processing experiments. From the results of the performance test of the CNC system, the indicators could meet or exceed the performance requirements of the existing highperformance CNC systems, and also have open, modular and network control functions. The system platform has been successfully applied Five-axis linkage CNC machine tools, CNC milling machine, CNC engraving machine, all-electric servo CNC bending machine, spring machine and other types of CNC machine tools, reducing the design difficulty, greatly reducing the development cycle, allowing users to focus on solving specific applications Problems, and it thus quickly promote the development of the national economy and the overall level of industrial manufacturing, and has produced a very good economic and social benefits.

关键词： embedded dual-core communication multi-axis linkage FPGA interpolation CNC system

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Incentivizing Smart Vehicles For Autonomous Driving HD Maps using predictive analytics

Incentivizing Smart Vehicles For Autonomous Driving HD Maps ...

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Machine Vision, Image Processing and Imaging Technology (MVIPIT), international conference on

作者： Muhammad Ilyas Khattak Yuan Hui Inam Ullah Ajmal Khan Ayaz Ahmad School of Control Science and Engineering Shandong University Jinan City Shandong province P.R. China Depart. of Computer Science Shandong Jianzhu University (SDJZU) Jinan City Shandong province P. R. China AI & Big data Depart. Woosong University Daejeon South Korea Depart. of Electrical and Computer Engineering COMSATS Institute of Information Technology (CIIT) Wah Cantt Pakistan

ISBN: (数字)9798350306545

ISBN: (纸本)9798350306552

Recent advancements in distributed data storage, colloborative processing capabilities, and their architectural design have a profound influence on our daily lives, simplifying the process of hosting computation-intensive software applications. A single software hosting device, for instance, an Onboard Computation Unit (OBCU) of an autonomous vehicle, on the other hand, can’t keep up with the growing need for diverse requirements of computing architectures and processing power of such applications. For example, the real-time handling and generation of HD maps is one such crucial and highly computation-intensive application for autonomous vehicles. For this purpose, an efficient solution is to rely on the computing power of adjacent resource-rich nodes. Hence, the use of a latency-aware predictive analytics-based computation task offloading method has a vital significance, especially with the advent of Vehicular Edge and Fog Computing (VEFC). VEFC models pool redundant computational resources in close proximity. It, however, faces several challenges. The stochastic nature of vehicular networks, intricate heterogeneity at several levels, and the uncertainty of time-sensitive applications for the timely completion of tasks impede the VEFC’s efficiency. We developed a computation offloading framework that timely alleviates the computing-resource-deficit devices by deploying vehicles as fog-nodes commensurate with the minimum latency requirements of advanced vehicular applications, especially computation-intensive HD map handling, and generation in real-time. Our technique is a greedy heuristic method that works in small, discrete steps instead of solving the entire optimization problem holistically. We used Monte Carlo simulation to show that our approach had an overall response time of under-300 milliseconds compared to other baseline methods.

关键词： Processor scheduling Computational modeling Scheduling Real-time systems Software Resource management Time factors

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Application of stress sensing test chips to area array packaging

Application of stress sensing test chips to area array packa...

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Thermal, Mechanical and Multiphysics simulation and Experiments in Micro-Electronics and Micro-systems EuroSimE

作者： Jeffrey C. Suhling Richard C. Jaeger Pradeep Lall M. Kaysar Rahim Jordan C. Roberts Safina Hussain Department of Mechanical Engineering Department of Electrical and Computer Engineering and NSF Center of Advanced Vehicle Electronics Aubum University Auburn AL USA

Thermal cycling accelerated life testing is often used to qualify area array packages (e.g. Ball Grid Arrays and Flip Chip) for various applications. Finite element life predictions for thermal cycling configurations are challenging due to the complicated temperature/time dependent constitutive relations and failure criteria needed for solders and encapsulants and their interfaces, aging/evolving material behavior (e.g. solders), difficulties in modeling plating finishes, the complicated geometries of typical electronic assemblies, etc. In addition, in-situ measurements of stresses and strains in assemblies subjected to temperature cycling is difficult because of the extreme environmental conditions and the fact that the primary materials/interfaces of interest (e.g. solder joints, die device surface, wire bonds, etc.) are embedded within the assembly (not at the surface). For these reasons, we really know quite little about the evolution of the stresses, strains, and deformations occurring within sophisticated electronic packaging geometries during thermal cycling. In our research, we are using test chips containing piezoresistive stress sensors to continuously characterize the in-situ die surface stress during long-term thermal cycling of several different area array packaging technologies including plastic ball grid array (PBGA) components, ceramic ball grid array (CBGA) components, and flip chip on laminate assemblies. The utilized (111) silicon test chips are able to measure the complete three-dimensional stress state (all 6 stress components) at each sensor site being monitored by the data acquisition hardware. The die stresses are initially measured at room temperature after packaging. The assemblies are then subjected to thermal cycling over various temperature ranges including 0 to 100?C, -40 to 125?C, and -55 to 125?C, for up to 3000 thermal cycles. During the thermal cycling, sensor resistances at critical locations on the die device surface (e.g. the die

关键词： Testing Thermal stresses Electronic packaging thermal management Assembly Electronics packaging Stress measurement Temperature sensors Aging Sensor arrays Flip chip

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simulation of Voice Processing Applications through VLIW DSP architectures

Simulation of Voice Processing Applications through VLIW DSP...

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14th IEEE international conference on Electronics, Circuits and systems (ICECS 2007), vol.1

作者： N. Sedaghati-Mokhtari M. N. Bojnordi A. Farmahini-Farahani M. Mousavinezhad S. M. Fakhraie Silicon Intelligence Laboratory School of ECE University of Tehran Tehran Iran Iran Telecommunication Research Center Tehran Iran

This paper presents simulation of G.729a speech codec, as a compute-intensive voice processing application, on a VLIW DSP architecture. The simulator of target processor is verified by the Texas Instruments C62xx VLIW DSP architecture. The cycle-accurate simulator is implemented using C++ programming language. The G.729a reference code is modified for single- and multi-channel voice coding and is executed in the simulation environment. The experiments are performed for two modes: single and multiple channels of voice data. The obtained results demonstrate functionality of the VLIW DSP architecture for efficient evaluation of single- and multi-channel voice processing. It is achieved that the target processor is functionally available to support real-time execution of up to 10 voice channels at the 200MHz working frequency while considering all of the operating conflicts.

关键词： VLIW Digital signal processing Mathematical model Computational modeling computer architecture Instruments computer languages Speech codecs Pipelines Monitoring

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A hybrid control architecture for autonomous mobile robot navigation in unknown dynamic environment

A hybrid control architecture for autonomous mobile robot na...

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IEEE international conference on Automation Science and Engineering

作者： Danial Nakhaeinia Pierre Payeur Tang Sai Hong Babak Karasfi School of Electrical Engineering and Computer Science University of Ottawa University Putra Malaysia

ISBN: (纸本)9781467381840

This paper introduces a new hybrid control architecture for solving the navigation problem of mobile robot in an unknown dynamic environment based on an actual-virtual target switching strategy. This hybrid architecture is a combination of deliberative and reactive architectures which consists of three layers: modeling, planning and reaction. The deliberative architecture produces collision-free with shortest-distance path, while using the reactive architecture generates safe and time minimal navigation path. The proposed approach differs from previous ones in its integration architecture, the control techniques implemented in each module, and interfaces between the deliberative and reactive components. Validity and feasibility of the proposed approach are verified through simulation and real robot experiments.

关键词： Robot sensing systems Robot kinematics Collision avoidance Navigation computer architecture Planning

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Preface

International Conference on Perspective Technologies and Met...

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international conference on Perspective Technologies and Methods in MEMS Design 2018年 VII-VIII页

作者： Lobur, Mykhaylo Computer Aided Design Department Lviv Polytechnic National University Ukraine

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