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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

共 2731 条记录，以下是271-280 订阅

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A Template-based Framework for Exploring Coarse-Grained Reconfigurable architectures

A Template-based Framework for Exploring Coarse-Grained Reco...

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international conference on Application Specific systems (ASAP), architectures and Processors

作者： Artur Podobas Kentaro Sano Satoshi Matsuoka RIKEN Center for Computational Science (R-CCS) Kobe Japan

ISBN: (数字)9781728171470

ISBN: (纸本)9781728172798

Coarse-Grained Reconfigurable architectures (CGRAs) are being considered as a complementary addition to modern High-Performance Computing (HPC) systems. These reconfigurable devices overcome many of the limitations of the (more popular) FPGA, by providing higher operating frequency, denser compute capacity, and lower power consumption. Today, CGRAs have been used in several embedded applications, including automobile, telecommunication, and mobile systems, but the literature on CGRAs in HPC is sparse and the field full of research opportunities. In this work, we introduce our CGRA simulator infrastructure for use in evaluating future HPC CGRA systems. Our CGRA simulator is built on synthesizable VHDL and is highly parametrizable, including support for connectivity, SIMD, data-type width, and heterogeneity. Unlike other related work, our framework supports co-integration with third-party memory simulators or evaluation of future memory architecture, which is crucial to reason around memory-bound applications. We demonstrate how our framework can be used to explore the performance of multiple different kernels, showing the impact of different configuration and design-space options.

关键词： computer architecture System-on-chip Computational modeling Field programmable gate arrays Kernel Tools Bandwidth

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SCALPsim. a tool for modeling asynchronous Self-Organizing 3-D NoC architectures

SCALPsim. a tool for modeling asynchronous Self-Organizing 3...

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IEEE international conference on Electronics, Circuits and systems (ICECS)

作者： Diego Barrientos Claudio Sousa Andres Upegui Bernard Girau InIT HEPIA University of Applied Sciences of Western Switzerland Geneva Switzerland Université de Lorraine LORIA UMR 7503 CNRS LORIA UMR 7503 vandoeuvre-les-Nancy France

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

Manycore architectures are mainly composed of a very large amount of computing nodes interconnected with a multiplicity of links usually forming a NoC-like mesh architecture. High-speed links permit to obtain a higher throughput but are much more expensive than normal links, making the interconnection of the system a cost/performance trade-off. Simulating such architectures is very important in order to characterise the optimal network topology for a given problem. In this work we introduce SCALPsim: a simulation framework permitting to evaluate routing algorithms and network properties in 1-D, 2-D and 3-D regular mesh topologies simultaneously using links of different characteristics in terms of latency and throughput. These features are particularly interesting in large scale systems with processing elements grouped into clusters, where communication properties differ largely inside and between clusters. This paper presents the framework and an application based on Cellular Self-Organizing Maps - CSOM.

关键词： Neurons Image coding computer architecture Scalp Topology Computational modeling Routing

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Weighted record sample for underwater seismic monitoring application 34

Weighted record sample for underwater seismic monitoring app...

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34th international conference on computers and Their Applications, CATA 2019

作者： Albarakati, Hussain Ammar, Reda Elfouly, Raafat Computer Science and Engineering Department University of Connecticut StorrsCT06269 United States Computer Science Department Rhode Island College United States

ISBN: (纸本)9781510885967

Underwater acoustic sensor networks have been developed as a new technology for real-time underwater applications, including seismic monitoring, disaster prevention, and oil well inspection. Unfortunately, this new technology is constrained to data sensing, large-volume transmission, and forwarding. As a result, the transmission of large volumes of data is costly in terms of both time and power. We thus focused our research activities on the development of embedded underwater computing systems. In this advanced technology, information extraction is performed underwater using data mining techniques or compression algorithms. We previously presented a new set of real-time underwater embedded system architectures that can manage multiple network configurations. In this study, we extend our research to develop information extraction for seismic monitoring underwater application to meet real-time constraints. The system performance is measured in terms of the minimum end-to-end delay and power consumption. The simulation results are presented to measure the performance of our architecture based on the information extraction algorithm. Copyright © 2012-2020 ***. All rights reserved.

关键词： embedded systems

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simulation and Validation of a computer-Aided Design Mobile Phone Model 21

Simulation and Validation of a Computer-Aided Design Mobile ...

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21st international conference on Electromagnetics in Advanced Applications (ICEAA)

作者： Monebhurrun, Vikass Cent Supelec EXPOSE PIEM GeePs Dept Electromagnet 3 Rue Joliot Curie F-91192 Gif Sur Yvette France

ISBN: (纸本)9781728105635

The specific absorption rate (SAR) compliance of wireless communication devices, such as mobile phones, is currently assessed by performing numerous measurements using a standard dosimetric test facility [1]. Considering the number of communication systems embedded in a mobile phone and frequency bands of operation (2G at 900 MHz and 1800 MHz, 3G at 2100 MHz, 4G at 700 MHz and 2600 MHz, WiFi at 2400 MHz) and use configurations (device operated at the ear or body-worn), the standardized SAR measurement procedure proves to be time-consuming and costly. To aid with the development of the computer-aided design (CAD) of such devices, the dual-logo IEC/IEEE 62704-3-2017 SAR pre-compliance standard, which relies on finite difference time domain (FDTD)-based computational tools, has been elaborated [2].

关键词： Mobile handsets Specific absorption rate Solid modeling Computational modeling Finite difference methods Time-domain analysis Standards

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Proceedings - 2011 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

Proceedings - 2011 International Conference on Embedded Comp...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

ISBN: (纸本)9781457708008

The proceedings contain 51 papers. The topics discussed include: methods for design and implementation of dynamic signal processing systems;supercomputing: past, present, and a possible future;on STM concurrency control for multicore embedded real-time software;accelerating collective communication in message passing on manycore system-on-chip;on the impact of dynamic task scheduling in heterogeneous MPSoCs;skeleton-based automatic parallelization of image processing algorithms for GPUs;power adaptive computing system design in energy harvesting environment;Smart Cache: a self adaptive cache architecture for energy efficiency;power proportional characteristics of an energy manager for web clusters;thermal optimization for micro-architectures through selective block replication;and design metrics and visualization techniques for analyzing the performance of MOEAs in DSE.

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RTL Test Generation on Multi-Core and Many-Core architectures 32

RTL Test Generation on Multi-Core and Many-Core Architecture...

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32nd international conference on VLSI Design (VLSID) / 18th international conference on embedded systems (ES)

作者： Varadarajan, Aravind Krishnan Hsiao, Michael S. Virginia Tech Dept Elect & Comp Engn Blacksburg VA 24061 USA

ISBN: (纸本)9781728104096

Design Verification of complex circuits has become an increasingly time-consuming process. The advent of parallel computing using General Purpose Graphics Processing Units (GPGPUs) has led to enhanced performance for various applications. We propose to leverage both the multi-core CPU and the GPGPU for RTL test generation. This is achieved by implementing a test generation framework that can utilize the SIMD type parallelism available in GPGPUs and task level parallelism available on CPUs. Not all applications can be made parallel due to complex dependencies, making parallelism non-trivial. Besides, large memory bandwidth requirements can become a bottleneck hindering potential speedups. In this paper, we have ported an RTL branch coverage based test generation framework to work within the constraints of a GPGPU environment. Experimental results show that considerable speedup can be achieved for test generation without loss of coverage.

关键词： Graphics processing units Test pattern generators Parallel processing Integrated circuit modeling Instruction sets Kernel Synchronization

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Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware architectures for Robust EEG Signal Artifacts Elimination

Exploring NLMS and IPNLMS Adaptive Filtering VLSI Hardware A...

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IEEE international conference on Electronics, Circuits and systems (ICECS)

作者： Andrei La Rosa Patrícia Ucker Guilherme Paim Eduardo da Costa Sérgio Almeida Sergio Bampi Graduate Program on Computing Federal University of Pelotas (UFPel) Brazil Graduate Program on Electronic Engineering and Computing Catholic University of Pelotas (UCPel) Brazil Graduate Program on Microelectronics (PGMicro) Federal University of Rio Grande do Sul (UFRGS) Brazil

ISBN: (数字)9781728160443

ISBN: (纸本)9781728160450

The elimination of artifacts is a crucial procedure to extract the full potential of the information into the EEG processing. embedded systems require low circuit area (cost) and efficient hardware architectures. Adaptive filtering plays a vital role as a single method and hybrid approaches for robustly eliminating the noise of the real-world EEG measures. In this paper, we propose and implement hardware architectures for both NLMS and IPNLMS adaptive filters. We investigate the filtering performance and circuit area, timing, and power dissipation of the hardware architecture proposals. To leverage the power-efficiency, we improve our hardware architectures employing the data-gating circuit design technique, which provided up to 20% power savings. Also, applying an HDL-Simulink co-simulation, we perform the hardware architectures tradeoff comparing the synthesis results and filtering performance. Our investigation demonstrates that IPNLMS reduces the time domain error in 11%, increasing less than 1% of circuit area and about the double of the energy per operation, compared to the NLMS.

关键词： Electroencephalography Hardware computer architecture Convergence Measurement Clocks Proposals

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Towards Time-Sensitive Networking in Heterogeneous Platforms with Virtualization

Towards Time-Sensitive Networking in Heterogeneous Platforms...

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international conference on Emerging Technologies and Factory Automation (ETFA)

作者： Luca Leonardi Lucia Lo Bello Gaetano Patti Department of Electrical Electronics and Computer Engineering University of Catania Catania Italy

ISBN: (数字)9781728189567

ISBN: (纸本)9781728189574

The advent of commercial-off-the-shelf (COTS) heterogeneous multicore platforms is offering many opportunities in the market of embedded computing systems for many application scenarios. The integration of multiple computing elements in a single device entails impressive performance capabilities. At the same time, the increased complexity of emerging systems requires the integration of more subsystems and functionalities, among others the communication subsystem. This work deals with the desirable properties of software transmission mechanisms to enable TSN communications in heterogeneous platforms handled by a hypervisor. Moreover, preliminary simulation results provide some insights on the limits and the advantages of the investigated architectures.

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Research on state space modeling, stability analysis and pid/pidn control of dc–dc converter for digital implementation 1st

Research on state space modeling, stability analysis and pid...

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1st international conference on Advances in Electrical and computer Technologies, ICAECT 2019

作者： Viswanatha, V. Venkata Siva Reddy, R. Rajeswari Acharya Institute of Technology Bengaluru India REVA University Bengaluru India

ISBN: (纸本)9789811555572

In this article, average large signal modeling technique is applied to develop the various transfer function models of the DC–DC buck converter. With the help of transfer function, Proportional—Integral-Derivative (PID) and PID with filter co-efficient (N) so-called PIDN controller is designed for voltage mode closed-loop control in both analog and digital domain. Bode plots are developed to show the open-loop and closed-loop control in both analog and digital domains. Similarly, Pole-zero plots in both analog and digital domains in order to demonstrate the stability of the buck converter. The obtained model is simulated in two variants;(1) Simulink environment. (2) Text-based computational implementation technique. simulation results in both the variants show that with PIDN control, the steady-state and dynamic response of the buck converter is increased compared to PID control since PIDN offers wider bandwidth and high gain. The filter co-efficient "N value" is taken higher, the derivative filter term " " will become ‘s’ which is an ideal derivative term. This ideal derivative has very high gain for high-frequency signals therefore high-frequency measurement noise will generate large variations of the control signal (PWM signal) which results in erroneous system operation. To prevent this situation, the value of filter co-efficient ‘N’ is taken to be low. Here low value of ‘N’ is 22765.4257546504 which is obtained by tuning process and the whole process is demonstrated. These models pave the way in the design, development analysis of closed-loop embedded control of DC–DC converters in the platforms like DSP- and FPGA-based systems. © Springer Nature Singapore Pte Ltd 2020.

关键词： Transfer functions

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Self-aware Memory Management for Emerging Energy-efficient architectures

Self-aware Memory Management for Emerging Energy-efficient A...

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international Green Computing conference

作者： Biswadip Maity Bryan Donyanavard Nikil Dutt University of California Irvine Irvine USA Ericsson Research Stockholm Sweden

ISBN: (数字)9781665415521

ISBN: (纸本)9781665415538

With the advent of GPUs and application-specific accelerators in embedded platforms, data-intensive applications have exacerbated the memory performance and energy bottleneck. Memory requirements and usage patterns vary widely in emerging architectures, and resource contention manifests differently based on the instance of the architecture. Workload-specific and system-specific optimizations for energy-efficient architectures are impractical due to the fast-evolving landscape of computer applications and hardware. We discuss how to apply self-awareness principles to design an energy-efficient memory subsystem, and the different degrees of self-awareness such a system can achieve. We apply these principles on approximate memory systems and observe energy savings of 10.5% for on-chip L1 cache. We believe this is a rich area for research and outline some future opportunities for using self-awareness in emerging energy-efficient architectures.

关键词： Runtime Memory management Machine learning Hardware Computational modeling Optimization Adaptation models

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