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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

共 2730 条记录，以下是281-290 订阅

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RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors 21st

RVfplib: A Fast and Compact Open-Source Floating-Point Emula...

引用

21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Perotti, Matteo Tagliavini, Giuseppe Mach, Stefan Bertaccini, Luca Benini, Luca Swiss Fed Inst Technol Gloriastr 35 CH-8092 Zurich Switzerland Univ Bologna Viale Risorgimento 2 I-40136 Bologna Italy

ISBN: (纸本)9783031045806;9783031045790

Small, low-cost IoT devices rely on floating-point (FP) software emulation on 32-bit integer cores when the cost of a full-fledged FPU is not affordable. Thus, the performance and code size of the FP emulation library are decisive for meeting energy and memory-size constraints. We propose RVfplib, the first ISA-optimized open-source library for single and double-precision IEEE 754 FP emulation on RV32IM[C] cores. RVfplib is 59% smaller and 2x faster than the GCC emulation library, on average. On benchmark programs, code size reduction is 39%, and performance boost 1.5x. RVfplib is 5.3% smaller than the leading closed-source RISC-V commercial library.

关键词： RISC-V embedded IoT Floating-point Library Size Performance

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Programming multi-core architectures using data-flow techniques

Programming multi-core architectures using data-flow techniq...

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international conference on embedded computer systems

作者： Arandi, Samer Evripidou, Paraskevas Department of Computer Science University of Cyprus Nicosia Cyprus

ISBN: (纸本)9781424479382

In this paper we present a Multithreaded programming methodology for multi-core systems that utilizes Data-Flow concurrency. The programmer augments the program with macros that define threads and their data dependencies. The macros are expanded into calls to the run-time that creates and maintains the dependency graph of the threads and performs the scheduling of the threads using Data-Flow principles. We demonstrate the programming methodology and discuss some of the issues and optimizations affecting the performance. A detailed evaluation is presented using two applications as case studies. The evaluation shows that the two applications scale well and compare favorably with the results of similar systems. Our results demonstrate that Data-Flow concurrency can be efficiently implemented as a Virtual Machine on multi-core systems. ©2010 IEEE.

关键词： computer architecture

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VGM-Bench: FPU Benchmark Suite for computer Vision, computer Graphics and Machine Learning Applications 20th

VGM-Bench: FPU Benchmark Suite for Computer Vision, Computer...

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20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Cremona, Luca Fornaciari, William Galimberti, Andrea Romanoni, Andrea Zoni, Davide Politecn Milan P zza Leonardo Da Vinci 32 I-20133 Milan Italy

ISBN: (纸本)9783030609399;9783030609382

With the Internet-of-things revolution, embedded devices are in charge of an ever increasing number of tasks ranging from sensing, up to Artificial Intelligence (AI) functions. In particular, AI is gaining importance since it can dramatically improve the QoS perceived by the final user and it allows to cope with problems whose algorithmic solution is hard to find. However, the associated computational requirements, mostly made of floating-point processing, impose a careful design and tuning of the computing platforms. In this scenario, there is a need for a set of benchmarks representative of the emerging AI applications and useful to compare the efficiency of different architectural solutions and computing platforms. In this paper we present a suite of benchmarks encompassing computer Graphics, computer Vision and Machine Learning applications, which are greatly used in many AI scenarios. Such benchmarks, differently from other suites, are kernels tailored to be effectively executed in bare-metal and specifically stress the floating-point support offered by the computing platform.

关键词： Benchmarks Machine learning Artificial intelligence Floating-point FPU

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Key research challenges for successfully applying MDD within Real-Time embedded Software development

Key research challenges for successfully applying MDD within...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Hovsepyan, Aram Van Baelen, Stefan Vanhooff, Bert Joosen, Wouter Berbers, Yolande Katholieke Univ Leuven Dept Computerwetenschappen B-3001 Heverlee Belgium

ISBN: (纸本)3540364102

Model-Driven Development (MDD) is a software development paradigm that promotes the use of models at different levels of abstraction and perform transformations between them to derive one or more concrete application implementations. In this paper we analyze the current status of MDD regarding its applicability for the development of Real-Time embedded Software. We discuss different modeling framework approaches used to specify the various models, and compare OMG/MDA-based approaches (MOF, UML Profiles and executable UML) with a generic MDD-based approach (GME). Finally, we identify the key challenges for future MDD research in order to successfully apply MDD within RTES Development. These challenges are mainly situated in the field of modeling and standardization of abstraction levels, model transformations and code generation, traceability, and integration of existing software within the MDD development process

关键词： Software engineering

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Exploring System Performance using Elastic Traces: Fast, Accurate and Portable 16

Exploring System Performance using Elastic Traces: Fast, Acc...

引用

international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Jagtap, Radhika Diestelhorst, Stephan Hansson, Andreas Jung, Matthias Wehn, Norbert ARM Res Cambridge England Univ Kaiserslautern Microelect Syst Design Res Grp Kaiserslautern Germany

ISBN: (纸本)9781509030767

simulation tools are indispensable to computer architects. Detailed execution-driven CPU models offer high accuracy, but at the cost of simulation speed. Trace-driven simulation is widely adopted to alleviate this problem, especially for studies focusing on memory-system exploration. Ideally, trace-driven core models will mimic out-of-order processors executing full-system workloads to enable computer architects to evaluate modern systems. Additionally, to be useful to the broader community the tracing and replay models should be publicly available. However, existing trace-driven approaches are limited in their applicability and availability. We propose elastic traces in which we accurately capture data and load/store order dependencies by instrumenting a detailed out-of-order processor model. In contrast to existing work, we do not rely on offline analysis of timestamps, and instead use accurate dependency information tracked inside the processor pipeline. We thereby account for the effects of speculation and branch misprediction resulting in a more accurate trace playback. We provide a trace player that honours the dependencies and thus adapts its execution time to memory-system changes, as would the actual CPU. Compared to the detailed CPU, our trace player achieves a speed-up of 6-8 times. When modifying the memory-system parameters, the average error in absolute execution time is 7% for SPEC 2006 benchmarks on a bare metal system and 17% for HPC benchmarks on Linux. Relative performance is predicted with less than 3% error, achieving fast and accurate system performance exploration. We make this functionality available to the broader community via a widely-used open source full-system simulator.

关键词： computer operating systems

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Accelerating high-level engineering computations by automatic compilation of geometric algebra to hardware accelerators

Accelerating high-level engineering computations by automati...

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Huthmann, Jens Müller, Peter Stock, Florian Hildenbrand, Dietmar Koch, Andreas Embedded Systems and Applications Group Technische Universität Darmstadt Germany Computer Science Department Technische Universität Darmstadt Germany

ISBN: (纸本)9781424479382

Geometric Algebra (GA), a generalization of quaternions, is a very powerful form for intuitively expressing and manipulating complex geometric relationships common to engineering problems. The actual evaluation of GA expressions, though, is extremely compute intensive due to the high-dimensionality of data being processed. On standard desktop CPUs, GA evaluations take considerably longer than conventional mathematical formulations. GPUs do offer sufficient throughput to make the use of concise GA formulations practical, but require power far exceeding the budgets for most embedded applications. While the suitability of low-power reconfigurable accelerators for evaluating specific GA computations has already been demonstrated, these often required a significant manual design effort. We present a proof-of-concept compile flow combining symbolic and hardware optimization techniques to automatically generate accelerators from the abstract GA descriptions without user intervention that are suitable for high-performance embedded computing. ©2010 IEEE.

关键词： Program processors

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modeling Nested for Loops with Explicit Parallelism in Synchronous DataFlow Graphs 19th

Modeling Nested for Loops with Explicit Parallelism in Synch...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Honorat, Alexandre Desnos, Karol Pelcat, Maxime Nezan, Jean-Francois Univ Rennes INSA Rennes CNRS IETR UMR 6164 F-35000 Rennes France Inst Pascal UCA SIGMA CNRS UMR 6602 Clermont Ferrand France

ISBN: (纸本)9783030275624;9783030275617

A common problem when developing signal processing applications is to expose and exploit parallelism in order to improve both throughput and latency. Many programming paradigms and models have been introduced to serve this purpose, such as the Synchronous DataFlow (SDF) Model of Computation (MoC). SDF is used especially to model signal processing applications. However, the main difficulty when using SDF is to choose an appropriate granularity of the application representation, for example when translating imperative functions into SDF actors. In this paper, we propose a method to model the parallelism of perfectly nested for loops with any bounds and explicit parallelism, using SDF. This method makes it possible to easily adapt the granularity of the expressed parallelism, thanks to the introduced concept of SDF iterators. The usage of SDF iterators is then demonstrated on the Scale Invariant Feature Transform (SIFT) image processing application.

关键词： SDF Parallelism

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BOSMI: A Framework for Non-Intrusive Monitoring and Testing of embedded Multithreaded Software on the Logical Level 18

BOSMI: A Framework for Non-Intrusive Monitoring and Testing ...

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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Jahic, Jasmin Kuhn, Thomas Jung, Matthias Wehn, Norbert Fraunhofer IESE Kaiserslautern Germany Univ Kaiserslautern Kaiserslautern Germany

ISBN: (纸本)9781450364942

Traditional software testing methods are inefficient in cases where data inputs alone do not determine the outcome of a program's execution. In order to verify such software, testing is often complemented by analysis of the execution trace. For monitoring the execution trace, most approaches today insert additional instructions at the binary level, making the monitoring intrusive. Binary instrumentation operate on a low level, making it difficult to properly modify a program's states and to quantify its code coverage. In this paper, we present a framework for testing complex embedded multithreaded software on the logical level. Testing software on this level avoids dependency on concrete compilers and relates the execution to the source code, thus enabling coverage. Our non-intrusive execution monitoring and control is implemented using the LLVM interpreter compiler infrastructure. Instead of forcing thread interleaving, we suggest simulating interleaving effects through non-intrusive changes of shared variables. This makes it possible to test a single thread without executing the full software stack, which is especially useful in situations where the full software stack is not available (e.g., pre-integration testing). We complement existing approaches with new features such as dynamic configuration of monitoring and execution roll-back to the checkpoints. Our approach introduces acceptable overhead without any complex setup.

关键词： execution monitoring execution control LLVM coverage concurrency

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Design of asynchronous embedded processor with new ternary data encoding scheme

Design of asynchronous embedded processor with new ternary d...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Lee, Je-Hoon Choi, Eun-Ju Cho, Kyoung-Rok Chungbuk Natl Univ Dept Comp & Commun Engn Cheongju Chungbuk Do South Korea

ISBN: (纸本)3540364102

This paper presents a low-power implementation of the asynchronous 8051 processor, called A8051 and it employs a new data encoding method, RT/NRT encoding, to reduce switching activities. The paper focuses on power analysis of the proposed data encoding based on the experimental design of A8051. The proposed data encoding method is devised to meet the DI assumption using Ternary logic. This method reduces not only the number of wires but also the switching activities. In terms of switching activities, the proposed ternary encoding can reduce 26% comparing to conventional ternary encoding. A8051 using RT/NRT encoding shows 24% higher instruction per energy metric comparing to A8051 using dual-rail encoding.

关键词： Program processors

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Instruction buffer with limited control flow and loop nest support

Instruction buffer with limited control flow and loop nest s...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Guzma, Vladimír Pitkänen, Teemu Takala, Jarmo Department of Computer Systems Tampere University of Technology FI-33720 Tampere Finland

ISBN: (纸本)9781457708008

In this work, we present a minimalistic, energy efficient implementation of instruction buffer. We use loop detection and execution trace analysis to find most commonly executed loops in already scheduled application and tailor instruction buffer size to the size of most commonly executed loop(s). In addition to our previous work, we allow buffering of loops with limited control flow (early exit from the loop or early return to the beginning of the loop). We also show how analysis of loop nests can decrease the number of times loop body is copied from memory into the buffer. Our results show that in case of favorable loop nest, we can execute all but initial loop iterations from the instruction buffer, keeping instruction memory in the deselect mode. © 2011 IEEE.

关键词： Energy efficiency

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