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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

共 2730 条记录，以下是281-290 订阅

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Towards a transformation chain modeling language

Towards a transformation chain modeling language

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Vanhooff, Bert Van Baelen, Stefan Hovsepyan, Aram Joosen, Wouter Berbers, Yolande Katholieke Univ Leuven Dept Comp Sci B-3001 Heverlee Belgium

ISBN: (纸本)3540364102

The Model Driven Development (MDD) paradigm stimulates the use of models as the main artifacts for software development. These models can be situated at high levels of abstraction, close to the application's business domain. Many consecutive automatic transformations (a transformation chain) can be applied to these models to add the necessary details in order to generate a concrete implementation. This means that a large part of the total development effort is relocated to the development of transformations and hence we should have the necessary tooling support for designing transformation chains. In this paper we propose a metamodel for a transformation chain modeling language that enables implementation independent composition of transformations. We also propose a concrete syntax for this language that is based on UML activity diagrams.

关键词： computer programming languages

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A trace-based scenario database for high-level simulation of multimedia MP-SoCs

A trace-based scenario database for high-level simulation of...

引用

international conference on embedded computer systems

作者： Van Stralen, Peter Pimentel, Andy D. Computer Systems Architecture Group Informatics Institute University of Amsterdam Netherlands

ISBN: (纸本)9781424479382

High-level simulation and design space exploration nowadays are key ingredients for system-level design of modern multimedia embedded systems. The majority of the work in this area evaluates systems under a single, fixed application workload. In reality, however, the application workload in such systems (i.e., the applications that are concurrently executing and contending for system resources), and therefore the intensity and nature of the application demands, can change dramatically over time. To facilitate the simulation and exploration of different workload scenarios, this paper presents the concept of a so-called scenario database, which has been integrated in our Sesame system-level simulation framework. This scenario database compactly stores application scenarios and allows for generating application workloads - in the form of event traces - belonging to the stored scenarios for the purpose of scenario-aware simulation in Sesame. ©2010 IEEE.

关键词： Database systems

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A hierarchical modeling framework for on-chip communication architectures 02

A hierarchical modeling framework for on-chip communication ...

引用

international conference on computer-Aided Design

作者： Zhu, XP Malik, S Princeton Univ Princeton NJ 08544 USA

ISBN: (纸本)0780376072

The communication sub-system of complex IC systems is increasingly critical for achieving system performance. Given this, it is important that the on-chip communication architecture should be included in any quantitative evaluation of system design during design space exploration. While there are several mature methodologies for the modeling and evaluation of architectures of processing elements, there is relatively little work done in modeling of an extensive range of on-chip communication architectures, and integrating this into a single modeling and simulation environment combining processing element and on-chip communication architectures. This paper describes a modeling framework with accompanying simulation tools that attempts to fill this gap. Based on an analysis of a wide range of on-chip communication architectures, we describe how a specific hierarchical class library can be used to develop new on-chip communication architectures, or variants of existing ones with relatively little incremental effort. We demonstrate this through three case studies including two commercial on-chip bus systems and an on-chip packet switching network. Here we show that through careful analysis and construction it is possible for the modeling environment to support the common features of these architectures as part of the library and permit instantiation of the individual architectures as variants of the library design. As part of this methodology we also show how different levels of abstraction of the model can be supported and viewed as different variants that can be used in an accuracy versus simulation time trade-off.

关键词： computer architecture Software prototyping Terminology Prototypes Virtual prototyping Space exploration Instruction sets Network-on-a-chip Spine Network topology

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ImpBench revisited: An extended characterization of implant-processor benchmarks

ImpBench revisited: An extended characterization of implant-...

引用

2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Strydis, Christos Dave, Dhara Gaydadjiev, Georgi N. Computer Engineering Lab. Delft University of Technology P.O. Box 5031 2600 GA Delft Netherlands

ISBN: (纸本)9781424479382

Implants are nowadays transforming rapidly from rigid, custom-based devices with very narrow applications to highly constrained albeit multifunctional embedded systems. These systems contain cores able to execute software programs so as to allow for increased application versatility. In response to this trend, a new collection of benchmark programs for guiding the design of implant processors, ImpBench, has already been proposed and characterized. The current paper expands on this characterization study by employing a geneticalgorithm- based, design-space exploration framework. Through this framework, ImpBench components are evaluated in terms of their implications on implant-processor design. The benchmark suite is also expanded by introducing one new benchmark and two new stressmarks based on existing ImpBench benchmarks. The stressmarks are proposed for achieving further speedups in simulation times without polluting the processor-exploration process. Profiling results reveal that processor configurations generated by the stressmarks follow with good fidelity - except for some marked exceptions - ones generated by the aggregated ImpBench suite. Careful use of the stressmarks can seriously reduce simulation times up to x30, which is an impressive speedup and a good tradeoff between DSE speed and accuracy. ©2010 IEEE.

关键词： Genetic algorithms

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Fully-automatic derivation of exact program-flow constraints for a tighter worst-case execution-time analysis

Fully-automatic derivation of exact program-flow constraints...

引用

2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Marref, Amine Department of Computer Science Umm Al-Qura University Makkah Saudi Arabia

ISBN: (纸本)9781457708008

Obtaining tight worst-case execution-time (WCET) estimations of real-time tasks is crucial since overly-pessimistic estimations are deemed impractical. One way of making WCET estimations tighter is to incorporate more program-flow information e.g., context-sensitive loop bounds, infeasible-path and same-path information, etc. In this paper we present and evaluate a completely automatic analysis that dynamically derives program-flow information to use in WCET analysis. Flow information is derived by a combination of test-data generation and parsing of program-execution traces to obtain flow-fact hypotheses which are then fed to a model checker to establish their correctness. Experimental evaluation shows that our method help achieve considerable tightness in WCET estimations at a manageable cost. © 2011 IEEE.

关键词： Model checking

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A UML profile for Asynchronous Hardware Design

A UML profile for Asynchronous Hardware Design

引用

6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Sandstrom, Kim Oliver, Ian Nokia Research Center Finland

ISBN: (纸本)3540364102

In this work we present UML for Hardware Design (UML-HD), a UML profile suitable for Asynchronous Hardware Design and an approach for automatically generating a Hardware Description Language (HDL) model from UML-HD models. A UML-HD model comprises solely class diagrams and an action language. We use stereotypes in two categories structure and activity - to categorise classes. Structure type stereotypes signify state and activity type signify transitions. The approach is largely inspired by Petri nets. Several model transformations are suggested in this paper, but only code generation to Haste was implemented.

关键词： computer hardware

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Hard Edges: Hardware-Based Control-Flow Integrity for embedded Devices 21st

Hard Edges: Hardware-Based Control-Flow Integrity for Embedd...

引用

21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Christou, George Vasiliadis, Giorgos Athanasopoulos, Elias Ioannidis, Sotiris Fdn Res & Technol Hellas FORTH ICS Iraklion Greece Univ Cyprus Nicosia Cyprus Tech Univ Crete TUC ECE Khania Greece

ISBN: (纸本)9783031045806;9783031045790

Control-Flow Integrity (CFI) is a popular technique to defend against State-of-the-Art exploits, by ensuring that every (indirect) control-flow transfer points to a legitimate address and it is part of the Control-flow Graph (CFG) of a program. Enabling CFI in real systems is not straightforward, since in many cases the actual CFG of a program can only be approximated. Even in the case where there is perfect knowledge of the CFG, ensuring that all return instructions will return to their actual call sites, without employing a shadow stack, is questionable. In this work, we explore the implementation of a full-featured CFI-enabled Instruction Set Architecture (ISA) on actual hardware. Our new instructions provide the finest possible granularity for both intra-function and inter-function Control-Flow Integrity. We implement hardware-based CFI (HCFI) by modifying a SPARC SoC and evaluate the prototype on an FPGA board by running SPECInt benchmarks instrumented with a fine-grained CFI policy. HCFI can effectively protect applications from code-reuse attacks, while adding less than 1% average runtime and 2% power consumption overhead, making it particularly suitable for embedded systems.

关键词： System-on-chip

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On-chip bus modeling for power and performance estimation

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Lee, Je-Hoon Cho, Young-Shin Kim, Seok-Man Cho, Kyoung-Rok Chungbuk Informat Technol Ctr CBNU BK21 Chungbuk South Korea Samsung SDI PDP Dev Team Cheonan South Korea CCNS Lab Cheongju Chugnbuk South Korea

ISBN: (纸本)9783540736226

This paper presented a latency and power model to determine the bus configuration of a target SoC system at its early design stage. The latency model analyzed the latencies of an on-chip bus and provided throughput reflecting the bus configuration. The power model provided power estimation based on the pre-determined bus architecture. This paper showed new parameters to devise the proposed models such as bus usage, active bridge ratio, etc. Moreover, we evaluated the throughput of the bus and compared this with the required throughput of the target SoC, including a number of real IPs. This target SoC was configured based on the estimation results obtained from the proposed bus model. This estimation were compared with the simulation results of target SoC design for verifying the accuracy of the proposed model. The evaluation showed that the accuracies of the proposed model for the latency and the power model were over 85% and 92%, respectively. This result set the standard for an efficient bus structure for a SoC design.

关键词： SoC on-chip bus bus modeling bus latency

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Configurable computing for high-security/high-performance ambient systems

Configurable computing for high-security/high-performance am...

引用

5th international Workshop on embedded computer systems - architectures, modeling, and simulation

作者： Gogniat, G Burleson, W Bossuet, L UBS LESTER Lorient France Univ Massachusetts Dept Elect & Comp Engn Amherst MA 01003 USA

ISBN: (纸本)354026969X

This paper stresses why configurable computing is a promising target to guarantee the hardware security of ambient systems. Many works have focused on configurable computing to demonstrate its efficiency but as far as we know none have addressed the security issue from system to circuit levels. This paper recalls main hardware attacks before focusing on issues to build secure systems on configurable computing. Two complementary views are presented to provide a guide for security and main issues to make them a reality are discussed. As the security at the system and architecture levels is enforced by agility significant aspects related to that point are presented and illustrated through the AES algorithm. The goal of this paper is to make designers aware of that configurable computing is not just hardware accelerators for security primitives as most studies have focused on but a real solution to provide high-security/high-performance for the whole system.

关键词： embedded systems

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Performance Evaluation of the Intel Xeon Phi Manycore Architecture Using Parallel Video-Based Driver Assistance Algorithms 14

Performance Evaluation of the Intel Xeon Phi Manycore Archit...

引用

international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Arndt, Oliver Jakob Becker, Daniel Giesemann, Florian Paya-Vaya, Guillermo Bartels, Christopher Blume, Holger Leibniz Univ Hannover Inst Microelect Syst D-30167 Hannover Germany Siemens AG Corp Technol D-81739 Munich Germany

ISBN: (纸本)9781479937707

Computational-intensive algorithms are often realized with dedicated or customized hardware architectures suffering from high development costs and low flexibility thereafter. Instead, modern multicore and manycore processors can execute a diversity of software applications (e.g., driver assistance systems) written in portable high-level programming languages resulting in less porting effort at lower costs for power-consumption tolerant fields. For instance, the Intel Xeon Phi manycore processor featuring 61 cores offers not only a high theoretical peak performance but also a supportive tool chain for the software development in high-level programming languages. In contrast to traditional general-purpose multicore processors, this manycore architecture, however, exhibits different processor characteristics, inter-core communication topologies, and instruction sets. In this paper, we introduce the parallel implementation of a histogram of oriented gradients algorithm for pedestrian detection. Using a parallel semi-global matching algorithm as well, serving as an additional driver assistance algorithm, we present an in-depth performance analysis case study on the Intel Xeon Phi and also note distinct characteristics of this target platform. To allow a fair comparison, we not only rate an Intel Xeon 16-core general-purpose processor, but also present a platform comparison to customized hardware architectures.

关键词： PROCESSOR Performance Evaluation hardware architecture high-level programming languages ARCHITECTURE Software design computer software tool chain Driver Assistance systems Applications software Drivers histograms Parallel Lines Multi-core processors Building construction

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