The proceedings contain 36 papers. The special focus in this conference is on embeddedcomputersystems: architectures, modeling, and simulation. The topics include: Micro-architecture and Control Electronics Simulati...
ISBN:
(纸本)9783031460760
The proceedings contain 36 papers. The special focus in this conference is on embeddedcomputersystems: architectures, modeling, and simulation. The topics include: Micro-architecture and Control Electronics simulation of Modular Color Center-Based Quantum computers;From Algorithm to Implementation: Enabling High-Throughput CNN-Based Equalization on FPGA for Optical Communications;parti-gem5: gem5’s Timing Mode Parallelised;reliable Basic Block Energy Accounting;rattlesnakeJake: A Fast and Accurate Pre-alignment Filter Suitable for Computation-in-Memory;PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations;Fast Shared-Memory Barrier Synchronization for a 1024-Cores RISC-V Many-Core Cluster;High Performance Instruction Fetch Structure within a RISC-V Processor for Use in Harsh Environments;Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-Based Approach to simulation and modeling;DD-MPU: Dynamic and Distributed Memory Protection Unit for embedded System-on-Chips;Fault Detection Mechanisms for COTS FPGA systems Used in Low Earth Orbit;trust-Based Adaptive Routing for NoCs;run-Time Detection of Malicious Behavior Based on Exploit Decomposition Using Deep Learning: A Feasibility Study on SysJoker;a Survey of Software Implementations for the Number Theoretic Transform;METASAT: Modular Model-Based Design and Testing for Applications in Satellites;RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project;Towards Privacy-First Security Enablers for 6G Networks: The PRIVATEER Approach;RISC-V-Based Platforms for HPC: Analyzing Non-functional Properties for Future HPC and Big-Data Clusters;enabling an Isolated and Energy-Aware Deployment of Computationally Intensive Kernels on Multi-tenant Environments;quantum Computing Research Lines in the Italian Center for Supercomputing;Devices and architectures for Efficient Computing In-Memory (CIM) Design.
The proceedings contain 34 papers. The special focus in this conference is on embeddedcomputersystems: architectures, modeling, and simulation. The topics include: Embeddings of Task Mappings to Multicore ...
ISBN:
(纸本)9783031045790
The proceedings contain 34 papers. The special focus in this conference is on embeddedcomputersystems: architectures, modeling, and simulation. The topics include: Embeddings of Task Mappings to Multicore systems;RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security Enforcement;Phase-Aware CPU Workload Forecasting;whiskEras 2.0: Fast and Accurate Whisker Tracking in Rodents;strictly Periodic Scheduling of Cyclo-Static Dataflow Models;Efficient Operator Sharing Modulo Scheduling for Sum-Product Network Inference on FPGAs;a Framework for Fixed Priority Periodic Scheduling Synthesis from Synchronous Data-Flow Graphs;hard Edges: Hardware-Based Control-Flow Integrity for embedded Devices;ROCKY: Rotation Countermeasure for the Protection of Keys and Other Sensitive Data;RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors;Deep Learning Techniques for Side-Channel Analysis on AES Datasets Collected from Hardware and Software Platforms;EDRA: A Hardware-Assisted Decoupled Access/Execute Framework on the Digital Market: Invited Paper;modeling the Scalability of the EuroExa Reconfigurable Accelerators - Preliminary Results: Invited Paper;the Known Unknowns: Discovering Trade-Offs Between Heterogeneous Code Changes: Invited Paper;Towards Efficient HW Acceleration in Edge-Cloud Infrastructures: The SERRANO Approach: Invited Paper;Cross-domain Modelling of Verification and Validation Workflows in the Large Scale European Research Project VALU3S: Invited Paper;Hardware/Software Co-Design of an Automatically Generated Analog NN;Mitigating the Effects of RRAM Process Variation on the Accuracy of Artificial Neural Networks;SparseMAX: Accelerating Quantum Neural Networks on GPU Clusters Using Sparse-Matrix Kernels;SEC-Learn: Sensor Edge Cloud for Federated Learning: Invited Paper;exploiting Similarity in Evolutionary Product Design for Improved Design Space Exploration;(When) Do Multiple Passes Save Energy?;dynamic Netwo
The following topics were dealt with: embedded parallel systems; network-on-a-chip; design space exploration; processor architecture; multiprocessors; reconfigurable computing; memory and caches.
The following topics were dealt with: embedded parallel systems; network-on-a-chip; design space exploration; processor architecture; multiprocessors; reconfigurable computing; memory and caches.
Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volum...
Copyright and Reprint Permission: Abstracting is permitted with credit to the source. Libraries are permitted to photocopy beyond the limit of U.S. copyright law for private use of patrons those articles in this volume that carry a code at the bottom of the first page, provided the per-copy fee indicated in the code is paid through Copyright Clearance Center, 222 Rosewood Drive, Danvers, MA 01923. For other copying, reprint or republication permission, write to IEEE Copyrights Manager, IEEE Operations Center, 445 Hoes Lane, Piscataway, NJ 08854. All rights reserved. Copyright (c) 2012 by IEEE.
Based on fundamental physics-based considerations, we introduce the Biaffine Temperature-Voltage power model (BiTV) for SoC systems, which takes the influence of dynamic voltage, frequency, and ambient temperature con...
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ISBN:
(纸本)9783031783760;9783031783777
Based on fundamental physics-based considerations, we introduce the Biaffine Temperature-Voltage power model (BiTV) for SoC systems, which takes the influence of dynamic voltage, frequency, and ambient temperature conditions into account. Using an ARM-Cortex-based AM572x system operating in a temperature-controlled oven, we provide experimental evidence of the validity of the BiTV power model over a significant range of ambient temperatures (25 to 55 degrees C), voltages (0.98 to 1.23 V) and frequencies (100 to 1,500 MHz). These experiments and the BiTV model provide quantitative elements to assess the impact of ambient temperature on systems' performance. Such insights could be of use to system designers and compiler writers, in particular when dealing with embeddedsystems operating in harsh conditions or under energy-critical constraints.
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