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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

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Accelerating Automotive Analytics: The M2DC Appliance Approach 19th

Accelerating Automotive Analytics: The M2DC Appliance Approa...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Agosta, Giovanni Brandolese, Carlo Fornaciari, William Mainardi, Nicholas Pelosi, Gerardo Reghenzani, Federico Zanella, Michele Des Courchamps, Gaetan Ducrot, Vincent Juilly, Kevin Monot, Sebastien Ceva, Luca Politecn Milan DEIB Milan Italy AS Grp Eolen Malakoff France Vodafone Automot Telemat Zurich Switzerland

ISBN: (纸本)9783030275624;9783030275617

The Modular Microserver DataCenter (M2DC) project provides low-energy, configurable, heterogeneous servers for applications that focus on the elaboration of large data sets, but can take advantage of performance enhancement provided by transparent acceleration techniques. In this paper, we exemplify the M2DC approach through one of the project's use cases, namely automotive Internet of Things analytics. We present the main goals of the use case and we show how an appropriate M2DC microserver can be used to accelerate the application without significant modifications to its code.

关键词： Data analytics embedded systems Compilers Applied cryptography Automotive

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FPGA based application specific processing for sensor nodes

FPGA based application specific processing for sensor nodes

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Nyländen, Teemu Janhunen, Janne Hannuksela, Jari Silvén, Olli Computer Science and Engineering Laboratory University of Oulu Finland Centre for Wireless Communications University of Oulu Finland

ISBN: (纸本)9781457708008

Energy efficient sensor nodes are among the rapidly expanding applications for embedded systems technology. Typically, the processing resources in sensor nodes are based on programmable micro-controllers and digital signal processors, and the same processing architecture is used regardless of the actual task of the node. This regularly results in at least an order of magnitude over-provisioning of resources, and in higher power consumption than would be needed by tightly application specific processing solutions. Currently, experiments show that Flash FPGA technology enables implementing precisely provisioned processing for sensor nodes with energy efficiency that rivals off-the-shelf processor solutions. The expected competitiveness originates from savings in silicon real-estate, and lowered software overheads, as inherently parallel tasks can be offloaded to dedicated hardware accelerators on the same die with a microcontroller unit, and radio baseband. The results pave the way for a novel type of self-powered sensor nodes whose processing resources are configured according to their tasks. © 2011 IEEE.

关键词： Sensor nodes

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embedded computer systems: architectures, modeling, and simulation 1

引用

丛书名： Lecture Notes in computer Science

1000年

作者： Alex Orailoglu Marc Reichenbach Matthias Jung

ISBN: (数字)9783031150746

ISBN: (纸本)9783031150739

This book constitutes the proceedings of the 22;international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2021, which took place in July 2022 in Samos, Greece.;The 21 full papers presented in this volume were carefully reviewed and selected from 44 submissions. The papers are organized in topics as follows: High level synthesis; memory systems; processor architecture; embedded software systems and beyond; deep learning optimization; extra-functional property estimation; innovative architectures and tools for security; european research projects on digital systems, services, and platforms.

关键词： computer System Implementation Control Structures and Microprogramming Software Engineering/Programming and Operating systems Input/Output and Data Communications

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MGSim-A simulation environment for multi-core research and education

MGSim-A simulation environment for multi-core research and e...

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2013 13th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2013

作者： Poss, Raphael Lankamp, Mike Yang, Qiang Fu, Jian Uddin, Man Jesshope, Chris R. University of Amsterdam Computer Systems Architecture Group Science Park 904 1098XH Amsterdam Netherlands

ISBN: (纸本)9781479901036

This article presents MGSim1, an open source discrete event simulator for on-chip hardware components developed at the University of Amsterdam. MGSim is used as research and teaching vehicle to study the fine-grained hardware/software interactions on many-core chips with and without hardware multithreading. MGSim's component library includes support for core models with different instruction sets, a configurable interconnect, multiple configurable cache and memory models, a dedicated I/O subsystem, and comprehensive monitoring and interaction facilities. The default model configuration shipped with MGSim implements Microgrids, a multi-core architecture with hardware concurrency management. MGSim is furthermore written mostly in C++ and uses object classes to represent chip components. It is optimized for architecture models that can be described as process networks. © 2013 IEEE.

关键词： C++ (programming language)

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ImpBench revisited: An extended characterization of implant-processor benchmarks

ImpBench revisited: An extended characterization of implant-...

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Strydis, Christos Dave, Dhara Gaydadjiev, Georgi N. Computer Engineering Lab. Delft University of Technology P.O. Box 5031 2600 GA Delft Netherlands

ISBN: (纸本)9781424479382

Implants are nowadays transforming rapidly from rigid, custom-based devices with very narrow applications to highly constrained albeit multifunctional embedded systems. These systems contain cores able to execute software programs so as to allow for increased application versatility. In response to this trend, a new collection of benchmark programs for guiding the design of implant processors, ImpBench, has already been proposed and characterized. The current paper expands on this characterization study by employing a geneticalgorithm- based, design-space exploration framework. Through this framework, ImpBench components are evaluated in terms of their implications on implant-processor design. The benchmark suite is also expanded by introducing one new benchmark and two new stressmarks based on existing ImpBench benchmarks. The stressmarks are proposed for achieving further speedups in simulation times without polluting the processor-exploration process. Profiling results reveal that processor configurations generated by the stressmarks follow with good fidelity - except for some marked exceptions - ones generated by the aggregated ImpBench suite. Careful use of the stressmarks can seriously reduce simulation times up to x30, which is an impressive speedup and a good tradeoff between DSE speed and accuracy. ©2010 IEEE.

关键词： Genetic algorithms

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NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers 22nd

NanoController: A Minimal and Flexible Processor Architectur...

引用

22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Weissbrich, Moritz Paya-Vaya, Guillermo Tech Univ Carolo Wilhelmina Braunschweig Chair Chip Design Embedded Comp Muhlenpfordtstr 22-23 D-38106 Braunschweig Germany

ISBN: (纸本)9783031150746;9783031150739

Distributed nodes in IoT and wireless sensor networks, which are powered by small batteries or energy harvesting, are constrained to very limited energy budgets. By intelligent power management and power gating strategies for the main microcontroller of the system, the energy efficiency can be significantly increased. However, timer-based, periodical power-up sequences are too inflexible to implement these strategies, and the use of a programmable power management controller demands minimum area and ultra-low power consumption from this system part itself. In this paper, the NanoController processor architecture is proposed, which is intended to be used as a flexible system state controller in the always-on domain of smart devices. The NanoController features a compact ISA, minimal silicon area and power consumption, and enables the implementation of efficient power management strategies in comparison to much simpler and constrained always-on timer circuits. For a power management control application of an electronic door lock, the NanoController is compared to small state-of-the-art controller architectures and has up to 86% smaller code size and up to 92% less silicon area and power consumption for 65 nm standard cell ASIC implementations.

关键词： Instruction-set architecture Processor architecture Ultra-low-power microcontroller

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Hard Edges: Hardware-Based Control-Flow Integrity for embedded Devices 21st

Hard Edges: Hardware-Based Control-Flow Integrity for Embedd...

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21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Christou, George Vasiliadis, Giorgos Athanasopoulos, Elias Ioannidis, Sotiris Fdn Res & Technol Hellas FORTH ICS Iraklion Greece Univ Cyprus Nicosia Cyprus Tech Univ Crete TUC ECE Khania Greece

ISBN: (纸本)9783031045806;9783031045790

Control-Flow Integrity (CFI) is a popular technique to defend against State-of-the-Art exploits, by ensuring that every (indirect) control-flow transfer points to a legitimate address and it is part of the Control-flow Graph (CFG) of a program. Enabling CFI in real systems is not straightforward, since in many cases the actual CFG of a program can only be approximated. Even in the case where there is perfect knowledge of the CFG, ensuring that all return instructions will return to their actual call sites, without employing a shadow stack, is questionable. In this work, we explore the implementation of a full-featured CFI-enabled Instruction Set Architecture (ISA) on actual hardware. Our new instructions provide the finest possible granularity for both intra-function and inter-function Control-Flow Integrity. We implement hardware-based CFI (HCFI) by modifying a SPARC SoC and evaluate the prototype on an FPGA board by running SPECInt benchmarks instrumented with a fine-grained CFI policy. HCFI can effectively protect applications from code-reuse attacks, while adding less than 1% average runtime and 2% power consumption overhead, making it particularly suitable for embedded systems.

关键词： System-on-chip

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Performance Evaluation of the Intel Xeon Phi Manycore Architecture Using Parallel Video-Based Driver Assistance Algorithms 14

Performance Evaluation of the Intel Xeon Phi Manycore Archit...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Arndt, Oliver Jakob Becker, Daniel Giesemann, Florian Paya-Vaya, Guillermo Bartels, Christopher Blume, Holger Leibniz Univ Hannover Inst Microelect Syst D-30167 Hannover Germany Siemens AG Corp Technol D-81739 Munich Germany

ISBN: (纸本)9781479937707

Computational-intensive algorithms are often realized with dedicated or customized hardware architectures suffering from high development costs and low flexibility thereafter. Instead, modern multicore and manycore processors can execute a diversity of software applications (e.g., driver assistance systems) written in portable high-level programming languages resulting in less porting effort at lower costs for power-consumption tolerant fields. For instance, the Intel Xeon Phi manycore processor featuring 61 cores offers not only a high theoretical peak performance but also a supportive tool chain for the software development in high-level programming languages. In contrast to traditional general-purpose multicore processors, this manycore architecture, however, exhibits different processor characteristics, inter-core communication topologies, and instruction sets. In this paper, we introduce the parallel implementation of a histogram of oriented gradients algorithm for pedestrian detection. Using a parallel semi-global matching algorithm as well, serving as an additional driver assistance algorithm, we present an in-depth performance analysis case study on the Intel Xeon Phi and also note distinct characteristics of this target platform. To allow a fair comparison, we not only rate an Intel Xeon 16-core general-purpose processor, but also present a platform comparison to customized hardware architectures.

关键词： PROCESSOR Performance Evaluation hardware architecture high-level programming languages ARCHITECTURE Software design computer software tool chain Driver Assistance systems Applications software Drivers histograms Parallel Lines Multi-core processors Building construction

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On-chip bus modeling for power and performance estimation

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international conference on embedded computer systems - architectures, modeling and simulation

作者： Lee, Je-Hoon Cho, Young-Shin Kim, Seok-Man Cho, Kyoung-Rok Chungbuk Informat Technol Ctr CBNU BK21 Chungbuk South Korea Samsung SDI PDP Dev Team Cheonan South Korea CCNS Lab Cheongju Chugnbuk South Korea

ISBN: (纸本)9783540736226

This paper presented a latency and power model to determine the bus configuration of a target SoC system at its early design stage. The latency model analyzed the latencies of an on-chip bus and provided throughput reflecting the bus configuration. The power model provided power estimation based on the pre-determined bus architecture. This paper showed new parameters to devise the proposed models such as bus usage, active bridge ratio, etc. Moreover, we evaluated the throughput of the bus and compared this with the required throughput of the target SoC, including a number of real IPs. This target SoC was configured based on the estimation results obtained from the proposed bus model. This estimation were compared with the simulation results of target SoC design for verifying the accuracy of the proposed model. The evaluation showed that the accuracies of the proposed model for the latency and the power model were over 85% and 92%, respectively. This result set the standard for an efficient bus structure for a SoC design.

关键词： SoC on-chip bus bus modeling bus latency

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A Toolchain for UML-based modeling and simulation of Networked embedded systems

A Toolchain for UML-based Modeling and Simulation of Network...

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UKSim-AMSS 15th international conference on computer Modelling and simulation (UKSim)

作者： Ebeid, Emad Fummi, Franco Quaglia, Davide Univ Verona Dep Comp Sci I-37100 Verona Italy

ISBN: (纸本)9780769549941;9781467364218

We present a toolchain to model and automatically generate executable simulation code for networked embedded systems applications. First, we provide a UML extension for modeling the network in distributed embedded systems. Second, we present a toolchain to automatically translate the UML model into an intermediate description and then to SystemC executable code. Finally, the developed simulation framework is based on the state-of-the-art network simulator named SCNSL which also provides a comprehensive library of well-tested simulation models for communication networks. The framework is explained on two different case studies related to wired/wireless network applications, one for home automation and the other for agriculture applications.

关键词： UML SystemC embedded systems Network modeling simulation

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