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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

共 2731 条记录，以下是301-310 订阅

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Model-Based Design Streamlines for STM32 Motor Control embedded Software System*

Model-Based Design Streamlines for STM32 Motor Control Embed...

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international conference on Control, Decision and Information Technologies (CoDIT)

作者： Loubna BELHAMEL Arturo BUSCARINO Antonio CUCUCCIO Luigi FORTUNA Gaetano RASCONA University of Catania Catania Italy CNR-IASI Italian National Research Council-Institute for Systems Analysis and Computer Science A.Ruberti Rome Italy STMicroelectronics Catania Italy

ISBN: (数字)9781728159539

ISBN: (纸本)9781728159546

This paper presents a Model-Based Design (MBD) methodology as a promising approach for the rapid and se-cure development of embedded System applications, including those involving digital controllers. Based on existing hardware and software application-oriented tools by STMicroelectronics, a new modeling technique has been implemented to move from a traditional design workflow to an MBD one by using Mathworks ® software platform. For a practical application of the proposed approach, a case study is reported to design a Permanent Magnet Synchronous Motor (PMSM) drive based on the STM32 MCU family. The main contribution of this paper is to make focus on concretely building a unique model architecture of a complex software/hardware system able to implement all the major aspects of MBD methodology such as executable requirements, Normal and Processor-In-the-Loop (PIL) simulation modes, continuous test and verification, automatic code generation. To achieve this purpose, a new Simulink ® blockset dedicated to the STM32 Motor Control ecosystem was developed. It includes Simulink blocks for maths, algorithms, and IPs, electronic circuitries, MCU peripherals, speed sensors. Simulink ® embedded Coder tool has been used to automatically generate code for a specific STM32 MCU tar-get to overcome the time consuming and error-prone problems of the handwritten coding.

关键词： Motor drives Software packages Mathematical model Hardware Libraries Integrated circuit modeling Tools

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1st international conference on Adaptive Instructional systems, AIS 2019, held as part of the 21st international conference on Human-computer Interaction, HCI international 2019

1st International Conference on Adaptive Instructional Syste...

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1st international conference on Adaptive Instructional systems, AIS 2019, held as part of the 21st international conference on Human-computer Interaction, HCI international 2019

ISBN: (纸本)9783030223403

The proceedings contain 50 papers. The special focus in this conference is on Adaptive Instructional systems. The topics include: Ibigkas! 2.0: Directions for the Design of an Adaptive Mobile-Assisted Language Learning App;Adaptive Learning Technology for AR Training: Possibilities and Challenges;intelligent Tutoring Design Alternatives in a Serious Game;missing Pieces: Infrastructure Requirements for Adaptive Instructional systems;standards Needed: Competency modeling and Recommender systems;measuring the Complexity of Learning Content to Enable Automated Comparison, Recommendation, and Generation;Capturing AIS Behavior Using xAPI-like Statements;standardizing Unstructured Interaction Data in Adaptive Instructional systems;exploring Methods to Promote Interoperability in Adaptive Instructional systems;adaptive Team Training for One;Examining Elements of an Adaptive Instructional System (AIS) Conceptual Model;interoperability Standards for Adaptive Instructional systems: Vertical and Horizontal Integrations;integrating Engagement Inducing Interventions into Traditional, Virtual and embedded Learning Environments;productive Failure and Subgoal Scaffolding in Novel Domains;adaptation and Pedagogy at the Collective Level: Recommendations for Adaptive Instructional systems;developing an Adaptive Trainer for Joint Terminal Attack Controllers;using an Adaptive Intelligent Tutoring System to Promote Learning Affordances for Adults with Low Literacy Skills;development of Cognitive Transfer Tasks for Virtual Environments and Applications for Adaptive Instructional systems;application of Theory to the Development of an Adaptive Training System for a Submarine Electronic Warfare Task;learning Analytics of Playing Space Fortress with Reinforcement Learning;adaptive Training: Designing Training for the Way People Work and Learn;wrong in the Right Way: Balancing Realism Against Other Constraints in simulation-Based Training;adaptive Remediation with Multi-modal Content.

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Algorithm-level Approximation for Fast (or not) embedded Stereovision Algorithm 18

Algorithm-level Approximation for Fast (or not) Embedded Ste...

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18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Bonnot, Justine Desnos, Karol Menard, Daniel Univ Rennes INSA Rennes CNRS IETRUMR 6164 Rennes France

ISBN: (纸本)9781450364942

Because of the growing concern towards the energy consumption of embedded devices, the quality of an application is now considered as a new tunable parameter during the implementation phase. Approximations are then deliberately introduced to gain performance. Nevertheless, when implementing an approximate computing technique, quality deteriorations may appear. In order to check that the application Quality of Service is still met despite the induced approximations, several metrics can be used. The proposed method introduces an algorithm-level approximate computing method in a stereovision algorithm. The proposed algorithm-level approximation aims at reducing the computational load in a stereo matching algorithm that outputs a depth map from two rectified images. Based on a smart loop perforation technique, this method offers an interesting quality/complexity trade-off. However, when comparing the obtained results to a more basic approximation technique, the results show that the quality/computation time trade-off is strongly dependent on the metric used. Our paper presents the impact of the choice of the quality metric on the results of the proposed approximate computing technique.

关键词： Approximate Computing Stereo Matching Loop Perforation Algorithm-level Approximation

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mcQEMU: Time-Accurate simulation of Multi-core platforms using QEMU

mcQEMU: Time-Accurate Simulation of Multi-core platforms usi...

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Euromicro Symposium on Digital System Design

作者： Humberto Carvalho Geoffrey Nelissen Pavel Zaykov CISTER Research Centre ISEP Polytechnic Institute of Porto Portugal Eindhoven University of Technology Eindhoven The Netherlands Honeywell International s.r.o Advanced Technology Europe Brno Czech Republic

ISBN: (数字)9781728195353

ISBN: (纸本)9781728195360

Full-system emulators allow the execution of guest operating systems and applications without the need of having access to the real target hardware. For many applications, besides the correct functional modeling, the full-system emulator shall also be time-accurate. In this paper, we present a new full-system multi-core simulator that delivers time-accurate execution and preserves the functional correctness of guest application. The proposed solution is based on QEMU. We enriched QEMU with various time models of multi-core platforms. We call this new full-system simulator mcQEMU. mcQEMU supports guest CPUs with out-of-order and in-order *** validated mcQEMU by emulating multi-core ARM processors in system mode. The time accuracy of mcQEMU is evaluated with the TACLeBench benchmark suite. From a timing prediction viewpoint, mcQEMU achieves an estimation error of only 15% in average when emulating the out-of-order ***6Quad processor by NXP. For full-system simulation, mcQEMU runs at 35 Mips for in-order architectures and 25 Mips for out-of-order ones. In user-mode simulation, mcQEMU can achieve up to 65 Mips.

关键词： Synchronization Emulation computer architecture Out of order Computational modeling Hardware

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BOSMI: A Framework for Non-Intrusive Monitoring and Testing of embedded Multithreaded Software on the Logical Level 18

BOSMI: A Framework for Non-Intrusive Monitoring and Testing ...

引用

18th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Jahic, Jasmin Kuhn, Thomas Jung, Matthias Wehn, Norbert Fraunhofer IESE Kaiserslautern Germany Univ Kaiserslautern Kaiserslautern Germany

ISBN: (纸本)9781450364942

Traditional software testing methods are inefficient in cases where data inputs alone do not determine the outcome of a program's execution. In order to verify such software, testing is often complemented by analysis of the execution trace. For monitoring the execution trace, most approaches today insert additional instructions at the binary level, making the monitoring intrusive. Binary instrumentation operate on a low level, making it difficult to properly modify a program's states and to quantify its code coverage. In this paper, we present a framework for testing complex embedded multithreaded software on the logical level. Testing software on this level avoids dependency on concrete compilers and relates the execution to the source code, thus enabling coverage. Our non-intrusive execution monitoring and control is implemented using the LLVM interpreter compiler infrastructure. Instead of forcing thread interleaving, we suggest simulating interleaving effects through non-intrusive changes of shared variables. This makes it possible to test a single thread without executing the full software stack, which is especially useful in situations where the full software stack is not available (e.g., pre-integration testing). We complement existing approaches with new features such as dynamic configuration of monitoring and execution roll-back to the checkpoints. Our approach introduces acceptable overhead without any complex setup.

关键词： execution monitoring execution control LLVM coverage concurrency

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Work-in-Progress: Flexible Group-Level Pruning of Deep Neural Networks for Fast Inference on Mobile GPUs

Work-in-Progress: Flexible Group-Level Pruning of Deep Neura...

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Proceedings of the international conference on Compilers, architectures and Synthesis for embedded systems (CASES)

作者： Kwangbae Lee Hoseung Kim Hayun Lee Dongkun Shin Department of Electrical and Computer Engineering Sungkyunkwan University South Korea

Network pruning is a promising compression technique to reduce computation and memory access cost of deep neural networks. In this paper, we propose a novel group-level pruning method to accelerate deep neural networks on mobile GPUs, where several adjacent weights are pruned in a group while providing high accuracy. Although several group-level pruning techniques have been proposed, the previous techniques can not achieve the desired accuracy at high sparsity. In this paper, we propose a unaligned approach to improve the accuracy of compressed model.

关键词： Neural networks Two dimensional displays Computational modeling Hardware Registers Libraries Parallel processing

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FAuto: An Efficient GMM-HMM FPGA Implementation for Behavior Estimation in Autonomous systems

FAuto: An Efficient GMM-HMM FPGA Implementation for Behavior...

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international Joint conference on Neural Networks (IJCNN)

作者： Junde Li Navyata Gattu Swaroop Ghosh School of Electrical Engineering and Computer Science Pennsylvania State University PA USA

ISBN: (数字)9781728169262

ISBN: (纸本)9781728169279

Driving behavior estimation in car-following scenario based on contextual traffic information is an essential capability for autonomous driving systems. Real-time motion planning based on incomplete environment perception requires complicated probabilistic model for interactions with surrounding objects and road conditions. Hidden Markov Model (HMM) with Gaussian emissions has been used to model driving behaviors for its ability of inferring unobserved states. While the high-dimensional contextual data is continuously processed, the system should be high-performance and power-efficient to make real-time decisions for safe operations. Field Programmable Gate Array (FPGA) is being increasingly used on embedded System-on-Chip (SoC) for mobile applications mainly because of its parallel computation and low-power consumption. This paper implements FAuto: the framework of HMM coupled with GMM algorithm on a Xilinx PYNQ-Z2 board for autonomous systems. We design the hybrid GMM-HMM model in python, and train the model using Next Generation simulation (NGSIM) trajectory data on a CPU platform. The hardware accelerator is designed through Vivado HLS 2018.2, and verified with Jupiter notebook. FAuto achieves 2.59 TOPS/W power efficiency, and 10.39× speedup compared to Python software implementation running on quad-core i7-7500U CPU.

关键词： Hidden Markov models Estimation Field programmable gate arrays Computational modeling Markov processes Gaussian mixture model

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18th international conference on Runtime Verification, RV 2018

18th International Conference on Runtime Verification, RV 20...

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18th international conference on Runtime Verification, RV 2018

ISBN: (纸本)9783030037680

The proceedings contain 28 papers. The special focus in this conference is on Runtime Verification. The topics include: Second school on runtime verification, as part of the ArVi COST action 1402 overview and reflections;Monitoring, learning and control of cyber-physical systems with STL (Tutorial);hardware-based runtime verification with embedded tracing units and stream processing;can we monitor all multithreaded programs?;runtime verification: From propositional to first-order temporal logic;monitoring smart contracts: Contractlarva and open challenges beyond;online and offline stream runtime verification of synchronous systems;metis: Resource and context-aware monitoring of finite state properties;predictive run-time verification of discrete-time reachability properties in black-box systems using trace-level abstraction and statistical learning;efficient timed diagnosis using automata with timed domains;bringing runtime verification home;a taxonomy for classifying runtime verification tools;verifying and validating autonomous systems: Towards an integrated approach;striver: Stream runtime verification for real-time event-streams;efficient monitoring of real driving emissions;property-driven runtime resolution of feature interactions;from parametric trace slicing to rule systems;scalable online first-order monitoring;practical information flow control for web applications;time-series learning using monotonic logical properties;evaluating perception systems for autonomous vehicles using quality temporal logic;tracing distributed component-based systems, a brief overview;MLTL benchmark generation via formula progression;an environment for the partrap trace property language (Tool demonstration);writing domain-specific languages for beepbeep;a framework for non-intrusive trace-driven simulation of manycore architectures with dynamic tracing configuration.

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SqueezeNext: Hardware-Aware Neural Network Design 31

SqueezeNext: Hardware-Aware Neural Network Design

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IEEE/CVF conference on computer Vision and Pattern Recognition (CVPR)

作者： Gholami, Amir Kwon, Kiseok Wu, Bichen Tai, Zizheng Yue, Xiangyu Jin, Peter Zhao, Sicheng Keutzer, Kurt Univ Calif Berkeley EECS Berkeley CA 94720 USA

ISBN: (数字)9781538661000

ISBN: (纸本)9781538661000

One of the main barriers for deploying neural networks on embedded systems has been large memory and power consumption of existing neural networks. In this work, we introduce SqueezeNext, a new family of neural network architectures whose design was guided by considering previous architectures such as SqueezeNet, as well as by simulation results on a neural network accelerator. This new network is able to match AlexNet's accuracy on the ImageNet benchmark with 112x fewer parameters, and one of its deeper variants is able to achieve VGG-19 accuracy with only 4.4 Million parameters, (31x smaller than VGG19). SqueezeNext also achieves better top-5 classification accuracy with 1.3x fewer parameters as compared to MobileNet, but avoids using depthwise-separable convolutions that are inefficient on some mobile processor platforms. This wide range of accuracy gives the user the ability to make speed-accuracy tradeoffs, depending on the available resources on the target hardware. Using hardware simulation results for power and inference speed on an embedded system has guided us to design variations of the baseline model that are 2.59x/8.26x faster and 2.25x/7.5x more energy efficient as compared to SqueezeNet/AlexNet without any accuracy degradation.

关键词： Neural networks Hardware computer architecture Semiconductor process modeling embedded systems Power demand Computational modeling

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Scheduling Real-time HiL Co-simulation of Cyber-Physical systems on Multi-core architectures 24

Scheduling Real-time HiL Co-simulation of Cyber-Physical Sys...

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24th IEEE international conference on embedded and Real-Time Computing systems and Applications (RTCSA)

作者： Saidi, Salah Eddine Pernet, Nicolas Sorel, Yves IFP Energies Nouvelles Rueil Malmaison France INRIA Paris France

ISBN: (纸本)9781538677599

When designing complex cyber-physical systems, engineers have to integrate numerical models from different modeling environments in order to simulate the whole system and estimate its global performances. Co-simulation refers to such joint simulation of heterogeneous models. If some parts of the system are physically available, it is possible to connect these parts to the co-simulation in a Hardware-in-the-Loop (HiL) approach. In this case, the simulation has to be performed in real-time where models execution consists in periodically reacting to the real (physically available) components and providing periodic output updates. This paper deals with the parallelization and scheduling of real-time Hardware-in-the-Loop co-simulation of numerical models on multi-core architectures. A method for defining real-time constraints that have to be met is proposed. Also, an ILP formulation as well as a heuristic are proposed to solve the problem of scheduling the co-simulation on a multi-core architecture while satisfying the previously defined real-time constraints. The proposed approach is evaluated for different sizes of co-simulations and multi-core processors.

关键词： co-simulation HiL scheduling real-time multi-core

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