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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

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RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM 19th

RRAMSpec: A Design Space Exploration Framework for High Dens...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Mathew, Deepak M. Chinazzo, Andre Lucas Weis, Christian Jung, Matthias Giraud, Bastien Vivet, Pascal Levisse, Alexandre Wehn, Norbert Tech Univ Kaiserslautern Kaiserslautern Germany Fraunhofer Inst Expt Software Engn IESE Kaiserslautern Germany Univ Grenoble Alpes CEA LETI MINATEC Campus Grenoble France Ecole Polytech Fed Lausanne Embedded Syst Lab ESL Lausanne Switzerland

ISBN: (纸本)9783030275624;9783030275617

Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate architectural models of RRAM crossbar devices are required to perform system level design space explorations of new Storage Class Memory (SCM) architectures using RRAM e.g. Non-Volatile-DIMM-P (NVDIMM-P). The major challenge in architectural modeling is the trade-off between accuracy and computing intensity. In this paper we present RRAMSpec, an architecture design space exploration framework, which enables fast exploration of various architectural trade-offs in designing high density RRAM devices, at accuracy levels close to circuit level simulators. The framework estimates silicon area, timings, and energy for RRAM devices. It outperforms state-of-the-art RRAM modeling tools by conducting architectural explorations at very high accuracy levels within few seconds of execution time. Our evaluations show various trade-offs in designing RRAM crossbar arrays with respect to array sizes, write time and write energy. Finally we present the influence of technology scaling on different RRAM design trade-offs.

关键词： RRAM ReRAM Crossbar NVM

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Speculative synchronization for coherence-free embedded NUMA architectures 14

Speculative synchronization for coherence-free embedded NUMA...

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14th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2014

作者： Papagiannopoulou, Dimitra Moreshet, Tali Marongiu, Andrea Benini, Luca Herlihy, Maurice Iris Bahar, R. School of Engineering Brown University ProvidenceRI02912 United States Department of Computer Science Brown University ProvidenceRI02912 United States Department of Engineering Swarthmore College SwarthmorePA19081 United States Department of Engineering ETH Zurich Zurich8092 Switzerland

ISBN: (纸本)9781479937707

High-end embedded systems, like their general-purpose counterparts, are turning to many-core cluster-based shared-memory architectures that provide a shared memory abstraction subject to non-uniform memory access (NUMA) costs. In order to keep the cores and memory hierarchy simple, many-core embedded systems tend to employ simple, scratchpad-like memories, rather than hardware managed caches that require some form of cache coherence management. These 'coherence-free' systems still require some means to synchronize memory accesses and guarantee memory consistency. Conventional lock-based approaches may be employed to accomplish the synchronization, but may lead to both useability and performance issues. Instead, speculative synchronization, such as hardware transactional memory, may be a more attractive approach. However, hardware speculative techniques traditionally rely on the underlying cache-coherence protocol to synchronize memory accesses among the cores. The lack of a cache-coherence protocol adds new challenges in the design of hardware speculative support. In this paper, we present a new scheme for hardware transactional memory support within a cluster-based NUMA system that lacks an underlying cache-coherence protocol. To the best of our knowledge, this is the first design for speculative synchronization for this type of architecture. Through a set of benchmark experiments using our simulation platform, we show that our design can achieve significant performance improvements over traditional lock-based schemes. © 2014 IEEE.

关键词： Locks (fasteners)

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A Comparison of NoTA and GENESYS

引用

9th SAMOS international Workshop

作者： Huber, Bernhard Obermaisser, Roman Vienna Univ Technol Inst Comp Engn A-1040 Vienna Austria

ISBN: (纸本)9783642031373

In the field of embedded systems, the trend of converging application systems (e.g., multimedia systems entering the automotive domain) is observable. Undertakings to tackle the challenges introduced by this digital convergence have been started by the European Union in the last years. GENESYS is such a European project that aims at developing a cross-domain architecture for embedded systems, which facilitates this digital convergence. This paper compares the GENESYS architecture with the Network on Terminal Architecture (NoTA), which is primarily targeted to the consumer applications domain, and elaborates on their major commonalities and differences such as service-orientation, component-based design, or the need for rigorous interface specifications.

关键词： embedded systems Cross-Domain architectures

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modeling the Scalability of the EuroExa Reconfigurable Accelerators - Preliminary Results Invited Paper 21st

Modeling the Scalability of the EuroExa Reconfigurable Accel...

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21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Miliadis, Panagiotis Mpakos, Panagiotis Papadopoulou, Nikela Goumas, Georgios Pnevmatikatos, Dionisios Natl Tech Univ Athens Athens Greece

ISBN: (纸本)9783031045806;9783031045790

Current technology and application trends push for both performance and power efficiency. EuroEXA is a project that tries to achieve these goals and push its performance to exascale performance. Towards this objective, EuroEXA node integrate reconfigurable (FPGA) accelerators to offload computational intensive workloads. To fully utilize the FPGA's resource pool, multiple accelerators must be instantiated. System design and dimensioning requires an early performance estimation to evaluate different design options, including using larger FPGA devices, instantiating larger number of accelerator instances, etc. In this paper, we present the preliminary results of modeling the scalability of EuroEXA reconfigurable accelerators in the FPGA fabric. We start by using simple equations to bound the total number of kernels that can work in parallel depending on the available memory channels and reconfigurable resources. Then, we use a 2nd degree polynomial model to predict the performance benefits of instantiating multiple replicated kernels in a FPGA. The model suggests whether the switching to another larger FPGA is advantageous choice in terms of performance. We verify our results using micro-benchmarks on two state-of-the-art FPGAs;AlveoU50 and AlveoU280.

关键词： FPGA FPGA modeling EuroEXA Reconfigurable accelerators Performance prediction

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simulation OF embedded computer CODE.

SIMULATION OF EMBEDDED COMPUTER CODE.

引用

Proceedings of the 1985 Summer computer simulation conference.

作者： Wells, Brian H. Raytheon Co Bedford MA USA Raytheon Co Bedford MA USA

ISBN: (纸本)0317609459

The composition of defense systems is becoming more software oriented every day. New system architectures are taking maximum advantage of reductions in computer costs and increased memory and throughput capabilities. Existing systems are being converted from purely hardware systems to hybrid system that use computers for many of the decision and control functions. This paper reviews the system development process and presents five options for modeling computer software embedded in hybrid systems. The utility and fidelity with the actual system provided by each modeling option are discussed. Then the cost and schedule, for developing a simulation for an example system, are determined and used to perform an evaluation of the modeling options. The evaluation shows that two of the modeling options are undesirable, based on cost. Based on schedule constraints, the remaining three options should be used in an evolutionary manner to provide the necessary simulation capabilities early in the system development process.

关键词： computer simulation

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Hybrid code description for developing fast and resource efficient image processing architectures 16

Hybrid code description for developing fast and resource eff...

引用

16th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2016

作者： Haublein, Konrad Reichenbach, Marc Reiche, Oliver Akif Ozkan, M. Fey, Dietmar Hannig, Frank Teich, Jurgen Computer Architecture Martensstraße 3 Erlangen91058 Germany Hardware-Software-Co-Design Cauerstraße 11 Erlangen91058 Germany

ISBN: (纸本)9781509030767

Image processing algorithms applied on programmable embedded systems very often do not meet the given constraints in terms of real time capability. Mapping these algorithms to reconfigurable hardware solves this issue, but demands further specific knowledge in hardware development. The design process can be accelerated by code generation through high-level synthesis, which is very flexible. However, the quality of synthesis depends on many factors like the provided constraints, code description, and algorithmic complexity. Hence, optimizing these parameters may improve the generated results in terms of logic and memory utilization, as well as data throughput and synthesis duration. In this work, we aim to exploit domain-specific knowledge for a hybrid code description in order to benefit from rapid development through high-level synthesis in combination with throughput optimized generic hardware descriptions. By utilizing code generation techniques, the entire design flow gets accelerated. Our synthesis results show a similar resource utilization and achievable throughput to a pure HDL described hardware. © 2016 IEEE.

关键词： Codes (symbols)

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A flash file system to support fast mounting for NAND flash memory based embedded systems

A flash file system to support fast mounting for NAND flash ...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Park, Song-Hwa Lee, Tae-Hoon Chung, Ki-Dong Pusan Natl Univ Dept Comp Sci Pusan 609735 South Korea

ISBN: (纸本)3540364102

In embedded systems, NAND flash memory is typically used as a storage medium because of its non-volatility, fast access time and solid-state shock resistance. However, it suffers from out-place-up date, limited erase cycles and page based read/write operations. Flash file systems such as JFFS2 and YAFFS, allocate memory spaces using LFS (Log-structured File System) to solve these problems. Because of this, many pieces of a file are scattered through out flash memory. Therefore, these file systems should scan entire flash memory to construct the data structures during the mounting. This means that it takes a long time to mount such file systems on a large chip. In this paper, we design and propose a new flash memory file system which targets mobile devices that require fast mounting. We experimented on the file system performance and the results show that we improve the mounting time by 64%-76% as flash usage compared to YAFFS.

关键词： Flash memory

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Scalable multi-core simulation using parallel dynamic binary translation

Scalable multi-core simulation using parallel dynamic binary...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Almer, Oscar Böhm, Igor Von Koch, Tobias Edler Franke, Björn Kyle, Stephen Seeker, Volker Thompson, Christopher Topham, Nigel Institute for Computing Systems Architecture University of Edinburgh United Kingdom Software Engineering for Embedded Systems Group Technical University Berlin Germany

ISBN: (纸本)9781457708008

In recent years multi-core processors have seen broad adoption in application domains ranging from embedded systems through general-purpose computing to large-scale data centres. simulation technology for multi-core systems, however, lags behind and does not provide the simulation speed required to effectively support design space exploration and parallel software development. While state-of-the-art instruction set simulators (Iss) for single-core machines reach or exceed the performance levels of speed-optimised silicon implementations of embedded processors, the same does not hold for multi-core simulators where large performance penalties are to be paid. In this paper we develop a fast and scalable simulation methodology for multi-core platforms based on parallel and just-in-time (Jit) dynamic binary translation (Dbt). Our approach can model large-scale multi-core configurations, does not rely on prior profiling, instrumentation, or compilation, and works for all binaries targeting a state-of-the-art embedded multi-core platform implementing the ARCompact instruction set architecture (Isa). We have evaluated our parallel simulation methodology against the industry standard Splash-2 and Eembc MultiBench benchmarks and demonstrate simulation speeds up to 25,307 Mips on a 32-core 86 host machine for as many as 2048 target processors whilst exhibiting minimal and near constant overhead. © 2011 IEEE.

关键词： embedded systems

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Exploiting intra-function correlation with the global history stack

Exploiting intra-function correlation with the global histor...

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5th international Workshop on embedded computer systems - architectures, modeling, and simulation

作者： Gao, F Sair, S N Carolina State Univ Dept Elect & Comp Engn Raleigh NC 27695 USA

ISBN: (纸本)354026969X

The demand for more computation power in high-end embedded systems has put embedded processors on parallel evolution track as the RISC processors. Caches and deeper pipelines are standard features on recent embedded microprocessors. As a result of this, some of the performance penalties associated with branch instructions in RISC processors are becoming more prevalent in these processors, As is the case in RISC architectures, designers have turned to dynamic branch prediction to alleviate this problem. Global correlating branch predictors take advantage of the influence past branches have on future ones. The conditional branch outcomes are recorded in a global history register (GHR). Based on the hypothesis that most correlation is among intra-function branches, we provide a detailed analysis of the Global History Stack (GHS) in this paper. The GHS saves the global history in the return address stack when a call instruction is executed. Following the subsequent return, the history is restored from the stack. In addition, to preserve the correlation between the callee branches and the caller branches following the call instruction, we save a few of the history bits coming from the end of the callee's execution. We also investigate saving the GHR of a function in the Branch Target Buffer (BTB) when it returns so that it can be restored when that function is called again. Our results show that these techniques improve the accuracy of several global history based prediction schemes by 4% on average. Consequently, performance improvements as high as 13% are attained.

关键词： embedded systems

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ADL-based specification of implementation styles for functional simulators

ADL-based specification of implementation styles for functio...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Penry, David A. Cahill, Kurtis D. Department of Electrical and Computer Engineering Brigham Young University Provo UT United States

ISBN: (纸本)9781457708008

Functional simulators find widespread use as sub-systems within microarchitectural simulators. The speed of functional simulators is strongly influenced by the implementation style of the functional simulator, e.g. interpreted vs. binary-translated simulation. Speed is also strongly influenced by the level of detail of the interface the functional simulator presents to the rest of the timing simulator. This level of detail may change during design space exploration, requiring corresponding changes to the interface and the simulator. However, for many implementation styles, changing the interface is difficult. As a result, architects may choose either implementation styles which are more malleable or interfaces with more detail than is necessary. In either case, simulation speed is traded for simulator design time. We show that this tradeoff is unnecessary if an orthogonal-specification design principle is practiced: specify how a simulator is to be implemented separately from what it is implementing and then synthesize a simulator from the combined specifications. We show that the use of an Architectural Description Language (ADL) with constructs for implementation style specification makes it possible to synthesize interfaces with different implementation styles with reasonable effort. © 2011 IEEE.

关键词： Simulators

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