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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Shahabuddin, Shahriar Janhunen, Janne Bayramoglu, Muhammet Fatih Juntti, Markku Ghazi, Amanullah Silven, Olli Univ Oulu Dept Commun Engn SF-90100 Oulu Finland Univ Oulu Dept Comp Sci & Engn SF-90100 Oulu Finland

ISBN: (纸本)9781479901036

This paper summarizes the design of a programmable processor with transport triggered architecture (TTA) for decoding LDPC and turbo codes. The processor architecture is designed in such a manner that it can be programmed for LDPC or turbo decoding for the purpose of internetworking and roaming between different networks. The standard trellis based maximum a posteriori (MAP) algorithm is used for turbo decoding. Unlike most other implementations, a supercode based sum-product algorithm is used for the check node message computation for LDPC decoding. This approach ensures the highest hardware utilization of the processor architecture for the two different algorithms. Up to our knowledge, this is the first attempt to design a TTA processor for the LDPC decoder. The processor is programmed with a high level language to meet the time-to-market requirement. The optimization techniques and the usage of the function units for both algorithms are explained in detail. The processor achieves 22.64 Mbps throughput for turbo decoding with a single iteration and 10.12 Mbps throughput for LDPC decoding with five iterations for a clock frequency of 200 MHz.

关键词： computer architecture maximum likelihood estimation optimisation parity check codes turbo codes

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Current Analysis Approaches and Performance Needs for Whole Slide Image Processing in Breast Cancer Diagnostics 15

Current Analysis Approaches and Performance Needs for Whole ...

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international conference on embedded computer systems architectures modeling and simulation

作者： Pollanen, Irene Braithwaite, Billy Haataja, Keijo Ikonen, Tiia Toivanen, Pekka Univ Eastern Finland Sch Comp Kuopio Campus Kuopio Finland

ISBN: (纸本)9781467373111

In this paper, the current approaches and performance needs for whole slide image (WSI) analysis processing in breast cancer diagnostics are discussed. WSIs provide high resolution digital image data from the patient's diseased tissue. Digital whole slide images are typically very large and contain a high amount of information. Digitizing tissue specimen into the form of digital images allows the development and application of computational analysis algorithms. Biological tissues are complex with variance in tissue structures between healthy individuals as well as between patients with the same disease. Furthermore, the tissue preparation and digitization usually generates a lot of artifacts and more complexity, which causes classification challenges. This variance and also the large size of the images make creating an accurate and reliable automated breast cancer image analysis a challenge. In the ALMARVI project we aim at generating and implementing efficient histopathological image analysis algorithms in our breast cancer analysis scheme. This paper focuses on discussing relevant information concerning histopathological breast cancer diagnosis, and could also be considered as an introduction to the concept of WSI analysis to non-experts. Since the WSI sizes are very large (up to 40 GB with no compression) there are challenges on the computational analysis which requires computationally efficient tools and suitable approaches to relieve the problems caused by the large size of the images.

关键词： whole slide image breast cancer computer-aided diagnosis

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Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms

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JOURNAL OF systems ARCHITECTURE 2007年第8期53卷 511-523页

作者： McAllister, J. Woods, R. Fischaber, S. Malins, E. Queens Univ Belfast ECIT Belfast BT3 9DT Antrim North Ireland

The emergence of programmable logic devices as single-chip heterogeneous processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimisation of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working solution on FPGA-centric embedded platforms. Two particular focuses for Abhainn are the automated but configurable reallisation of inter-processor communication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimisation. This paper outlines the approaches employed in these areas and demonstrates their effectiveness on high end signal processing beamforming applications. (c) 2007 Elsevier B.V. All rights reserved.

关键词： FPGA DSP electronic system level design heterogeneous platform embedded computing

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The DESERVE project: Towards future ADAS functions 14

The DESERVE project: Towards future ADAS functions

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Kutila, Matti Pyykonen, Pasi van Koningsbruggen, Paul Pallaro, Nereo Perez-Rastelli, Joshue VTT Tech Res Ctr Finland Tampere Finland Technolution BV Gouda Netherlands Ctr Ric FIAT Turin Italy INRIA Le Chesnay France

ISBN: (纸本)9781479937707

This article introduces the objectives and structure of the European research project DESERVE that is co-funded by the ARTEMIS-JU and national funding bodies. The project started in September 2012 with a duration of 3 years. The project aims to establish a new embedded SW and HW design by using a more efficient development process (including the enabling general platform concept and tool chain) in order to overcome challenges in reducing component costs and development time of future ADAS functions for modern vehicles. Both the process and the platform concept will be demonstrated with innovative ADAS functions in 3 passenger cars, 1 truck and 1 motorcycle. embedded hardware and software units have been developed for improving electronic horizon band of vehicles by detecting objects in front. Moreover, driver/motorcycle rider awareness is analysed by monitoring his/her actions online. The systems need to be robust and reliable in different environment conditions (night time, rain, etc.). The DESERVE platform distinguishes three layers of intelligence: perception, application and intervention& warning control. The demonstrators will be based on software development tools from Elektrobit (ADTF) and Intempora (RTmaps). These tools are used to create 10 innovative ADAS applications as part of an integral ADAS development platform, following a new design and development process. Since the project is highly application oriented, the requirements have been adapted mainly from the ISO 26262 standard and the AUTOSAR framework which ensures compatibility with the existing automotive software environment.

关键词： automotive ADAS function driver monitoring camera traffic safety embedded systems

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Predictable Dynamic embedded Data Processing

Predictable Dynamic Embedded Data Processing

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Geilen, Marc Stuijk, Sander Basten, Twan Eindhoven Univ Technol Dept Elect Engn NL-5600 MB Eindhoven Netherlands

ISBN: (纸本)9781467322973;9781467322966

Cyber-physical systems interact with their physical environment. In this interaction, non-functional aspects, most notably timing, are essential to correct operation. In modern systems, dynamism is introduced in many different ways. The additional complexity threatens timely development and reliable operation. Applications often have different modes of operation with different resource requirements and different levels of required quality-of-service. Moreover, multiple applications in dynamically changing combinations share a platform and its resources. To preserve efficient development of such systems, dynamism needs to be taken into account as a primary concern, not as a verification or tuning effort after the design is done. This requires a model-driven design approach in which timing of interaction with the physical environment is taken into consideration;formal models capture applications and their platforms in the physical environment. Moreover, platforms with resources and resource arbitration are needed that allow for predictable and reliable behavior to be realized. Run-time management is further required to deal with dynamic use-cases and dynamic trade-offs encountered at run-time. In this paper, we present a model-driven approach that combines model-based design and synthesis with development of platforms that support predictable, repeatable, composable realizations and a run-time management approach to deal with dynamic use-cases at run-time. A formal, compositional model is used to exploit Pareto-optimal trade-offs in the system use. The approach is illustrated with dataflow models with dynamic application scenarios, a predictable platform architecture and run-time resource management that determines optimal trade-offs through an efficient knapsack heuristic.

关键词： Runtime physical environment Platform resource requirements operation mode Time Management management of resources Surgery dynamism

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NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers 22nd

NanoController: A Minimal and Flexible Processor Architectur...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Weissbrich, Moritz Paya-Vaya, Guillermo Tech Univ Carolo Wilhelmina Braunschweig Chair Chip Design Embedded Comp Muhlenpfordtstr 22-23 D-38106 Braunschweig Germany

ISBN: (纸本)9783031150746;9783031150739

Distributed nodes in IoT and wireless sensor networks, which are powered by small batteries or energy harvesting, are constrained to very limited energy budgets. By intelligent power management and power gating strategies for the main microcontroller of the system, the energy efficiency can be significantly increased. However, timer-based, periodical power-up sequences are too inflexible to implement these strategies, and the use of a programmable power management controller demands minimum area and ultra-low power consumption from this system part itself. In this paper, the NanoController processor architecture is proposed, which is intended to be used as a flexible system state controller in the always-on domain of smart devices. The NanoController features a compact ISA, minimal silicon area and power consumption, and enables the implementation of efficient power management strategies in comparison to much simpler and constrained always-on timer circuits. For a power management control application of an electronic door lock, the NanoController is compared to small state-of-the-art controller architectures and has up to 86% smaller code size and up to 92% less silicon area and power consumption for 65 nm standard cell ASIC implementations.

关键词： Instruction-set architecture Processor architecture Ultra-low-power microcontroller

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Profiling Dilithium Digital Signature Traces for Correlation Differential Side Channel Attacks 20th

Profiling Dilithium Digital Signature Traces for Correlation...

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20th international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Fournaris, Apostolos P. Dimopoulos, Charis Koufopavlou, Odysseas Res Ctr ATHENA Ind Syst Inst Patras Sci Pk Patras Greece Univ Patras Elect & Comp Engn Dept Rion Campus Patras Greece

ISBN: (纸本)9783030609399;9783030609382

A significant concern for the candidate schemes of the NIST postquantum cryptography standardization project is the protection they support against side-channel attacks. One of these candidate schemes currently in the NIST standardization race is the Dilithium signature scheme. This postquantum signature solution has been analyzed for side channel attack resistance especially against timing attacks. Expanding our attention on other types of side-channel analysis, this work is focused on correlation based differential side channel attacks on the polynomial multiplication operation of Dilithium digital signature generation. In this paper, we describe how a Correlation Power Attack should be adapted for the Dilithium signature generation and describe the attack process to be followed. We determine the conditions to be followed in order for such an attack to be feasible, (isolation of polynomial coefficient multiplication inpower traces) and we create a power trace profiling paradigm for the Dilithium signature scheme executed in embedded systems to showcase that the conditions can be met in practice. Expanding the methodology of recent works that mainly use simulations for power trace collection, in this paper, power trace capturing and profiling analysis of the signature generation process was succesfully done on a, noisy, Commercial off-the-shelf ARM Cortex-M4 embedded system.

关键词： Postquantum cryptography Side channel attack Secure embedded systems

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Reconfigurable multiple operation array

Reconfigurable multiple operation array

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5th international Workshop on embedded computer systems - architectures, modeling, and simulation

作者： Calderon, H Vassiliadis, S Delft Univ Technol EEMCS Comp Engn Lab Dept Elect Engn Delft Netherlands

ISBN: (纸本)354026969X

In this paper, we investigate the collapsing of eight multi-operand addition related operations into a single and common (3:2) counter array. We consider for this unit multiplication in integer and fractional representations, the Sum of Absolute Differences (SAD) in unsigned, signed magnitude and two's complement notation. Furthermore, the unit also incorporates a Multiply-Accumulation unit, (MAC) for two's complement notation. The proposed multiple operation unit was constructed around 10 element arrays that can be reduced using well known counter techniques, which are feed with the necessary data to perform the proposed eight operations: It is estimated that 6/8 of the basic (3:2) counter array is shared by the operations. The obtained results of the presented unit indicates that is capable of processing a 4x4 SAD macro-block in 36.35 ns and takes 30.43 ns to process the rest of the operations using a VIRTEX 11 PRO xc2vp100-7ff1696 FPGA device.

关键词： embedded systems

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High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP 22nd

High-Level Synthesis of Digital Circuits from Template Haske...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Folmer, H. H. de Groote, R. Bekooij, M. J. G. Univ Twente CAES Comp Architectures Embedded Syst Enschede Netherlands Sax Hogesch Enschede Netherlands

ISBN: (纸本)9783031150746;9783031150739

Functional languages as input specifications for HLS-tools allow to specify data dependencies but do not contain a notion of time nor execution order. In this paper, we propose a method to add this notion to the functional description using the dataflow model SDF-AP. SDF-AP consists of patterns that express consumption and production that we can use to enforce resource usage. We created an HLS-tool that can synthesize parallel hardware, both data and control path, based on the repetition, expressed in Higher-Order Functions, combined with specified SDF-AP patterns. Our HLS-tool, based on Template Haskell, generates an Abstract Syntax Tree based on the given patterns and the functional description uses the Clash-compiler to generate VHDL/Verilog. Case studies show consistent resource consumption and temporal behavior for our HLS-tool. A comparison with a commercially available HLS-tool shows that our tool outperforms in terms of latency and sometimes in resource consumption. The method and tool presented in this paper offer more transparency to the developer and allow to specify more accurately the synthesized hardware compared to what is possible with pragmas of the Vitis HLS-tool.

关键词： High level synthesis

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Hybrid functional and instruction level power modeling for embedded processors

Hybrid functional and instruction level power modeling for e...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Blume, Holger Becker, Daniel Botteck, Martin Brakensiek, Joerg Noll, Tobias G. Univ Aachen Rhein Westfal TH Aachen Chair Elect Engn & Comp Syst D-52062 Aachen Germany Nokia Res Ctr D-44807 Bochum Germany

ISBN: (纸本)3540364102

In this contribution the concept of Functional-Level Power Analysis (FLPA) for power estimation of programmable processors is extended in order to model even embedded general purpose processors. The basic FLPA approach is based on the separation of the processor architecture into functional blocks like e.g. processing unit, clock network, internal memory etc. The power consumption of these blocks is described by parameterized arithmetic models. By application of a parser based automated analysis of assembler codes the input parameters of the arithmetic functions like e.g. the achieved degree of parallelism or the kind and number of memory accesses can be computed. For modeling an embedded general purpose processor (here, an ARM940T) the basic FLPA modeling concept had to be extended to a so-called hybrid functional level and instruction level model in order to achieve a good modeling accuracy. The approach is exemplarily demonstrated and evaluated applying a variety of basic digital signal processing tasks ranging from basic filters to complete audio decoders. Estimated power figures for the inspected tasks are compared to physically measured values. A resulting maximum estimation error of less than 8 % is achieved.

关键词： Program processors

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