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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Folmer, H. H. de Groote, R. Bekooij, M. J. G. Univ Twente CAES Comp Architectures Embedded Syst Enschede Netherlands Sax Hogesch Enschede Netherlands

ISBN: (纸本)9783031150746;9783031150739

Functional languages as input specifications for HLS-tools allow to specify data dependencies but do not contain a notion of time nor execution order. In this paper, we propose a method to add this notion to the functional description using the dataflow model SDF-AP. SDF-AP consists of patterns that express consumption and production that we can use to enforce resource usage. We created an HLS-tool that can synthesize parallel hardware, both data and control path, based on the repetition, expressed in Higher-Order Functions, combined with specified SDF-AP patterns. Our HLS-tool, based on Template Haskell, generates an Abstract Syntax Tree based on the given patterns and the functional description uses the Clash-compiler to generate VHDL/Verilog. Case studies show consistent resource consumption and temporal behavior for our HLS-tool. A comparison with a commercially available HLS-tool shows that our tool outperforms in terms of latency and sometimes in resource consumption. The method and tool presented in this paper offer more transparency to the developer and allow to specify more accurately the synthesized hardware compared to what is possible with pragmas of the Vitis HLS-tool.

关键词： High level synthesis

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Software-oriented system-level simulation for design space exploration of reconfigurable architectures

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10th Asia-Pacific conference on Advances in computer systems Architecture

作者： Tham, KS Maskell, DL Nanyang Technol Univ Ctr High Performance Embedded Syst Singapore Singapore

ISBN: (纸本)3540296433

To efficiently utilize the functionality of dynamic reconfigurable computing systems, it is imperative that a software-oriented approach for modeling complex hardware/software systems be adopted. To achieve this, we need to enhance the simulation environment to understand these dynamic reconfiguration requirements during system-level modeling. We present a flexible simulation model which is able to produce multiple views/contexts for a given problem. We use this model to examine each view for the mapping space, bandwidth, reconfiguration requirements, and configuration patterns of each computational problem.

关键词： computer architecture

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Rapid implementation and optimisation of DSP systems on FPGA-centric heterogeneous platforms

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JOURNAL OF systems ARCHITECTURE 2007年第8期53卷 511-523页

作者： McAllister, J. Woods, R. Fischaber, S. Malins, E. Queens Univ Belfast ECIT Belfast BT3 9DT Antrim North Ireland

The emergence of programmable logic devices as single-chip heterogeneous processing platforms for digital signal processing applications poses challenges concerning rapid implementation and high level optimisation of algorithms on these platforms. This paper describes Abhainn, a rapid implementation methodology and toolsuite for translating an algorithmic expression of the system to a working solution on FPGA-centric embedded platforms. Two particular focuses for Abhainn are the automated but configurable reallisation of inter-processor communication fabrics, and the establishment of novel dedicated hardware component design methodologies allowing algorithm level transformation for system optimisation. This paper outlines the approaches employed in these areas and demonstrates their effectiveness on high end signal processing beamforming applications. (c) 2007 Elsevier B.V. All rights reserved.

关键词： FPGA DSP electronic system level design heterogeneous platform embedded computing

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Reducing execution unit leakage power in embedded processors

Reducing execution unit leakage power in embedded processors

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Homayoun, Houman Baniasadi, Amirali Univ Victoria Dept Elect & Comp Engn Victoria BC Canada

ISBN: (纸本)3540364102

We introduce low-overhead power optimization techniques to reduce leakage power in embedded processors. Our techniques improve previous work by a) taking into account idle time distribution for different execution units, and b) using instruction decode and control dependencies to wakeup the gated (but needed) units as soon as possible. We take into account idle time distribution per execution unit to detect an idle time period as soon as possible. This in turn results in increasing our leakage power savings. In addition, we use information already available in the processor to predict when a gated execution unit will be needed again. This results in early and less costly reactivation of gated execution units. We evaluate our techniques for a representative subset of MiBench benchmarks and for a processor using a configuration similar to Intels Xscale processor. We show that our techniques reduce leakage power considerably while maintaining performance.

关键词： Program processors

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Reconfigurable multiple operation array

Reconfigurable multiple operation array

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5th international Workshop on embedded computer systems - architectures, modeling, and simulation

作者： Calderon, H Vassiliadis, S Delft Univ Technol EEMCS Comp Engn Lab Dept Elect Engn Delft Netherlands

ISBN: (纸本)354026969X

In this paper, we investigate the collapsing of eight multi-operand addition related operations into a single and common (3:2) counter array. We consider for this unit multiplication in integer and fractional representations, the Sum of Absolute Differences (SAD) in unsigned, signed magnitude and two's complement notation. Furthermore, the unit also incorporates a Multiply-Accumulation unit, (MAC) for two's complement notation. The proposed multiple operation unit was constructed around 10 element arrays that can be reduced using well known counter techniques, which are feed with the necessary data to perform the proposed eight operations: It is estimated that 6/8 of the basic (3:2) counter array is shared by the operations. The obtained results of the presented unit indicates that is capable of processing a 4x4 SAD macro-block in 36.35 ns and takes 30.43 ns to process the rest of the operations using a VIRTEX 11 PRO xc2vp100-7ff1696 FPGA device.

关键词： embedded systems

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Efficient static buffering to guarantee throughput-optimal FPGA implementation of synchronous dataflow graphs

Efficient static buffering to guarantee throughput-optimal F...

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Kee, Hojin Bhattacharyya, Shuvra S. Kornerup, Jacob Department of Electrical and Computer Engineering University of Maryland College Park MD 20742 United States National Instruments Corp. Austin TX 78759 United States

ISBN: (纸本)9781424479382

When designing DSP applications for implementation on field programmable gate arrays (FPGAs), it is often important to minimize consumption of limited FPGA resources while satisfying real-time performance constraints. In this paper, we develop efficient techniques to determine dataflow graph buffer sizes that guarantee throughput-optimal execution when mapping synchronous dataflow (SDF) representations of DSP applications onto FPGAs. Our techniques are based on a novel two-actor SDF graph Model (TASM), which efficiently captures the behavior and costs associated with SDF graph edges (flowgraph connections). With our proposed techniques, designers can automatically generate upper bounds on SDF graph buffer distributions that realize maximum achievable throughput performance for the corresponding applications. Furthermore, our proposed techinque is characterized by low polynomial time complexity, which is useful for rapid prototyping in DSP system design. ©2010 IEEE.

关键词： Throughput

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Software/network Co-simulation of heterogeneous industrial networks architectures

Software/network Co-simulation of heterogeneous industrial n...

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Proceedings - IEEE international conference on computer Design: VLSI in computers and Processors, ICCD 2004

作者： Fummi, F. Martini, S. Monguzzi, M. Perbellini, G. Poncino, M. Universitá di Verona Verona Italy Sitek S.p.A S.G. Lupatoto Italy Embedded Systems Design Center Verona Italy

ISBN: (纸本)0769522319

The work presents a modeling and analysis framework for heterogeneous industrial networks architectures which is based on a tight integration of a network simulator with embedded software, middleware and a real-time operating system. This framework is suitable for modeling and simulating the behavior of typical components involved in factory automation applications (e.g., PLCs, remote controllers, operational screens, etc.) when they are connected through heterogeneous industrial networks. Experiments show that the framework allows to take early architectural decisions by evaluating the expected system performance based on the available models. © 2004 IEEE.

关键词： computer architecture

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Energy-aware design space exploration of registerfile for extensible processors

Energy-aware design space exploration of registerfile for ex...

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2010 10th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2010

作者： Yazdanbakhsh, Amir Kamal, Mehdi Salehi, Mostafa E. Noori, Hamid Fakhraie, Sied Mehdi Silicone Intelligence and VLSI Systems Laboratory School of Electrical and Computer Engineering University of Tehran Tehran 14395-515 Iran Low-Power High-Performance Nanosystems Laboratory School of Electrical and Computer Engineering University of Tehran Tehran 14395-515 Iran

ISBN: (纸本)9781424479382

This paper describes an energy-aware methodology that identifies custom instructions for critical code segments, given the available data bandwidth constraint between custom logic and a base processor. Our approach enables designers to optionally constrain the number of input and output operands for custom instructions to reach the acceptable performance considering the energy dissipation of the registerfile. We describe a design flow to identify promising area, performance, and power tradeoffs. We study the effect of custom instruction I/O constraints and registerfile input/output (I/O) ports on overall performance and energy usage of the registerfile. Our experiments show that, in most cases, the solutions with the highest performance are not identified with relaxed I/O constraints. Results for packet-processing benchmarks covering cryptography and lookup applications are shown, with speed-ups between 25% and 40%, and energy reduction between 20% and 30%. ©2010 IEEE.

关键词： Energy dissipation

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Pre-simulation elaboration of heterogeneous systems: The SystemC multi-disciplinary virtual prototyping approach 15

Pre-simulation elaboration of heterogeneous systems: The Sys...

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15th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2015

作者： Aoun, Cédric Ben Andrade, Liliana Maehne, Torsten Pêcheux, François Louërat, Marie-Minerve Vachouxy, Alain Sorbonne Universités UPMC Univ Paris 06 CNRS UMR 7606 Paris France LSM Lausanne Switzerland

ISBN: (纸本)9781467373111

Designers of the upcoming digital-centric More-than-Moore systems are lacking a common design and simulation environment able to efficiently manage all the multi-disciplinary aspects of its components of various nature that closely interact with each other. A key to successful design and verification lies in a SystemC-based virtual prototyping environment that is able to simulate a complex heterogeneous system as a whole, for which each component is described and solved using the most appropriate Model of Computation (MoC). In this paper, we present a new generic MoC-independent elaboration scheme that aims at preparing a Virtual Prototype (VP) for simulation. It requires to check the correct composition of the system model through dimensional analysis, to explore the model structure to identify involved MoC and interfaces between MoCs, and to detect the underlying dependencies. Eventually, information extracted from the exploration allow the instantiation of MoC-specific solvers. To soundly handle the global model execution with a Discrete Event (DE) kernel as the main solver, synchronization mechanisms with master-slave semantics within the model structure are implicitly deduced. © 2015 IEEE.

关键词： Virtual prototyping

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A hardware accelerated configurable ASIP architecture for embedded real-time video-based driver assistance applications

A hardware accelerated configurable ASIP architecture for em...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Schewior, Gregor Flatt, Holger Dolar, Carsten Banz, Christian Blume, Holger Leibniz Universität Hannover Institute of Microelectronic Systems Appelstr. 4 30167 Hannover Germany

ISBN: (纸本)9781457708008

In this paper, a flexible HW architecture for video-based driver assistance applications is presented. It comprises a customizable and extensible processor template and several task-specific HW accelerators. The proposed heterogeneous architecture allows utilization of the programmable processor core for control and low data rate tasks. For the acceleration of computationally intensive tasks of the application, special functional units and custom instructions can be added to the processor template to form an application specific instruction set processor (ASIP). Moreover, dedicated HW accelerators can be attached to the ASIP. To compare the diverse design options, a shape detection application for traffic sign detection is utilized as case study. It is shown that single tasks of a pure software implementation can be significantly accelerated by usage of special functional units by a factor of up to 35 and by usage of HW accelerators of up to 243. The proposed architecture has been mapped onto an FPGA and it could be shown that a realtime capable system can be realized. © 2011 IEEE.

关键词： Automobile drivers

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