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Towards modeling Cyber-Physical systems with SysML/MARTE/pCCSL 42

Towards Modeling Cyber-Physical Systems with SysML/MARTE/pCC...

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42nd Annual IEEE-computer-Society computers, Software and Applications (COMPSAC) conference - Staying Smarter in a Smartening World

作者： Huang, Ping Jiang, Kaiqiang Guan, Chunlin Du, Dehui East China Normal Univ Shanghai Key Lab Trustworthy Comp Shanghai 200062 Peoples R China

ISBN: (纸本)9781538626672

Cyber-Physical systems (CPS) are networks of heterogeneous embedded systems immersed within a physical environment. modeling such heterogeneous systems is actively researched. However, there still lacks a systematic approach to model characteristics of CPS. To solve the problem, we propose a flexible co-modeling approach that relies on SysML/MARTE/pCCSL to capture different aspects of CPS, including structure, behavior, clock constraints and NFP. The novelty of our approach lies in the use of logical clocks and SysML/MARTE/pCCSL to drive and coordinate different models, which supports a standard language-based modeling for CPS. To capture the characteristics of CPS such as stochastic behavior and continuous behavior, we extend some meta-models of SysML/MARTE. For the block diagram, we extend it with four new stereotypes of blocks and the type of model. We adopt a new stereotype FMIConnection to describe the information transmission between blocks, which denotes that the blocks will be exported as corresponding FMU components. It will be of great benefit to the co-simulation of CPS. For the state machine diagram, we attach Ordinary Differential Equation (ODE) and TimedDelay to a state, which models the continuous behavior and stochastic time delay. The consistency between various models is specified with pCCSL. To implement our approach, we develop the toolset based on GEMOC. Finally, to demonstrate the feasibility of our co-modeling approach, we present some multi-view models of an energy-aware building as a case study.

关键词： CPS SysML/MARTE co-modeling meta-models GEMOC energy-aware building

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Sub-Word Parallel Precision-Scalable MAC Engines for Efficient embedded DNN Inference

Sub-Word Parallel Precision-Scalable MAC Engines for Efficie...

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IEEE international conference on Artificial Intelligence Circuits and systems (AICAS)

作者： Linyan Mei Mohit Dandekar Dimitrios Rodopoulos Jeremy Constantin Peter Debacker Rudy Lauwereins Marian Verhelst Dept. of Electrical Engineering MICAS KU Leuven Belgium imec Belgium

ISBN: (纸本)9781538678855

To enable energy-efficient embedded execution of Deep Neural Networks (DNNs), the critical sections of these workloads, their multiply-accumulate (MAC) operations, need to be carefully optimized. The SotA pursues this through run-time precision-scalable MAC operators, which can support the varying precision needs of DNNs in an energy-efficient way. Yet, to implement the adaptable precision MAC operation, most SotA solutions rely on separately optimized low precision multipliers and a precision-variable accumulation scheme, with the possible disadvantages of a high control complexity and degraded throughput. This paper, first optimizes one of the most effective SotA techniques to support fully-connected DNN layers. This mode, exploiting the transformation of a high precision multiplier into independent parallel low-precision multipliers, will be called the Sum Separate (SS) mode. In addition, this work suggests an alternative low-precision scheme, i.e. the implicit accumulation of multiple low precision products within the multiplier itself, called the Sum Together (ST) mode. Based on the two types of MAC arrangements explored, corresponding architectures have been proposed to implement DNN processing. The two architectures, yielding the same throughput, are compared in different working precisions (2/4/8/16-bit), based on Post-Synthesis simulation. The result shows that the proposed ST-Mode based architecture outperforms the earlier SS-Mode by up to ×1.6 on Energy Efficiency (TOPS/W) and ×1.5 on Area Efficiency (GOPS/mm 2 ).

关键词： Engines computer architecture Throughput Neural networks Registers Bandwidth Complexity theory

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Performance-Oriented Neural Architecture Search

Performance-Oriented Neural Architecture Search

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international conference on High Performance Computing & simulation (HPCS)

作者： Andrew Anderson Jing Su Rozenn Dahyot David Gregg School of Computer Science and Statistics Trinity College Dublin Dublin Ireland

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

Hardware-Software Co-Design is a highly successful strategy for improving performance of domain-specific computing systems. We argue for the application of the same methodology to deep learning; specifically, we propose to extend neural architecture search with information about the hardware to ensure that the model designs produced are highly efficient in addition to the typical criteria around accuracy. Using the task of keyword spotting in audio on edge computing devices, we demonstrate that our approach results in neural architecture that is not only highly accurate, but also efficiently mapped to the computing platform which will perform the inference. Using our modified neural architecture search, we demonstrate 0.88% increase in TOP-1 accuracy with 1.85× reduction in latency for keyword spotting in audio on an embedded SoC, and 1.59× on a high-end GPU.

关键词： computer architecture Convolution Computational modeling Neural networks Quantization (signal) Space exploration Machine learning

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Evaluating the impact of spiking neural network traffic on extreme-scale hybrid systems

Evaluating the impact of spiking neural network traffic on e...

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2018 IEEE/ACM Performance modeling, Benchmarking and simulation of High Performance computer systems, PMBS 2018

作者： Wolfe, Noah Plagge, Mark Carothers, Christopher D. Mubarak, Misbah Ross, Robert B. Department of Computer Science Rensselaer Polytechnic Institute United States Argonne National Laboratory Mathematics and Computer Science United States

ISBN: (纸本)9781728101828

As we approach the limits of Moore's law, there is increasing interest in non-Von Neuman architectures such as neuromorphic computing to take advantage of improved compute and low power capabilities. Spiking neural network (SNN) applications have so far shown very promising results running on a number of processors, motivating the desire to scale to even larger systems having hundreds and even thousands of neuromorphic processors. Since these architectures currently do not exist in large configurations, we use simulation to scale real neuromorphic applications running on a single neuromorphic chip, to thousands of chips in an HPC class system. Furthermore, we use a novel simulation workflow to perform a full scale systems analysis of network performance and the interaction of neuromorphic workloads with traditional CPU workloads in a hybrid supercomputer environment. On average, we find Slim Fly, Fat-Tree, Dragonfly-lD, and Dragonfly-2D are 45 %, 46 %, 76 %, and 83 % respectively faster than the worst case performing topology for both convolutional and Hopfield NN workloads running alongside CPU workloads. Running in parallel with CPU workloads translates to an average slowdown of 21 % for a Hopfield type workload and 184 % for convolutional NN workloads across all HPC network topologies. © 2018 IEEE.

关键词： Supercomputers

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Approximating Memory-bound Applications on Mobile GPUs

Approximating Memory-bound Applications on Mobile GPUs

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international conference on High Performance Computing & simulation (HPCS)

作者： Daniel Maier Nadjib Mammeri Biagio Cosenza Ben Juurlink Technische Universität Berlin Germany

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

Approximate computing techniques are often used to improve the performance of applications that can tolerate some amount of impurity in the calculations or data. In the context of embedded and mobile systems, a broad number of applications have exploited approximation techniques to improve performance and overcome the limited capabilities of the hardware. On such systems, even small performance improvements can be sufficient to meet scheduled requirements such as hard real-time deadlines. We study the approximation of memory-bound applications on mobile GPUs using kernel perforation, an approximation technique that exploits the availability of fast GPU local memory to provide high performance with more accurate results. Using this approximation technique, we approximated six applications and evaluated them on two mobile GPU architectures with very different memory layouts: a Qualcomm Adreno 506 and an ARM Mali T860 MP2. Results show that, even when the local memory is not mapped to dedicated fast memory in hardware, kernel perforation is still capable of 1.25× speedup because of improved memory layout and caching effects. Mobile GPUs with local memory show a speedup of up to 1.38×.

关键词： Kernel Graphics processing units Instruction sets computer architecture Hardware Image reconstruction Resilience

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Formal and virtual multi-level design space exploration 1

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5th international conference on Model-Driven Engineering and Software Development, MODELSWARD 2017

作者： Li, Letitia W. Genius, Daniela Apvrille, Ludovic Télécom ParisTech Université Paris-Saclay Biot France Sorbonne Universités UPMC Paris 06 LIP6 CNRS UMR 7606 Paris France Institut VEDECOM Versailles France

ISBN: (数字)9783319947648

ISBN: (纸本)9783319947631

With the growing complexity of embedded systems, a systematic design process and tool are vital to help designers assure that their design meets specifications. The design of an embedded system evolves through multiple modeling phases, with varying levels of abstraction. A modeling toolkit should also support the various evaluations needed at each stage, in the form of simulation, formal verification, and performance evaluation. This chapter introduces our model-based engineering process with the supporting toolkit TTool, with two main design stages occurring at a different level of abstraction. A system-level design space exploration selects the architecture and partitions functions into hardware and software. The subsequent software design phase then designs and assesses the detailed functionality of the system, and evaluates the partitioning choices. We illustrate the design phases and supported evaluations with a Smart Card case study. © Springer international Publishing AG, part of Springer Nature 2018.

关键词： embedded systems

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Edge and Fog Computing Enabled AI for IoT-An Overview

Edge and Fog Computing Enabled AI for IoT-An Overview

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IEEE international conference on Artificial Intelligence Circuits and systems (AICAS)

作者： Zhuo Zou Yi Jin Paavo Nevalainen Yuxiang Huan Jukka Heikkonen Tomi Westerlund Fudan University Shanghai China Dept. of Future Technologies University of Turku Turku Finland

ISBN: (纸本)9781538678855

In recent years, Artificial Intelligence (AI) has been widely deployed in a variety of business sectors and industries, yielding numbers of revolutionary applications and services that are primarily driven by high-performance computation and storage facilities in the cloud. On the other hand, embedding intelligence into edge devices is highly demanded by emerging applications such as autonomous systems, human-machine interactions, and the Internet of Things (IoT). In these applications, it is advantageous to process data near or at the source of data to improve energy & spectrum efficiency and security, and decrease latency. Although the computation capability of edge devices has increased tremendously during the past decade, it is still challenging to perform sophisticated AI algorithms in these resource-constrained edge devices, which calls for not only low-power chips for energy efficient processing at the edge but also a system-level framework to distribute resources and tasks along the edge-cloud continuum. In this overview, we summarize dedicated edge hardware for machine learning from embedded applications to sub-mW “always-on” IoT nodes. Recent advances of circuits and systems incorporating joint design of architectures and algorithms will be reviewed. Fog computing paradigm that enables processing at the edge while still offering the possibility to interact with the cloud will be covered, with focus on opportunities and challenges of exploiting fog computing in AI as a bridge between the edge device and the cloud.

关键词： Cloud computing Edge computing Artificial intelligence computer architecture Hardware Internet of Things Computational modeling

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8th international Workshop on Performance modeling, Benchmarking and simulation of High Performance Computing systems, PMBS 2017

8th International Workshop on Performance Modeling, Benchmar...

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8th international Workshop on Performance modeling, Benchmarking and simulation of High Performance Computing systems, PMBS 2017

ISBN: (纸本)9783319729701

The proceedings contain 13 papers. The special focus in this conference is on Performance modeling, Benchmarking and simulation of High Performance Computing systems. The topics include: Performance and energy usage of workloads on KNL and haswell architectures;A survey of application memory usage on a national supercomputer: An analysis of memory requirements on ARCHER;Comparison of parallelisation approaches, languages, and compilers for unstructured mesh algorithms on GPUs;periodic I/O scheduling for super-computers;A performance study of quantum ESPRESSO’s PWscf Code on multi-core and GPU systems;modeling large compute nodes with heterogeneous memories with cache-aware roofline model;A scalable analytical memory model for CPU performance prediction;modeling UGAL on the dragonfly topology;resilient N-body tree computations with algorithm-based focused recovery: Model and performance analysis;multi-fidelity Surrogate modeling for Application/Architecture Co-design.

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The impact of the AC922 Architecture on Performance of Deep Neural Network Training

The impact of the AC922 Architecture on Performance of Deep ...

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international conference on High Performance Computing & simulation (HPCS)

作者： Paweł Rościszewski Michał Iwański Paweł Czarnul Faculty of Electronics Telecommunications and Informatics Gdańsk University of Technology Poland IBM Systems IBM Poland

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

Practical deep learning applications require more and more computing power. New computing architectures emerge, specifically designed for the artificial intelligence applications, including the IBM Power System AC922. In this paper we confront an AC922 (8335-GTG) server equipped with 4 NVIDIA Volta V100 GPUs with selected deep neural network training applications, including four convolutional and one recurrent model. We report performance results depending on batch sizes and GPU selection and compare them with the results from another contemporary workstation based on the same set of GPUs - NVIDIA® DGX Station ™ . The results show that the AC922 performs better in all tested configurations, achieving improvements up to 10.3%. Profiling indicates that the improvement is due to the efficient I/O pipeline. The performance differences depend on the specific model, rather than on the model class (RNN/CNN). Both systems offer good scalability up to 4 GPUs. In certain cases there is a significant difference in performance depending on exactly which GPUs are used for computations.

关键词： Training Servers computer architecture Bandwidth Computational modeling Benchmark testing Machine learning

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Design Space Exploration of embedded Applications on Heterogeneous CPU-GPU Platforms

Design Space Exploration of Embedded Applications on Heterog...

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international conference on High Performance Computing & simulation (HPCS)

作者： Abdullah Siddiqui Gul N. Khan Electrical Computer and Biomedical Engineering Ryerson University Toronto Ontario Canada

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

CPU-GPU platforms possess the potential of enhancing the performance of applications through some unique and diverse capabilities of both CPU-GPU devices. As a result, the methodologies for CPU/GPU system design space exploration for various applications are now considerably more challenging on these heterogeneous platforms. In this paper, we present a heuristic algorithm for partitioning the computation of applications between a CPU and GPU, while satisfying the user-defined constraints. Our methodology leverages the SIMD-related computing and hierarchical memory model of GPUs to optimize application mapping and allocation to CPU-GPU systems. The algorithm partitions the application, which is specified as a Directed Acyclic Graph (DAG), for a CPU-GPU platform to meet the objectives specified by the user. The effectiveness of our methodology is demonstrated by efficiently partitioning and executing MJPEG decoder and benchmark applications on a CPU-GPU system.

关键词： Graphics processing units Task analysis Partitioning algorithms Genetic algorithms Computational modeling Resource management Parallel processing

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