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检索条件"任意字段=International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation"

共 2730 条记录，以下是341-350 订阅

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Fast and cycle-accurate simulation of multi-threaded applications on SMP architectures using hybrid prototyping 16

Fast and cycle-accurate simulation of multi-threaded applica...

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international conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS)

作者： Saboori, Ehsan Abdi, Samar Concordia Univ Montreal PQ Canada

ISBN: (纸本)9781450344838

This paper presents a fast and cycle accurate simulation environment for early power-performance analysis of multi-threaded applications targeted to symmetric multiprocessing embedded architectures. Our simulation environment leverages the hybrid prototyping technique, where a lightweight emulation kernel performs logical simulation of multiple identical cores on top of a single physical instance of a core. The technique does not require a detailed timing model of the core hardware because the application threads execute directly on the target core. Previous work on hybrid prototyping supported modeling of only statically scheduled threads, thereby severely limiting its modeling capabilities. In this work, we describe the modeling of dynamic RTOS scheduler as well as hardware interrupts on top of the emulation kernel, in order to support the simulation of unmodified multi-threaded applications. Our experimental results demonstrate the high accuracy, simulation speed and scalability of our hybrid prototyping-based simulation models.

关键词： Hybrid prototyping embedded systems Multicore design Rapid prototyping Symmetrical Multi Processor Virtual prototyping FPGA prototyping

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An embedded Hardware-Efficient Architecture for Real-Time Cascade Support Vector Machine Classification

An Embedded Hardware-Efficient Architecture for Real-Time Ca...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Kyrkou, Christos Theocharides, Theocharis Bouganis, Christos-Savvas Univ Cyprus KIOS Res Ctr Dept Elect & Comp Engn Nicosia Cyprus Univ London Imperial Coll Sci Technol & Med Dept Elect & Elect Engn London SW7 2AZ England

ISBN: (纸本)9781479901036

Support Vector Machines (SVMs) are considered as a state-of-the-art classification algorithm yielding high accuracy rates. However, SVMs often require processing a large number of support vectors, making the classification process computationally demanding, especially when considering embedded applications. Cascade SVMs have been proposed in an attempt to speed-up classification times, but improved performance comes at a cost of additional hardware resources. Consequently, in this paper we propose an optimized architecture for cascaded SVM processing, along with a hardware reduction method in order to reduce the overheads from the implementation of additional stages in the cascade, leading to significant resource and power savings for embedded applications. The architecture was implemented on a Virtex 5 FPGA platform and evaluated using face detection as the target application on 640x480 resolution images. Additionally, it was compared against implementations of the same cascade processing architecture but without using the reduction method, and a single parallel SVM classifier. The proposed architecture achieves an average performance of 70 frames-per-second, demonstrating a speed-up of 5x over the single parallel SVM classifier. Furthermore, the hardware reduction method results in the utilization of 43% less hardware resources and a 20% reduction in power, with only 0.7% reduction in classification accuracy.

关键词： Field Programmable Gate Arrays Support Vector Machines Cascade Classifier Real-time and embedded systems Parallel Architecture

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Software Fault Tolerance for FPUs via Vectorization 15

Software Fault Tolerance for FPUs via Vectorization

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Chen, Zhi Inagaki, Ryoichi Nicolau, Alexandru Veidenbaum, Alexander V. Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA

ISBN: (纸本)9781467373111

Future generation processors are expected to have high soft error rates and will require increased fault detection and fault tolerance. This work focuses on errors in execution units. Hardware or software duplication or triplication, parity, or residue codes could be used to detect errors in execution units. However, hardware duplication/triplication have significant area overhead and, in applications with high utilization of floating point units (FPU), very high energy cost. Software duplication/triplication of instructions also increases both execution time and energy consumption. This paper proposes to reduce the cost of redundant instruction execution in FPUs through vectorization. Duplicated or triplicated instructions and result comparisons can be packed by a compiler into vector instructions, such as SSE or AVX. Experimental results using hand vectorization on a variety of benchmarks show that, compared to error detection through scalar instruction duplication, vector mode redundant execution achieves 1.78x and 2.73x average speedup for SSE and AVX instructions, respectively. It also significantly reduces the energy consumption, by an average of 40% and 53%, respectively, for SSE and AVX. Thus the proposed technique enables error detection with no hardware cost and reduced time and energy overhead compared to brute-force scalar instruction duplication.

关键词： Streaming SIMD Extensions instruction Error detection energy consumption instruction execute software fault tolerance residue codes Replication Legal Executions compilers computer hardware Error analysis Fault tolerance execution time Defect detection

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Mining dynamic document spaces with massively parallel embedded processors

Mining dynamic document spaces with massively parallel embed...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Jacobs, Jan W. M. Dai, Rui Smit, Gerard J. M. Oce Technol BV NL-5900 MA Venlo Netherlands Natl Univ Singapore Design Technol Inst Fac Engn Singapore 119260 Singapore Univ Twente NL-7500 AE Enschede Netherlands

ISBN: (纸本)3540364102

Currently Oce investigates future document management services. One of these services is accessing dynamic document spaces, i.e. improving the access to document spaces which are frequently updated (like newsgroups). This process is rather computational intensive. This paper describes the research conducted on software development for massively parallel processors. A prototype has been built which processes streams of information from specified newsgroups and transforms them into personal information maps. Although this technology does speed up the training part compared to a general purpose processor implementation its real benefits emerges with larger problem dimensions because of the scalable approach.

关键词： Program processors

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An optimization methodology for memory allocation and task scheduling in SoCs via linear programming

An optimization methodology for memory allocation and task s...

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Ristau, Bastian Fettweis, Gerhard Tech Univ Dresden Vodafone Chair Mobile Commun Syst D-01062 Dresden Germany

ISBN: (纸本)3540364102

Applications for system on chips become more and more complex. Also the number of available components (DSPs, ASICs, Memories, etc.) rises continuously. These facts necessitate a structured method for selecting components, mapping applications and evaluating the chosen configuration and mapping. In this work we present a methodology for the last named. We will consider optimization of memory allocation and task scheduling as a packing problem and minimize needed memory area. The results can be used as one element of an automated performance analysis for a given system on a high abstraction level. This analysis is essential for establishing a framework that iterates over a large quantity of possible systems. Considering a part of the H.264 codec as an example we will illustrate the results. Furthermore we will show that results can be retrieved fast compared to other NP-hard problems due to intelligent formulation of conditions within the linear program.

关键词： Storage allocation (computer)

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High level quantitative hardware prediction modeling using statistical methods

High level quantitative hardware prediction modeling using s...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Meeuws, Roel Galuzzi, Carlo Bertels, Koen Computer Engineering Lab Delft University of Technology Netherlands

ISBN: (纸本)9781457708008

With the increasing proliferation of heterogeneous and reconfigurable computing, it has become essential to have efficient prediction models to drive early HW-SW partitioning and co-design. In this paper, we present a high level quantitative prediction modeling approach that accurately models the relation between hardware and software metrics, based on several statistical techniques. The proposed approach generates models that predict hardware performance indicators for reconfigurable components, such as the number of slices, the number of flip-flops, and the number of wires. It utilizes automatic model selection, artificial neural networks, (logistic) regression, and data transformations. These models take a high-level language description as input, enabling hardware prediction in the early design stages. We calibrate the models for two sets of tools targeting Xilinx and Altera FPGAs, where we report, for example, and error of 14% for the number of multipliers in case of Xilinx and an error of only 18% for the number of wires in case of Altera. To provide a realistic evaluation, we validate the approach using 181 kernels, contrary to the majority of the existing techniques, which use libraries of tens of kernels at most. © 2011 IEEE.

关键词： Forecasting

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modeling the Temperature Bias of Power Consumption for Nanometer-Scale CPUs in Application Processors 14

Modeling the Temperature Bias of Power Consumption for Nanom...

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international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： De Vogeleer, Karel Memmi, Gerard Jouvelot, Pierre Coelho, Fabien TELECOM ParisTech INFRES CNRS LTCI UMR 5141 Paris France MINES ParisTech Paris France

ISBN: (纸本)9781479937707

We introduce and experimentally validate a new macro-level model of the CPU temperature/power relationship within nanometer-scale application processors or system-onchips. By adopting a holistic view, this model is able to take into account many of the physical effects that occur within such systems. Together with two algorithms described in the paper, our results can be used, for instance by engineers designing power or thermal management units, to cancel the temperature-induced bias on power measurements. This will help them gather temperature-neutral power data while running multiple instance of their benchmarks. Also power requirements and system failure rates can be decreased by controlling the CPU's thermal behavior. Even though it is usually assumed that the temperature/power relationship is exponentially related, there is however a lack of publicly available physical temperature/power measurements to back up this assumption, something our paper corrects. Via measurements on two pertinent platforms sporting nanometer-scale application processors, we show that the power/temperature relationship is indeed very likely exponential over a 20 degrees C to 85 degrees C temperature range. Our data suggest that, for application processors operating between 20 degrees C and 50 degrees C, a quadratic model is still accurate and a linear approximation is acceptable.

关键词： central processing units PROCESSOR Power consumption Power measurement Linear approximation Bias Bias Bias Statistical Biases bias(electronics)

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Reducing execution unit leakage power in embedded processors

Reducing execution unit leakage power in embedded processors

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6th international Workshop on embedded computer systems - architectures, modeling and simulation

作者： Homayoun, Houman Baniasadi, Amirali Univ Victoria Dept Elect & Comp Engn Victoria BC Canada

ISBN: (纸本)3540364102

We introduce low-overhead power optimization techniques to reduce leakage power in embedded processors. Our techniques improve previous work by a) taking into account idle time distribution for different execution units, and b) using instruction decode and control dependencies to wakeup the gated (but needed) units as soon as possible. We take into account idle time distribution per execution unit to detect an idle time period as soon as possible. This in turn results in increasing our leakage power savings. In addition, we use information already available in the processor to predict when a gated execution unit will be needed again. This results in early and less costly reactivation of gated execution units. We evaluate our techniques for a representative subset of MiBench benchmarks and for a processor using a configuration similar to Intels Xscale processor. We show that our techniques reduce leakage power considerably while maintaining performance.

关键词： Program processors

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A Reliable and Fast ANN Based Behavioral modeling Approach for GaN HEMT 16

A Reliable and Fast ANN Based Behavioral Modeling Approach f...

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16th international conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit Design (SMACD) / 15th conference on PhD Research in Microelectronics and Electronics (PRIME)

作者： Khusro, Ahmad Husain, Saddam Hashmi, Mohammad S. Auyenur, Medet Ansari, Abdul Quaiyum Jamia Millia Islamia Dept Elect Engn New Delhi India Nazarbayev Univ Dept Elect & Comp Engn Astana Kazakhstan

ISBN: (纸本)9781728112015

The paper proposes an accurate, fast and advanced neural network approach to model the small signal behavior of GaN High Electron Mobility Transistor (HEMT). The presented approach makes use of the nonlinear autoregressive series-parallel and parallel architectures to model a 2x200 mu m device for a broad frequency range of 1GHz - 18GHz. A comparison is drawn between the two architectures based on the training algorithm, accuracy, convergence rate and number of epochs. An excellent agreement is found between the measured S-parameters and the proposed model for the complete broad frequency range. The proposed model can be embedded into computer aided design tool for an accurate and expedited design process of RF/microwave circuits and systems.

关键词： GaN HEMT NARX architecture modeling Machine Learning

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Towards Future Adaptive Multiprocessor systems-On-Chip: an Innovative Approach for Flexible architectures

Towards Future Adaptive Multiprocessor Systems-On-Chip: an I...

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international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Lemonnier, Fabrice Millet, Philippe Almeida, Gabriel Marchesan Huebner, Michael Becker, Juergen Pillement, Sebastien Sentieys, Olivier Koedam, Martijn Sinha, Shubhendu Goossens, Kees Piguet, Christian Morgan, Marc-Nicolas Lemaire, Romain Thales Res & Technol 1 Ave Augustin Fresnel F-91767 Palaiseau France Karlsruhe Inst Technol KIT Inst Informat Proc Technol D-76131 Karlsruhe Germany Ruhr Univ Bochum Embedded Syst Informat Technol D-44801 Bochum Germany Univ Rennes IRISA F-22300 Lannion France Eindhoven Univ Technol Eindhoven Netherlands Ctr Suisse Elect & microtechn SA CSEM Neuchatel Switzerland CEA Leti Grenoble France

ISBN: (纸本)9781467322973;9781467322966

This paper introduces adaptive techniques targeted for heterogeneous manycore architectures and introduces the FlexTiles platform, which consists of general purpose processors with some dedicated accelerators. The different components are based on low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. These features enable a breakthrough in term of computing performance while improving the on-line adaptive capabilities brought from smart heuristics. Thus, we propose a virtualisation layer which provides a higher abstraction level to mask the underlying heterogeneity present in such architectures. Given the large variety of possible use cases that these platforms must support and the resulting workload variability, offline approaches are no longer sufficient because they do not allow coping with time changing workloads. The upcoming generation of applications include smart cameras, drones, and cognitive radio. In order to facilitate the architecture adaptation under different scenarios, we propose a programming model that considers both static and dynamic behaviors. This is associated with self adaptive strategies endowed by an operating system kernel that provides a set of functions that guarantee quality of service (QoS) by implementing runtime adaptive policies. Dynamic adaptation will be mainly used to reduce both overall power consumption and temperature and to ease the problem of decreasing yield and reliability that results from submicron CMOS scales.

关键词： ARCHITECTURE Self tuning operating system kernels computational performance system-on-chip Platform Cognitive radio Runtime Multiprocessor Quality of service Workload

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