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A Multi-agent simulation for the Research on the Market Equilibrium Phenomena Using Q-Network Algorithm

A Multi-agent Simulation for the Research on the Market Equi...

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international conference on Communication Technology (ICCT)

作者： Jinyan Wang Bo Chen College of Mathematics and Computer Science Fuzhou University Fuzhou Fujian Province China

For the problems related to market equilibrium in complex market environments, analyses are conducted in the past, using some mathematical models and the game theory. These methods are based on the economic structural equations themselves, ignoring the interactions between economic subjects, and the hypothesis of subject homogeneity has no reference in the real world. On contrast, this paper proposes a multi-agent simulation model, from the microscopic point of view. In such simulation, agents interact with each other, and the decisions are made by agent-embedded AI systems, the Q-network. Therefore, there is no need to elaborate the behavioral rule for each agent, or manually set up too many assumptions. This paper assumes that the simulated market operates in a hypothetical way, in which there are two types of economic entities, namely, banks and enterprises. Banks and enterprises lending behaviors lead to a symbiotic relationship between the banks and the enterprises, while business-to-business transactions make the enterprises symbiotically compete with each other. In the experiment, the observed behavior of each agent can be reasonably explained. Agents endogenously generate intelligent behavioral patterns compatible with the environment. Therefore, this AI-based method can replace the artificially designated decision-making strategy in simulations of market, thus facilitating related economic researches.

关键词： Economics Mathematical model Companies Decision making Markov processes Training Computational modeling

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Hiding Side-channel Leakage through Hardware Randomization: a Comprehensive Overview 17

Hiding Side-channel Leakage through Hardware Randomization: ...

引用

17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Mentens, Nele Katholieke Univ Leuven IMEC COSIC Kasteelpark Arenberg 10 B-3001 Leuven Belgium

ISBN: (纸本)9781538634370

This paper gives (i) an overview of the reconfiguration capabilities of modern hardware devices and (ii) a summary and comparison of hardware architectures that use random reconfiguration as a countermeasure against side-channel attacks. We categorize the architectures according to their suitability for specic hardware platforms. Further, we compare the reconfiguration methods and the attacks that the countermeasures protect against. Although the presented randomization countermeasures can usually be applied to a broad range of algorithms, evaluation results are presented for specific cryptographic algorithms. In most cases, randomization countermeasures can be combined with other countermeasures that are tailored to specific algorithms.

关键词： Field programmable gate arrays Hardware Table lookup Cryptography Power demand Registers Field programmable gate arrays Table lookup computer hardware Power demand Registers cryptography Randomisation Reconfiguration channel leak Hardware Platform ARCHITECTURE

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Translation Validation of Code Generation from the SIGNAL Data-Flow Language to Verilog

Translation Validation of Code Generation from the SIGNAL Da...

引用

international conference on Semantics, Knowledge and Grid (SKG)

作者： Hafiz Muhammad Amjad Kai Hu Jianwei Niu Noor Khan Loïc Besnard Jean-Pierre Talpin School of Computer Science & Engineering Beihang University Beijing China IRISA Rennes France INRIA Campus de Beaulieu Rennes France

ISBN: (数字)9781728158235

ISBN: (纸本)9781728158242

The SIGNAL is a high-level synchronous data-flow language for the design and implementation of safety-critical embedded systems. It provides a unified framework for specification, modeling, formal analysis, and automatic code generation for different general-purpose languages like Java, C, and C++. However, fully implemented and verified open source tool for code generation from SIGNAL to Hardware Description Language (HDL) is not available. This paper describes the formal verification of the generated Verilog code from the SIGNAL language. Proving the correctness of generated code is very important when it is for safety-critical embedded systems. We use the translation validation technique for verifying the correctness of the generated code. In this approach, the Polychrony Toolset builds the models of source SIGNALprograms with its associated model checker SIGALI. The open source tool Yosys generates models for target Verilog programs in the SMT-LIB standard format. We transform the model generated by Yosys to the model accepted by the SIGALI model checker. Finally, we use the SIGALI model checker to validate the translation by symbolic simulation between both source and target program models. The target program may have fewer behaviors than the source program therefore if the model of the target program implies the model of the source program, it means the target program preserves the semantics of the source program, and the translation is correct.

关键词： Hardware design languages Mathematical model Clocks Semantics Tools embedded systems Encoding

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modeling Traffic Workloads in Data-center Network simulation Tools

Modeling Traffic Workloads in Data-center Network Simulation...

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international conference on High Performance Computing & simulation (HPCS)

作者： Luis Gonzalez-Naharro Jesus Escudero-Sahuquillo Pedro J. García Francisco J. Quiles Jose Duato Wenhao Sun Xiang Yu Hewen Zheng Department of Computing Systems University of Castilla-La Mancha Spain Universitat Politècnica de València Spain Huawei Technologies Co. Ltd. China

ISBN: (数字)9781728144849

ISBN: (纸本)9781728144856

POSTER PAPER Data-centers are commonly used by most important cloud providers worldwide in order to provide storage and computing resources, and, based on these resources, advanced IT services and applications. With the expected explosion of data in the next few years, Data-centers will require new architectures to cope with the new requirements of applications and users. One of the crucial subsystems within the Data-center architecture that must evolve accordingly to the new requirements is the interconnection network or Data-center network (DCN). The DCN performance (basically, high communication bandwidth and low latency) must be guaranteed, otherwise the DCN becoming the system bottleneck. There are several key issues that DCN designers must make decisions on, such as the network topology, routing algorithm, congestion management, etc. An important aspect that impacts on the DCN design are the network communication patterns generated by applications and services. In that sense, an accurate modeling of these traffic workloads would help network designers to make better decisions. In this paper, we present an analysis of the few available studies on traffic modeling for DCNs, in order to gather a set of parameters that define the behaviour of common traffic workloads. Based on these parameters, we have implemented a synthetic DCN traffic generator, which has been included in our simulation framework in order to feed the network with the inferred traffic workloads. We have conducted extensive simulations to test the impact of the parameter variation on the network performance. From the obtained results, we can conclude that the destination distribution is crucial for the network performance. Higher oversubscription of destinations generates incast scenarios that lead to congestion situations and head-of-line blocking, affecting other flows that do not contribute to the incast situation and so spoiling the network performance.

关键词： Facebook computer architecture Bandwidth Analytical models Web servers Load modeling

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SysRT: A Modular Multiprocessor RTOS Simulator for Early Design Space Exploration 17

SysRT: A Modular Multiprocessor RTOS Simulator for Early Des...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Xiao, Jun Pimentel, Andy Lipari, Giuseppe Univ Amsterdam Amsterdam Netherlands Univ Lille Lille France

ISBN: (纸本)9781538634370

Modern embedded systems increasingly accommodate several applications running concurrently on a multiprocessor platform managed by a real-time operating system (RTOS). The increasing design complexity of such systems calls for good design tools to evaluate real-time performance during the very early stages of design. To this end, fast system-level simulators that allow for efficient hardware/software co-simulation are essential. In this paper, we present SysRT, a generic and high-level RTOS simulator that is highly suited for early design space exploration (DSE). The simulator contains different types of application models and a modular RTOS kernel model, all developed in SystemC. Efficient and precise modeling of preemptive scheduling is achieved via an event-driven simulation approach, allowing simulations to be performed much faster than cycle-accurate simulations. At the same time, the kernel model is developed to be generic and modular to support for easy plug-in of new schedulers as well as new resource sharing protocols. Comparing SysRT with state-of-art simulators, it achieves faster simulation speeds with an identically small simulation error. We demonstrate the flexibility of SysRT and its benefits for early DSE using experiments with a mixed workload executing on multiprocessor platforms with different numbers of cores.

关键词： Task analysis Kernel Real-time systems Unified modeling language computer architecture Timing Computational modeling UML task analysis computer Architecture real-time systems Computational modeling Space Exploration simulator Kernel Modularity Multiprocessor Seeds analog error

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Run-time Mapping Algorithm for Dynamic Workloads using Process Merging Transformations 17

Run-time Mapping Algorithm for Dynamic Workloads using Proce...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sinaei, Sima Fatemi, Omid Pimentel, Andy D. Univ Tehran Tehran Elect & Comp Dept Tehran Iran Univ Amsterdam Informat Inst Amsterdam Netherlands

ISBN: (纸本)9781538634370

Exploration of task mappings has an important role to achieve high performance in heterogeneous multi-processor system-on-chip (MPSoC) platforms. The application workloads in modern MPSoC-based embedded systems are becoming increasingly dynamic. Different applications concurrently execute and contend for resources in such systems. In this paper, a run-time algorithm is proposed to analytically evaluate the system throughput of to-be-executed applications (modelled as Kahn Process Networks, KPNs) in order to quickly determine a proper resource binding for these applications. Merging transformations on the KPNs are applied to capture the cases in which the number of processes in the KPN is larger than the number of available processing resources, thereby modeling the effects of binding multiple processes to a single processor. We evaluated our algorithm using a heterogeneous MPSoC system with several applications. Our experimental results revealed that during runtime, the performance of selected mapping with regard to available resources is close to the optimal performance obtained by exhaustive search and simulation. Therefore, the results clearly confirm that our algorithm is effective.

关键词： embedded systems multiprocessor-systems-on-chip (MPSoCs) run-time mapping design space exploration of heterogeneous MPSoCs process merging performance evaluation

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Exploring Different Execution Paradigms in Exposed Datapath architectures with Buffered Processing Units 17

Exploring Different Execution Paradigms in Exposed Datapath ...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Bhagyanath, Anoop Schneider, Klaus Univ Kaiserslautern Dept Comp Sci Kaiserslautern Germany

ISBN: (纸本)9781538634370

Exposed datapath processor architectures allow the software to bypass register usage by directly moving intermediate results between processing units with suitable instructions. Synchronous Control Asynchronous Dataflow (SCAD) is a new exposed datapath architecture consisting of a grid of processing units with buffers to store their input and output values. Code generation inspired from queue machines can utilize the bypassing capability of such exposed datapath architectures with buffered processing units and can completely eliminate the use of registers this way. In this paper, we consider different execution paradigms of SCAD that make a compromise between hardware complexity, hardware scalability, and the use of instruction-level parallelism. To that end, we study both resource- and time-optimal code for all variants that we determine by satisfiability modulo theories (SMT) solvers. Experimental results show that the execution paradigm followed by our original SCAD architecture makes a reasonable compromise between hardware complexity and the use of instruction-level parallelism while maintaining hardware scalability.

关键词： computer architecture Registers Buffer storage Hardware Scalability Encoding Complexity theory Registers computer hardware BUFFER STORAGE Scalability computer Architecture Complexity theory instruction-level parallelism ARCHITECTURE Legal Executions

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Extraction of Recursion Level Parallelism for embedded Multicore systems 17

Extraction of Recursion Level Parallelism for Embedded Multi...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Aguilar, Miguel Angel Leupers, Rainer Ascheid, Gerd Eusse, Juan Fernando Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silex GmbH Herne Germany

ISBN: (纸本)9781538634370

Recursive programs that typically implement divide-and-conquer algorithms are well-suited for multicore systems, as they offer a high degree of parallelization potential. So far, existing parallelizing compilers have mainly focused on extracting other parallel patterns, such as data or pipeline level parallelism. In this paper, we propose a toolflow for the extraction of recursion level parallelism for embedded multicore systems. To achieve this, the toolflow verifies not only the mutual independence of recursive call-sites, but also selects an appropriate task granularity to ensure a good trade-off between load balancing and parallelization overhead. Profitable parallelization opportunities are implemented by using compiler directives from the OpenMP tasking model. Results show the effectiveness of our toolflow, as it is able to speedup sequential recursive programs between 2.5x and 3.8x on a quad-core platform.

关键词： Task analysis Multicore processing Parallel processing Analytical models Performance analysis Static analysis Load management task analysis load management PARALLEL PROCESSING (computerS) ANALYSIS MODELS Multi-core processors parallelism Synclitism Recursion Recursive Procedure parallelizing compilers parallelization

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A New State Model for DRAMs Using Petri Nets 17

A New State Model for DRAMs Using Petri Nets

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Jung, Matthias Kraft, Kira Wehn, Norbert Fraunhofer IESE D-67663 Kaiserslautern Germany Univ Kaiserslautern D-67663 Kaiserslautern Germany

ISBN: (纸本)9781538634370

The functionality of DRAMs, especially the state transitions are described in JEDEC standards. These standards contain a finite state machine, which intends to provide an overview of the possible state transitions and the commands to control them. However, today's DRAMs are highly concurrent devices as they provide bank parallelism. The state diagram used in JEDEC standards does not model this concurrency and furthermore it is misleading in several aspects. In this paper, for the first time we present an easily comprehensive model of the DRAM states and transitions, using a Petri Net, which covers also the DRAM concurrency.

关键词： Random access memory Petri nets Inhibitors Standards Parallel processing computer architecture Concurrent computing Petri nets random access machine computer Architecture PARALLEL PROCESSING (computerS) Parallel programming DRAM1 gene Inhibitors Joint Electron Device Engineering Council State Change finite state machines

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System simulation with gem5 and SystemC The Keystone for Full Interoperability 17

System Simulation with gem5 and SystemC The Keystone for Ful...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Menard, Christian Castrillon, Jeronimo Jung, Matthias Wehn, Norbert Tech Univ Dresden Dresden Germany Fraunhofer IESE Kaiserslautern Germany Univ Kaiserslautern Kaiserslautern Germany

ISBN: (纸本)9781538634370

SystemC TLM based virtual prototypes have become the main tool in industry and research for concurrent hardware and software development, as well as hardware design space exploration. However, there exists a lack of accurate, free, changeable and realistic SystemC models of modern CPUs. Therefore, many researchers use the cycle accurate open source system simulator gem5, which has been developed in parallel to the SystemC standard. In this paper we present a coupling of gem5 with SystemC that offers full interoperability between both simulation frameworks, and therefore enables a huge set of possibilities for system level design space exploration. Furthermore, we show that the coupling itself only induces a relatively small overhead to the total execution time of the simulation.

关键词： Time-varying systems Time-domain analysis Couplings Timing Protocols Hardware Industries Time domain analysis Couplings time-varying systems computer hardware execution time systems simulation protocols industries coupling Interoperability Space Exploration keystone

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