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Editor’s Note: Special Issue on embedded computer systems: architectures, modeling and simulation

international Journal of Parallel Programming 2018年第6期46卷 1184-1184页

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Agent and Multi-Agent systems: Technology and Applications 10th KES international conference, KES-AMSTA 2016 Puerto de la Cruz, Tenerife, Spain, June ...

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2018年

作者： Gordan Ježić Yun Heh Jessica Chen-Burger Robert J Howlett Lakhmi C Jain

ISBN: (纸本)9783319819884

The modern economy is driven by technologies and knowledge. Digital technologies can free, shift and multiply choices, often intruding on the space of other industries, by providing new ways of conducting business operations and creating values for customers and companies. The topics covered in this volume include software agents, multi-agent systems, agent modelling, mobile and cloud computing, big data analysis, business intelligence, artificial intelligence, social systems, computer embedded systems and nature inspired manufacturing, etc. that contribute to the modern Digital Economy. This volume highlights new trends and challenges in agent, new digital and knowledge economy research and includes 28 papers classified in the following specific topics: business process management, agent-based modeling and simulation, anthropic-oriented computing, learning paradigms, business informatics and gaming, digital economy, and advances in networked virtual enterprises. Published papers were selected for presentation at the 10th KES conference on Agent and Multi-Agent systems: Technologies and Applications (KES-AMSTA 2016) held in Puerto de la Cruz, Tenerife, Spain. Presented results would be of theoretical and practical value to researchers and industrial practitioners working in the fields of artificial intelligence, collective computational intelligence, innovative business models, new digital and knowledge economy and, in particular, agent and multi-agent systems, technologies, tools and applications.

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Circuit and System Design Automation for Internet of Things

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IEEE TRANSACTIONS ON computer-AIDED DESIGN OF INTEGRATED CIRCUITS AND systems 2018年第1期37卷 3-6页

作者： Mohanty, Saraju P. Hueebner, Michael Xue, Chun Jason Li, Xin Li, Hai Univ North Texas Dept Comp Sci & Engn Denton TX 76203 USA Ruhr Univ Bochum Chair Embedded Syst Informat Technol Bochum Germany City Univ Hong Kong Dept Comp Sci Hong Kong Hong Kong Peoples R China Duke Univ Dept Elect & Comp Engn Durham NC USA

Internet-of-Things (IoT) is the technical backbone of smart cities which are envisioned to cope up with rapid urbanization of human population with limited resources. IoT provides three key features of smart cities such as intelligence, interconnection, and instrumentation. IoT is essentially a system-of-systems which can be considered as a configurable dynamic global network of networks. The main components of IoT include the following: 1) The Things; 2) Internet; 3) LAN; and 4) The Cloud. IoT is built by various diverse components including electronics, sensors, actuators, controllers, networks, firmware, and software. However, the existing electronics, controllers, and processors do not meet IoT requirements, such as multiple sensors, communication protocols, and security requirements. The existing computer-aided design (CAD) or electronic design automation tools are not enough to meet diverse challenges such as time-to-market, complexity, and cost of IoT. The required electronic circuits and systems need to be developed by handling and solving specific requirements. Real-time and ultralow power plays a major role since mobile devices in the IoT have to provide a long availability with a relative small energy budget. At the same time, reliability, availability, real-time constraints, and performance requirements pose significant challenges, and therefore, lead to a high interest in research. In this special issue, different approaches to design novel devices, circuits, and systems for solving the challenges with IoT are targeted. Various novel design automation components including modeling, design flows, simulation methods, and optimizations for designing of modern IoT are targeted, from system level down to device level. The current special issue was envisioned with the above technical considerations. After a rigorous review process, a set of articles were selected for this special issue. These papers are briefly discussed in the rest of the editorial.

关键词： Special issues and sections Internet of Things Design automation Smart buildings Smart cities

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Compressing 3D-CNNs for Hardware-Efficient Object Classification in Video Streams

Compressing 3D-CNNs for Hardware-Efficient Object Classifica...

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international conference on Signals and Electronic systems, ICSES

作者： Maciej Wielgosz Matej Mertik AGH University of Science and Technology Krakow Poland Alma Mater Europaea Maribor Slovenia

This paper presents a set of methods for effective compression of 3D-CNN deep learning architectures with a particular focus on embedded platforms. Deep learning models are massive regarding the number of parameters, especially in video processing. Such memory consumption poses a challenge when it comes to efficient deployment to embedded devices. The authors applied a series of quantization and pruning techniques and showed that it is possible to significantly reduce an 80M-parameters-large deep learning model with a negligible (approx. 1 perc.) decrease in accuracy.

关键词： Task analysis Quantization (signal) computer architecture Computational modeling Training Optimization

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Work-in-Progress: Impact of Graph Partitioning on SNN Placement for a Multi-Core Neuromorphic Architecture

Work-in-Progress: Impact of Graph Partitioning on SNN Placem...

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Proceedings of the international conference on Compilers, architectures and Synthesis for embedded systems (CASES)

作者： Francesco Barchi Gianvito Urgese Enrico Macii Andrea Acquaviva Department of Control and Computer Engineering Politecnico di Torino Italy

In this paper, we evaluate a partitioning and placement technique for mapping concurrent applications over a globally asynchronous locally synchronous (GALS) multi-core architecture designed for simulating a spiking neural network (SNN) in real-time. We designed a task placement pipeline capable of analysing the network of neurons and producing a placement configuration that enables a reduction of communication between computational nodes. The neuronto-core mapping problem has been formalised as a two phases problem: Partitioning and Placement. The Partitioning phase aims at grouping together the most connected network components, maximising the amount of self-connections within each identified group. For this purpose we used a multilevel k-way graph partitioning strategy capable of generating network-partitions. The Placement phase aims at placing groups of neurons over the chip mesh minimising the communication between computational nodes. For implementing this step, we designed and evaluate the performances of three placement variants. In the results, we point out the importance of using a partitioning algorithm for the SNN graph. We were able to achieve an increase in self-connections of 19% and an improvement of the final overall post-placement synaptic elongation of 29% using the simulated annealing placement technique, compared to 22% obtained without partitioning.

关键词： Neurons Sociology Statistics computer architecture Simulated annealing Program processors Brain modeling

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A Model-Based Concept for RTOS Portability

A Model-Based Concept for RTOS Portability

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ACS/IEEE international conference on computer systems and Applications

作者： Renata Martins Gomes Marcel Baunach Graz University of Technology Graz Austria

The amount and diversity of connected computing platforms in the Internet of Things (IoT) is expected to increase exponentially throughout the next years, together with their dependability requirements. This imposes many challenges to software and hardware developers and calls for safe and secure real-time operating systems (RTOSs) that are portable to different or changing hardware. Middleware ports, including RTOS ports, must keep functional and non-functional behavior constant towards the application. Current middleware portability approaches for embedded systems, however, are arduous and error prone. We present a novel approach towards portability of embedded RTOSs based on the formal, hardware-independent and detailed specification of RTOS kernels. With additional models of relevant MCU properties and instruction set architectures (ISA), we are able to generate low level RTOS code for different target architectures. This paper focuses on the hardware-independent model of the context switch within a multi-tasking RTOS. With the general approach, we expect to (1) reduce the effort for maintaining and porting RTOS code, as well as the (2) likeliness for errors, (3) make it easier to test new kernel concepts during OS development, (4) improve security by modeling different levels of access permissions for memory or peripherals depending on the execution mode, and (5) improve safety by formally proving the correctness and consistency of the models.

关键词： Kernel Hardware Task analysis computer architecture Internet of Things

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Work in Progress: An Confidentiality and Integrity Scheme for the Distributed Shared Memory of embedded Multi-core System

Work in Progress: An Confidentiality and Integrity Scheme fo...

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Proceedings of the international conference on Compilers, architectures and Synthesis for embedded systems (CASES)

作者： Pengfei Yang Quan Wang Xiaokun Huang Xin Mi School of Computer Science and Technology Xidian University Xi'an China

For the multi-core systems, the distributed shared memory(DSM) has become the mainstream for its scalability and portable. A new security policy needs to be designed to protect the data in the DSM. In this paper, a memory confidentiality protection method is designed based on the dynamic key and compression counter(CPS), The method improves the encryption efficiency significantly and solves the problem of the ciphertext re-encrypting when the counter overflows. A memory integrity protection method is proposed based on a multi-granularity incremental hash tree(MIT), to reduce the memory occupation and the amount of calculation. A secondary conversion method of the ciphertext is designed so that the data can be transmitted among the untrusted processing units without sharing the private keys. The optimized methods are quantitatively evaluated using the SimpleScalar architecture simulation tool. Experimental results show that the performance degradation of the proposed confidentiality protection method is 11.84% on average, which is better than the split counter mode(SPLIT) method and the block encryption method. The proposed integrity protection method has a 48.72% reduction in memory occupation and a 32.62% improvement in the performance reduction rate compared with the hash-tree method, it's better than the multi-grained hash tree(MGT) method and the Bonsai Merkle Tree(BMT) method too.

关键词： Encryption Memory management Indexes Micromechanical devices System-on-chip

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7th international Congress of Telematics and Computing, WITCOM 2018

7th International Congress of Telematics and Computing, WITC...

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7th international Congress of Telematics and Computing, WITCOM 2018

ISBN: (纸本)9783030037628

The proceedings contain 23 papers. The special focus in this conference is on Telematics and Computing. The topics include: Automatic fuzzy contrast enhancement using gaussian mixture models clustering;characterization of the serious games applied to the historical heritage;service architecture of systems immersed in internet of things paradigm;embedded system for the communication and monitoring of an electric microgrid using IoT;mobile system as a support in the study of calculus;implementation of personal information management architecture in mobile environments;software system for the analysis of mental stress in usability tests;proposal of a tool for the stimation of satisfaction in usability test under the approach of thinking aloud;exploration of serious games on environmental issues;security evaluation in wireless networks;recycling: A Serious game focused on the classification of waste;modeling a hazardous waste monitoring system with INGENIAS methodology;estimation of skill level in intelligent tutoring systems using a multi-attribute methodology;development serious games using agile methods. test case: Values and attitudinal skills;Microstrip antenna array design for (698-806) MHz UHF band application;performance evaluation of a P2P system in underlay cognitive radio network;design and simulation of antennas for energy harvesting systems in the WiFi band;low Power sensor node applied to domotic using IoT;proposal for a VoD service supported in a context-based architecture;architecture proposal for the processing of control algorithms applied in microgrids;news article classification of Mexican newspapers.

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20th international Workshop on computer Algebra in Scientific Computing, CASC 2018

20th International Workshop on Computer Algebra in Scientifi...

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20th international Workshop on computer Algebra in Scientific Computing, CASC 2018

ISBN: (纸本)9783319996387

The proceedings contain 25 papers. The special focus in this conference is on computer Algebra in Scientific Computing. The topics include: On a Polytime Factorization Algorithm for Multilinear Polynomials over F2;tropical Newton–Puiseux Polynomials;orthogonal Tropical Linear Prevarieties;symbolic-Numerical Algorithms forÂ Solving Elliptic Boundary-Value Problems Using Multivariate Simplex Lagrange Elements;symbolic-Numeric simulation of Satellite Dynamics with Aerodynamic Attitude Control System;finding Multiple Solutions in Nonlinear Integer Programming with Algebraic Test-Sets;positive Solutions of systems of Signed Parametric Polynomial Inequalities;qualitative Analysis of a Dynamical System with Irrational First Integrals;effective Localization Using Double Ideal Quotient and Its Implementation;on Unimodular Matrices of Difference Operators;a Purely Functional computer Algebra System embedded in Haskell;splitting Permutation Representations ofÂ Finite Groups by Polynomial Algebra Methods;factoring Multivariate Polynomials with Many Factors and Huge Coefficients;beyond the First Class of Analytic Complexity;a Theory and an Algorithm forÂ Computing Sparse Multivariate Polynomial Remainder Sequence;a Blackbox Polynomial System Solver onÂ Parallel Shared Memory computers;Sparse Polynomial Arithmetic with the BPASÂ Library;computation of Pommaret Bases Using Syzygies;a Strongly Consistent Finite Difference Scheme for Steady Stokes Flow and its Modified Equations;symbolic-Numeric Methods for Nonlinear Integro-Differential modeling;a Continuation Method for Visualizing Planar Real Algebraic Curves withÂ Singularities;from Exponential Analysis to Padé Approximation and Tensor Decomposition, in One and More Dimensions;Symbolic Algorithm for Generating the Orthonormal Bargmann–Moshinsky Basis for SU(3) Group.

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Memory Analysis and Performance modeling for HPC Applications on embedded Hardware via Instruction Accurate simulation

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2nd Annual international Scientific Federated conference on Software Development and Object Technologies (SDOT)

作者： Ditter, Alexander Schoenwetter, Dominik Kuzmin, Anton Fey, Dietmar Aizinger, Vadym Friedrich Alexander Univ Erlangen Nurnberg FAU Chair Comp Sci Comp Architecture 3 Erlangen Germany Friedrich Alexander Univ Erlangen Nurnberg FAU Chair Appl Math AM1 Erlangen Germany

ISBN: (纸本)9783319465357;9783319465340

The efficient usage and development of embedded multi-and many-core systems is an important field of research for years and decades. In the last decade, utilizing embedded and especially low-power architectures for high performance computing (HPC) applications became an important part of research. The reason for this are the constantly increasing energy costs along with an increasing awareness of energy consumption in general. As suitable low-power HPC architectures are not yet available at a larger scale, simulation of new and appropriate architectures becomes an important factor for the success of low-power systems and clusters. In order to speed up simulation, at the cost of accuracy, different levels of abstraction were introduced. Currently the class of instruction accurate simulations seems to yield the best trade-off between speed and precision, especially when simulating complex multi-and many-core systems. In this paper we present our investigations about the accuracy of the state-of-the-art instruction accurate embedded multi-and many-core simulation environment Open Virtual Platforms (OVP) in comparison to an actual embedded hardware system from Altera. Our investigations include the actual usage of the same operating system running on both, the target hardware and the simulation as well as serial and parallel software benchmarks. We analyze the current accuracy of the simulation environment with respect to a performance model, based on the execution time of the simulation and the actual embedded hardware system. Using the instruction accurate simulation technology from OVP is for the simulation of embedded/low-power HPC hardware architectures and applications. Furthermore, we point out first steps towards further possibilities for obtaining a better performance model by the use of our simple memory model.

关键词： Energy utilization

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