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检索条件"任意字段=International Conference on Embedded Computer Systems -Architectures, Modeling and Simulation"

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Borrowing from yourself: Faster future video segmentation with partial channel update 26

Borrowing from yourself: Faster future video segmentation wi...

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26th international conference on Pattern Recognition / 8th international Workshop on Image Mining - Theory and Applications (IMTA)

作者： Courdier, Evann Fleuret, Francois Idiap Res Inst EPFL Martigny Switzerland Univ Geneva Idiap Res Inst Geneva Switzerland

ISBN: (数字)9781665490627

ISBN: (纸本)9781665490627

Semantic segmentation is a well-addressed topic in the computer vision literature, but the design of fast and accurate video processing networks remains challenging. In addition, to run on embedded hardware, computer vision models often have to make compromises on accuracy to run at the required speed, so that a latency/accuracy trade-off is usually at the heart of these real-time systems' design. For the specific case of videos, models have the additional possibility to make use of computations made for previous frames to mitigate the accuracy loss while being real-time. In this work, we propose to tackle the task of fast future video segmentation prediction through the use of convolutional layers with time-dependent channel masking. This technique only updates a chosen subset of the feature maps at each time-step, bringing simultaneously less computation and latency, and allowing the network to leverage previously computed features. We apply this technique to several fast architectures and experimentally confirm its benefits for the future prediction subtask.

关键词： Heart computer vision Computational modeling Semantic segmentation Modulation Streaming media Predictive models

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Fast Bit-Sliced VLSI architectures on FPGA for Montgomery Domain Modular Inversion

Fast Bit-Sliced VLSI Architectures on FPGA for Montgomery Do...

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international conference on VLSI Design

作者： Soham Adhikary Ayan Palchaudhuri Department of Electronics & Communication Engineering School of Electrical and Computer Sciences Indian Institute of Technology Bhubaneswar Argul Khordha Odisha India

ISBN: (数字)9798331522445

ISBN: (纸本)9798331522452

Modular inversion computation forms a crucial component in Elliptic Curve Cryptosystems. In this paper, we have proposed a fast VLSI architecture for Kaliski's Montgomery domain modular inversion al-gorithm using bit-sliced design paradigm. Logic sharing among functional modules and direct configuration of the FPGA logic primitives were adopted to reduce the critical path wherever possible. The hardwired carry chain fabric of FPGA was exploited to bring down the critical path delay. The entire design flow was implemented on modern day FPGA family and the post-implementation timing simulation results are reported.

关键词： embedded systems simulation computer architecture Very large scale integration Elliptic curve cryptography Fabrics Table lookup Delays Logic Field programmable gate arrays

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A Dual-Critic Deep Deterministic Policy Gradient Approach for Task Offloading in Edge-Fog-Cloud Environment 5

A Dual-Critic Deep Deterministic Policy Gradient Approach fo...

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5th international conference on computer and Applications, ICCA 2023

作者： Ebrahim, Moshira A. Ebrahim, Gamal A. Mohamed, Hoda K. Ain Shams University Faculty of Engineering Computer and Systems Engineering Department Cairo11517 Egypt

ISBN: (纸本)9798350303254

Computation intensive IoT applications have grown exponentially over the past few years, which has led to the rise in popularity of the edge, fog, and cloud computing paradigms among mobile devices with embedded smart chips. Mobile Edge Computing (MEC) and Fog Computing (FC) usually cooperate with cloud computing to fulfill the high-demand requirements and optimize the network resources of complex computational offloading environments. In this paper, the topic of computational offloading for the hierarchical Edge-Fog-Cloud (EFC) computing is examined where edge, fog, and cloud nodes function as relay nodes that are constructed for latency critical and computations intensive jobs. Hierarchical EFC makes use of both centralized and distributed computing architectures considering diverse channel quality, network selection, and cloud access. This study proposes an improved Deep Reinforcement Learning (DRL) algorithm to find the optimal decision for offloading a computational task in EFC networks. simulation results validate the proposed DRL-based model by comparing it with other alternative algorithms. Experimental results demonstrate how the proposed approach can efficiently reduce the latency delay by 43% and energy cost by 32% of IoT end devices. Additionally, it can achieve a higher success rate compared with the other related algorithms with more than 16%. © 2023 IEEE.

关键词： Reinforcement learning

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Reconfigurable Planar Electromagnetic Lens Array modeling for Fast Performance Evaluation

Reconfigurable Planar Electromagnetic Lens Array Modeling fo...

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2023 IEEE international conference on Control, Electronics and computer Technology, ICCECT 2023

作者： Inserra, Daniele Xu, Wanqiang Zhang, Yuqiong Li, Zehua Abalo, Essohan-Eyouemou Xie, Fuzhen Wen, Guangjun Tonello, Andrea M. University of Electronic Science and Technology of China School of Information and Communication Engineering Chengdu China Alpen-Adria-Universität Klagenfurt Institute of Networked and Embedded Systems Klagenfurt Austria

ISBN: (纸本)9798350399028

Planar electromagnetic (EM) lenses are thin devices usually comprising sub-wavelength unit cell elements that synthesize a certain phase delay profile to focus the energy at a specific distance from the lens focal length. The design of these planar EM lenses unit cell elements is usually performed by means of full-EM simulation and optimization software. However, the full-EM simulation of the whole planar EM lens for its performance verification has an extremely large computational complexity, as well as it requires a very long simulation time. A mathematical model which describes the behavior of a planar EM lens array based on the characteristics of the EM lens unit cell elements is described in this paper. After that, this model is employed to benchmark the performance of a planar EM lens array based on a reconfigurable transmit array unit cell element, verifying the ability of the lens to reconfigure the focus characteristics to better deal with different incident angles ranges. © 2023 IEEE.

关键词： Benchmarking

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Enabling Multi-level Network modeling in Structural simulation Toolkit for Next-Generation HPC Network Design Space Exploration 38th

Enabling Multi-level Network Modeling in Structural Simulat...

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38th international conference on High Performance Computing, ISC High Performance 2023

作者： Chenna, Sai P. Kumar, Nalini Borges, Leonardo Steyer, Michael Thierry, Philippe Garzaran, Maria Intel Corporation Santa Clara United States Intel Corporation Munich Germany Intel Corporation Paris France

ISBN: (纸本)9783031408427

The last decade has seen high-performance computing (HPC) systems become denser and denser. Higher node and rack density has led to development of multi-level networks - at socket, node, ‘pod’, rack, and between nodes. As sockets become more complex with integrated or co-packaged heterogeneous architectures, this network complexity is going to increase. In this paper, we extend Structural simulation Toolkit (SST) to model these multi-level networks designs. We demonstrate this newly introduced capability by modeling a combination of a few different network topologies at different levels of the system and simulating the performance of collectives and some popular HPC communication patterns. © 2023, The Author(s), under exclusive license to Springer Nature Switzerland AG.

关键词： Network topology

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Symbiotic Content Caching in Next-Generation Information-Centric Networking 19

Symbiotic Content Caching in Next-Generation Information-Cen...

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19th Annual international conference on Distributed Computing in Smart systems and the Internet of Things, DCOSS-IoT 2023

作者： Rahman, Aisha B. Charatsaris, Panagiotis Siraj, Md Sadman Tsiropoulou, Eirini Eleni University of New Mexico Dept. of Electrical and Computer Engineering AlbuquerqueNM United States School of Electrical and Computer Engineering National Technical University of Athens Athens Greece

ISBN: (纸本)9798350346497

The continuous growth of mobile data traffic with strict time requirements calls for the development of sustainable edge content caching solutions. This becomes more prominent in the setting of Information-Centric Networking (ICN) architectures, where different ICNs are leasing caching slices to the available content providers (CPs), who in turn offer their services to the users. In this paper, we introduce a novel symbiotic content caching framework that provides the necessary economic benefits to the ICNs and the CPs to mutualistically collaborate among each other. The corresponding mutualistic interactions among the ICNs and CPs are studied under the prism of two different market-based models, namely the competitive market and oligopoly market models. A game-theoretic approach is followed in order to determine the optimal leasing prices of the ICNs' content caching slices and the CPs' optimal amount of leased caching memory from the ICNs. The performance evaluation of the proposed new symbiotic content caching paradigm is achieved via modeling and simulation, while the benefits and drawbacks of the competitive and oligopoly market modeling approaches are revealed and discussed. © 2023 IEEE.

关键词： Game theory

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PATARA: Extension of a Verification Framework for RISC-V Instruction Set Implementations 23rd

PATARA: Extension of a Verification Framework for RISC-V Ins...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Gesper, Sven Stuckmann, Fabian Wöbbekind, Lucy Payá-Vayá, Guillermo Chair for Chip Design for Embedded Computing Technische Universität Braunschweig Braunschweig Germany

ISBN: (纸本)9783031460760

Compliance testing is mandatory when implementing the hardware architecture of a specific RISC-V instruction set. An official compliance test suite with handwritten test cases can be helpful for this verification task. However, a high-quality test suite requires significant manual effort and cannot easily adapt to specific processor hardware architecture organization implementation aspects such as single-cycle, multi-cycle, or pipeline (with a different number of pipeline stages) configurations. This issue can be resolved by using an automatic test generation framework. However, these frameworks require the execution of a golden reference model for functional verification, which increases the verification time and introduces additional error possibilities. This paper extends the PATARA framework, based on the REVERSI approach, to generate randomized, self-testing test cases for any RISC-V hardware implementation. The REVERSI method takes profit of the instruction set to reverse the functionality of one instruction with other ones, verifying the functionality within the same test program and without requiring a golden reference model (e.g., simulator). The PATARA framework is extended to generate tests covering all possible hardware architecture implementation hazards and cache misses by taking into account different processor architecture parameters. In order to validate the methodology, a case study is used to verify a 6 pipeline-stages RV32IM hardware architecture implementation, reaching up to 100 % condition coverage with the REVERSI self-testing approach against 78.94% coverage achieved by the official handwritten compliance test framework. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Software testing

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High Performance Instruction Fetch Structure within a RISC-V Processor for Use in Harsh Environments 23rd

High Performance Instruction Fetch Structure within a RISC-V...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Hawich, Malte Rumpeltin, Nico Rücker, Malte Stuckenberg, Tobias Blume, Holger Leibniz University Hanover Institute of Microelectronic Systems Hanover Germany Drilling Services Baker Hughes Celle Germany

ISBN: (纸本)9783031460760

An increasing number of sensors and actuators are being used in today’s high-tech drilling tools to further optimise the drilling process. Each sensor and actuator either generates data that needs to be processed or requires real-time input control signals. RISC-V processors are being developed to meet the computational demands of today’s harsh environment applications. A known bottleneck for processors is the data flow and instruction input to the processor, especially as memory response times are particularly high for the state-of-the-art 180 nm harsh environment silicon-on-insulator (SOI) technology, further limiting the design space. Therefore, this paper presents a high-performance instruction fetch architecture that achieves a high clock frequency while preserving high instructions per cycle. We evaluate different approaches to implementing such a design and propose a design that is able to reach up to 0.73 instructions per cycle (IPC) and achieve a clock frequency of 229 MHz, which is more than twice as high as previous designs in this technology. The new architecture achieves 167 million instructions per second (MIPS), which is four times higher than the rocket chip achieves when synthesised for the same harsh environment technology. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Application specific integrated circuits

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Applying Formal Methods to Maximize Power Efficiency in embedded architectures

Applying Formal Methods to Maximize Power Efficiency in Embe...

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international conference on Computing and Networking Technology (ICCNT)

作者： Sonia Riyat Swati Gupta V. Pushparajesh Department of Management ARKA JAIN University Jamshedpur Jharkhand India Department of Life Sciences Vivekananda Global University Jaipur India Department of Electrical and Electronics Engineering School of Engineering and Technology JAIN (Deemed to be University) Bangalore Karnataka India

ISBN: (数字)9798350370249

ISBN: (纸本)9798350370270

With the increasing demand to make electronics ever smaller and more electricity efficient, embedded systems architectures have continued to evolve requiring new techniques for ensuring power efficiency of devices. The basic approach of this painting is to introduce how formal strategies have been used to improve energy performance on embedded architectures. Model-based strategies are used to edition architectural behavior and characteristics, crash protection, predictability through engineering verification (either by workflow or simulation), power performance. The power architectural structure and consumption are optimized by making powerful trade-offs between cost and space efficiency using the results of formal methods. The method proposed in this work is suitable for a wide range of embedded systems architectures and can easily be adapted to be implemented elsewhere on different structures. Although the paintings were not used to produce any software in colors and also have merits for these classes, this formal method can be a money-saver of energy consumption during the embedded systems development process with a reliability and performance guarantee.

关键词： Performance evaluation embedded systems Green design computer architecture Predictive models Reliability engineering Software Software reliability Protection Painting

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Proceedings - 2012 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2012

Proceedings - 2012 International Conference on Embedded Comp...

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2012 international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2012

ISBN: (纸本)9781467322973

The proceedings contain 45 papers. The topics discussed include: just-in-time verification in ADL-based processor design;virtual prototyping for efficient multi-core ECU development of driver assistance systems;system modeling and multicore simulation using transactions;BADCO : behavioral application-dependent superscalar core model;an application-specific network-on-chip for control architectures in RF transceivers;a framework for efficient cache resizing;a tightly-coupled multi-core cluster with shared-memory HW accelerators;architecture-level fault-tolerance for biomedical implants;reconfigurable miniature sensor nodes for condition monitoring;counting stream registers: an efficient and effective snoop filter architecture;design space exploration in application-specific hardware synthesis for multiple communicating nested loops;and memory bounds for the distributed execution of a hierarchical synchronous data-flow graph.

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