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Specific Emitter Identification based on CNN and Transformer 5

Specific Emitter Identification based on CNN and Transformer

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5th international Academic Exchange conference on Science and Technology Innovation, IAECST 2023

作者： Wang, Bin Gao, Ning Wang, Feng The 38th Research Institute of China Electronics Technology Group Corporation Key Laboratory of Aperture Array and Space Application Key Laboratory of Intelligent Information Processing Anhui Hefei230088 China Hefei University of Technology School of Computer and Information Hefei230601 China

ISBN: (纸本)9798350357738

Specific emitter identification(SEI) plays an increasingly crucial and potential role in both military and civilian scenarios. It refers to a process to discriminate individual emitters from each other by analyzing extracted characteristics from given radio signals. In this paper, we present a novel radiation source identification method named CNNFormer based on a hybrid architecture of Convolutional Neural Network and Transformer, harnessing the strengths of both architectures to enhance feature extraction and sequence modeling. We demonstrate the effectiveness of our approach on simulation datasets, achieving state-of-the-art accuracy in emitter identification. We showcase outstanding performance of our method on simulation datasets, achieving 98.29% three-class identification accuracy the emitter dataset with three devices and 97.60% ten-class identification accuracy on an RF fingerprint dataset with ten XSPR transmitters. Furthermore, our model allows for insight into the key features contributing to identification. This work contributes to enhancing the security and reliability of wireless communication systems. © 2023 IEEE.

关键词： Convolutional neural networks

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RISC-V Processor Technologies for Aerospace Applications in the ISOLDE Project 23rd

RISC-V Processor Technologies for Aerospace Applications in ...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Fornaciari, William Reghenzani, Federico Agosta, Giovanni Zoni, Davide Galimberti, Andrea Conti, Francesco Tortorella, Yvan Parisi, Emanuele Barchi, Francesco Bartolini, Andrea Acquaviva, Andrea Gregori, Daniele Cognetta, Salvatore Ciancarelli, Carlo Leboffe, Antonio Serri, Paolo Burrello, Alessio Pagliari, Daniele Jahier Urgese, Gianvito Martina, Maurizio Masera, Guido Di Carlo, Rosario Sciarappa, Antonio Politecnico di Milano Milan Italy University of Bologna Bologna Italy E4 Computer Engineering SpA Scandiano Italy Thales Alenia Space Italia S.p.A Turin Italy Politecnico di Torino Torino Italy Leonardo SpA Rome Italy

ISBN: (纸本)9783031460760

Modern space applications impose significant challenges to the design of hardware and software platforms. Beyond traditional applications such as avionics, Attitude Orbit Control, and signal/telemetry processing, new developments increasingly leverage Machine Learning models to enhance the autonomy of spacecraft. Such AI-based functional-ities promise significant advantages, but require computing power beyond what can be provided by current on-board platforms. At the same time, the challenge of technological sovereignty requires a move towards open hardware and software. To achieve these objectives, within the KDT ISOLDE project started in 2023, we propose the development of a new family of processors for AI-based applications to be deployed on board of satellites. In this paper, we showcase some examples of space applications with their requirements, and highlight the possible solutions as well as the corresponding work that will be carried out in ISOLDE, and the expected results. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Space applications

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Autonomous Driving Vision Accuracy modeling with Neural Networks 7

Autonomous Driving Vision Accuracy Modeling with Neural Netw...

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7th international conference on Inventive Computation Technologies, ICICT 2024

作者： Zhou, Jiyan Liu, Jinfeng Guangdong Provincial Science And Technology Cadre College Zhuhai519000 China

ISBN: (纸本)9798350359299

The study presents a novel approach to modeling accuracy in autonomous driving vision systems using neural networks. By merging various vision technologies and advanced neural network architectures, the proposed methodology aims to improve perception accuracy and safety in autonomous driving scenarios. The introduction describes the central role of automobiles in today's society and the burgeoning development of autonomous driving technologies in the automotive industry. The background section reviews recent advances in self-driving technology, emphasizing the integration of computational perception and multiple sensor inputs as foundational elements. The methodology section discusses the intricacies of vision modeling for autonomous driving, including object detection, instance segmentation, lane line detection, and 3D reconstruction models. The discussion extends to the challenges of accurate perception in autonomous vehicles, highlighting the importance of deep learning techniques and convolutional neural networks (CNNs). The simulation and testing section explains the experimental setup, leveraging high-performance computing resources and curated datasets for comprehensive evaluations. Evaluation metrics such as Intersection over Union (IoU) and Million Multiply-Accumulate Operations (MACs) are used to assess model performance and computational complexity. The results highlight the effectiveness of the proposed methodology in improving model accuracy and computational efficiency for various autonomous driving tasks. Ultimately, the study underscores the importance of accurate vision modeling in advancing the safety and reliability of autonomous driving technologies, and provides a foundational framework for future research and development efforts in this area. © 2024 IEEE.

关键词： computer vision

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FPGA-Based Network-Attached Accelerators - An Environmental Life Cycle Perspective 1

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36th international conference on Architecture of Computing systems (ARCS)

作者： Steinert, Fritjof Stabernack, Benno Heinrich Hertz Inst HHI Fraunhofer Telecommun Einsteinufer 37 D-10587 Berlin Germany Univ Potsdam Embedded Syst Architectures Signalproc August Bebel Str 89 D-14469 Potsdam Germany

ISBN: (数字)9783031427855

ISBN: (纸本)9783031427848;9783031427855

Homogeneous computing systems are reaching their limits with the growing demands of current applications. Accelerating compute-intensive applications ensures manageable computing times and boosts energy efficiency, which is an important lever as part of ongoing efforts to tackle global climate change. Field Programmable Gate Array (FPGA) accelerators are well-known for increasing throughput and, in particular, energy efficiency for many applications. FPGA accelerators connected directly to the data center high-speed network are ideal for integration into a heterogeneous data center, avoiding the energy and resource overhead of a carrier system. The standalone Network-attached Accelerators (NAAs) further benefits from low latency and predictable line-rate network throughput, as well as an interoperable communications interface. For selected use cases, we compare a heterogeneous computing cluster extended by NAAs with a homogeneous CPU-based cluster not only in terms of computing performance and energy efficiency, but also considering resource efficiency. For this purpose, we perform a Life Cycle Assessment (LCA) for both systems based on the Key Performance Indicators for Data Center Efficiency (KPI4DCE) indicator set, which takes into account the manufacturing phase in addition to the usage phase. The KPI4DCE tool has been extended to include modeling of NAAs. This allows us to show that NAAs are not only more energy-efficient, but also more resource-efficient for the selected applications, leading to a strong improvement of the environmental impact of the manufacturing phase.

关键词： FPGA Network-attached Accelerator Data Center Life Cycle Assessment Reconfigurable Computing Heterogeneous Computing

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Efficient Handover Mode Synchronization for NR-REDCAP on a Vector DSP 23rd

Efficient Handover Mode Synchronization for NR-REDCAP on a V...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Qureshi, Sheikh Faizan Damjancevic, Stefan Matus, Emil Utyansky, Dmitry Wolf, Pieter van der Fettweis, Gerhard Vodafone Chair Mobile Communications Systems Technische Universität Dresden Dresden01062 Germany Synopsys Inc Yerevan Armenia Synopsys Inc Eindhoven Netherlands

ISBN: (纸本)9783031460760

To enable the low-cost design of 5G IoT Standard reduced capability (NR-REDCAP) devices, hardware-software trade-offs must be made for various signal processing baseband kernels. Dedicated hardware for a kernel provides better speed and power efficiency but limits the device’s programmability. With the varying range of user equipment (UE) deployment scenarios and dynamic wireless channel conditions, flexible solutions like DSPs are favorable for implementing channel estimation, channel equalization, and waveform modulation/demodulation algorithms. Due to stringent requirements on latency for algorithms like decimation, synchronization, and decoding, designers might favor dedicated hardware over DSP-based solutions. Such dedicated hardware increases the device cost as it needs to be added to the modem design solely to implement synchronization. In this work, we study the most critical operation mode of synchronization for the NR-REDCAP standard, i.e., during the Handover between cells. Whereas for the enhanced mobile broadband (eMBB) 5G NR standard, dedicated hardware might be the best implementation choice for decimation and synchronization;in contrast, for NR-REDCAP, a cost saving can be achieved by implementing and optimizing the kernels onto the vector DSP. After algorithmic and structural optimizations, our results show that the synchronization procedure can be accommodated on a vector DSP with a clock frequency of 500 MHz. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Synchronization

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The FPGA Implementation of Pseudorandom Word Generation Algorithms 12

The FPGA Implementation of Pseudorandom Word Generation Algo...

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12th IEEE international conference on Intelligent Data Acquisition and Advanced Computing systems: Technology and Applications, IDAACS 2023

作者： Opanasenko, Volodymyr Zavyalov, Stanislav V.M. Glushkov Institute of Cybernetics of Nas of Ukraine Department of Microprocessor Devices Kyiv03187 Ukraine Radionix Limited Company Kyiv03187 Ukraine

ISBN: (纸本)9798350358056

This paper introduces a novel FPGA-based hardware implementation of a pseudorandom word (PSW) generator. Using the FPGA reconfiguration property, the proposed approach allows you to change the algorithms and replace the online structure during the generator. The integration of embedded digital signal processing (DSP) blocks within the FPGA chip allows for the efficient implementation of the pseudorandom bit generator by leveraging fundamental operations like multiplication with accumulation at the gate level. The PSW generator's design and implementation are performed using the VHDL language and the CAD tool ISE 14.02 Foundation. The implementation is carried out on a Spartan-based series chip (6SLX4CSG225-3), and the paper provides a comprehensive analysis of the time and hardware costs associated with three different types of pseudorandom word generators. To validate the effectiveness of the designs, the simulation results are obtained using the ModelSim SE 10.1c, and timing diagrams are presented for these structures. © 2023 IEEE.

关键词： bit sequence generation CAD DSP FPGA generator of pseudo-random sequences random number generation reconfigurable logic simulation modeling statistical randomness

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BusyMap, an Efficient Data Structure to Observe Interconnect Contention in SystemC TLM-2.0

BusyMap, an Efficient Data Structure to Observe Interconnect...

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Design, Automation and Test in Europe conference and Exhibition

作者： Emad M. Arasteh Vivek Govindasamy Rainer Dömer Chapman University Orange CA USA Center for Embedded and Cyber-physical Systems University of California Irvine USA

ISBN: (数字)9783981926385

ISBN: (纸本)9798350348606

For designing embedded computer architectures that meet desired performance constraints at low cost, fast and accurate simulation models are needed early in the design flow. To identify and avoid bottlenecks early at the system level, observing the contention of shared resources is critical. In this paper, we propose and evaluate a novel data structure called BusyMap that accurately reflects contention at system busses or similar inter-connect components. BusyMap is an efficient data structure that allows the system designer to accurately model and easily observe contention in IEEE loosely-timed TLM-2.0. In contrast to prior state-of-the-art, our model fully supports temporal decoupling and multiple levels of interconnect. Our experiments demonstrate the effectiveness of BusyMap with results showing high accuracy at high -speed System C simulation.

关键词： embedded systems Costs Computational modeling Data structures Data models Timing

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MoDLF - A Model-Driven Deep Learning Framework for Autonomous Vehicle Perception (AVP) 22

MoDLF - A Model-Driven Deep Learning Framework for Autonomou...

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ACM/IEEE 25th international conference on Model Driven Engineering Languages and systems (MODELS)

作者： Safdar, Aon Azam, Farooque Anwar, Muhammad Waseem Akram, Usman Rasheed, Yawar Natl Univ Sci & Technol Coll EME Dept Comp & Software Engn Lahore Pakistan Malardalen Univ Dept Innovat Design & Engn Vasteras Sweden

ISBN: (纸本)9781450394666

Modern vehicles are extremely complex embedded systems that integrate software and hardware from a large set of contributors. modeling standards like EAST-ADL have shown promising results to reduce complexity and expedite system development. However, such standards are unable to cope with the growing demands of the automotive industry. A typical example of this phenomenon is autonomous vehicle perception (AVP) where deep learning architectures (DLA) are required for computer vision (CV) tasks like real-time object recognition and detection. However, existing modeling standards in the automotive industry are unable to manage such CV tasks at a higher abstraction level. Consequently, system development is currently accomplished through modeling approaches like EAST-ADL while DLA-based CV features for AVP are implemented in isolation at a lower abstraction level. This significantly compromises productivity due to integration challenges. In this article, we introduce MoDLF - A Model-Driven Deep learning Framework to design deep convolutional neural network (DCNN) architectures for AVP tasks. Particularly, Model Driven Architecture (MDA) is leveraged to propose a metamodel along with a conformant graphical modeling workbench to model DCNNs for CV tasks in AVP at a higher abstraction level. Furthermore, Model-To-Text (M2T) transformations are provided to generate executable code for MATLAB((R)) and Python. The framework is validated via two case studies on benchmark datasets for key AVP tasks. The results prove that MoDLF effectively enables model-driven architectural exploration of deep convnets for AVP system development while supporting integration with renowned existing standards like EAST-ADL.

关键词： Model-Driven Architecture Model transformation Low code Autonomous vehicles perception Deep learning computer vision

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The Interplay between Business Needs and Data Architecture Explored through Enterprise Architecture Models 17

The Interplay between Business Needs and Data Architecture E...

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17th IFIP WG 8.1 Working conference on the Practice of Enterprise modeling Forum, 1st international Workshop on Models for simulation, M4S 2024, 2nd international Workshop on the Foundations and Applications of Capabilities in Enterprises, Transformations, and ESG Initiatives, FACETE 2024, Workshop on Advancing Enterprise Modelling through Digital Transformation, FAIR Data Management, and Blockchain Integration, AEM 2024, Tools and Demos, PoEM-Companion 2024

作者： Petersen, Sobah Abbas Krogstie, John Department of Computer Science Norwegian University of Science and Technology Trondheim Norway

It is of enormous importance that our IT-solutions contribute to sustainable development of society. The ZEN (center on Zero Emission Neighbourhoods) have developed a set of Key Performance Indicators that are deemed important to follow up as we build and refurbish the built environment to achieve net-energy-positive areas that produce more electricity than what it uses, including during the building process. The focus on these kinds of initiatives is often technical and represented as informal descriptions and models of IT and data architectures. In this study, we investigate the use of Enterprise Architecture modeling in ArchiMate to represent both the technical aspects, but in interplay with also the organizational and business aspects of a solution to support the achievement of zero-emission buildings and neighborhoods from the point of view of a diverse set of stakeholders. Going from a purely technical focus to an enterprise focus enables a richer discussion on what needs to be in place to enable the development and evolution of systems to monitor the adherence to the selected Key Performance Indicators. It also illustrates the multi-valency of the underlying data in that it can be used in different ways for different purposes and user-groups. In this work, we use this insight in the development of a set of dashboards presenting data for different types of users for different purposes. © 2024 Copyright for this paper by its authors.

关键词： Green buildings

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The Cost of Flexibility: embedded versus Discrete Routers in CGRAs for HPC

The Cost of Flexibility: Embedded versus Discrete Routers in...

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IEEE international conference on Cluster Computing (CLUSTER)

作者： Adhi, Boma Cortes, Carlos Tan, Yiyu Kojima, Takuya Podobas, Artur Sano, Kentaro RIKEN Ctr Computat Sci R CCS Kobe Hyogo Japan Iwate Univ Dept Syst Innovat Engn Sci & Engn Morioka Iwate Japan Univ Tokyo Grad Sch Informat Sci & Technol Tokyo Japan KTH Royal Inst Technol Stockholm Sweden

ISBN: (数字)9781665498562

ISBN: (纸本)9781665498562

Coarse-Grained Reconfigurable Arrays (CGRAs) are a class of reconfigurable architectures that inherit the performance and usability properties of Central Processing Units (CPUs) and the reconfigurability aspects of Field-Programmable Gate Arrays (FPGAs). Historically, CGRAs have been successfully used to accelerate embedded applications and are today also being considered to accelerate High-Performance Computing (HPC) applications in future supercomputers. However, embedded systems and supercomputers are two vastly different domains with different applications and constraints, and it is today not fully understood what CGRA design decisions adequately cater to the HPC market. One such unknown design decision is regarding the interconnect that facilitates intra-CGRA communication. Today, intra-CGRA communication comes in two flavors: using routers closely embedded into the compute units or using discrete routers outside the compute units. The former trades flexibility for a reduction in hardware cost, while the latter has greater flexibility but is more resource hungry. In this paper, we aspire to understand which of both designs best suits the CGRA HPC segment. We extend our previous methodology, which consists of both a parameterized CGRA design and an OpenMP-capable compiler, to accommodate both types of routing designs, including verification tests using RTL simulation. Our results show that the discrete router design can facilitate better use of processing elements (PEs) compared to embedded routers and can achieve up to 79.27% reduction in unnecessary PE occupancy for an aggressively unrolled stencil kernel on a 18 x 16 CGRA at a (estimated) hardware resource overhead cost of 6.3x. This reduction in PE occupancy can be used, for example, to exploit instruction-level parallelism (ILP) through even more aggressive unrolling.

关键词： CGRA Routing architecture Design space exploration HPC RTL simulation

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