The proceedings contain 50 papers. The topics discussed include: concurrent memory subsystem and application optimization for ASIP design;automatic recognition of computational kernels for platform-dependent code opti...
ISBN:
(纸本)9781509030767
The proceedings contain 50 papers. The topics discussed include: concurrent memory subsystem and application optimization for ASIP design;automatic recognition of computational kernels for platform-dependent code optimizations;Bard: a unified framework for managing soft timing and power constraints;power models supporting energy-efficient co-design on ultra-low power embeddedsystems;real-time tasks and voltage/frequency controller collaboration on low power energy operational systems;a bypass first policy for energy-efficient last level caches;AccuRA: accurate alignment of short reads on scalable reconfigurable accelerators;simulator calibration for accelerator-rich architecture studies;exploring system performance using elastic traces: fast, accurate and portable;CoolSim: statistical techniques to replace cache warming with efficient, virtualized profiling;architecture exploration of a programmable neural network processor for embeddedsystems;design productivity of a high level synthesis compiler versus HDL;a configurable SIMD architecture with explicit datapath for intelligent learning;improving performance in VLIW soft-core processors through software-controlled ScratchPads;and NanoStreams: codesigned microservers for edge analytics in real time.
The proceedings contain 52 papers. The topics discussed include: rethinking memory system design for data-intensive computing;visual processing sparks a new class of processors;experiences in speeding up computer visi...
ISBN:
(纸本)9781467373111
The proceedings contain 52 papers. The topics discussed include: rethinking memory system design for data-intensive computing;visual processing sparks a new class of processors;experiences in speeding up computer vision applications on mobile computing platforms;parallelism extraction in embedded software for android devices? reconfigurable computing for future vision-capable devices;learning-based analytical cross-platform performance prediction;bridging the semantic gap between heterogeneous modeling formalisms and FMI;platform-aware dynamic data type refinement methodology for radix tree data structures;efficient dual-ISA support in a retargetable, asynchronous dynamic binary translator;tervel: a unification of descriptor-based techniques for non-blocking programming;and physical design aware system level synthesis of hardware.
The proceedings contain 48 papers. The topics discussed include: co-design of many-accelerator heterogeneous systems exploiting virtual platforms;robustness analysis of multiprocessor schedules;dynamic-vector executio...
ISBN:
(纸本)9781479937707
The proceedings contain 48 papers. The topics discussed include: co-design of many-accelerator heterogeneous systems exploiting virtual platforms;robustness analysis of multiprocessor schedules;dynamic-vector execution on a general purpose EDGE chip multiprocessor;combining application adaptivity and system-wide resource management on multi-core platforms;resource conscious prefetching for irregular applications in multicores;characterizing communication behavior of dataflow programs using trace analysis;on tokens and signals: bridging the semantic gap between data flow models and hardware implementations;and automated design flow for coarse-grained reconfigurable platforms: an RVC-CAL multi-standard decoder use-case.
An introduction is presented in which the editor discusses various reports within the issue on topics including video coding, embeddedsystems, and dynamic cache adaptation.
An introduction is presented in which the editor discusses various reports within the issue on topics including video coding, embeddedsystems, and dynamic cache adaptation.
The proceedings contain 41 papers. The topics discussed include: parallelizing general histogram application for CUDA architectures;abstraction of polychronous dataflow specifications into mode-automata;modeling pipel...
ISBN:
(纸本)9781479901036
The proceedings contain 41 papers. The topics discussed include: parallelizing general histogram application for CUDA architectures;abstraction of polychronous dataflow specifications into mode-automata;modeling pipelined application with synchronous data flow graphs;parallel implementation of real-time semi-global matching on embedded multi-core architectures;a process-based reconfigurable SystemC module for simulation speedup;lightweight resource estimation model to extend battery life in video playback;energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs;an embedded hardware-efficient architecture for real-time cascade support vector machine classification;concurrent multi-level arrays: wait-free extensible hash maps;and fast transaction-level dynamic power consumption modeling in priority preemptive wormhole switching networks on chip.
OpenGL SC 2 is Khronos' Graphics API for safety critical systems. However, unlike other Khronos' APIs, available OpenGL SC 2 drivers are only provided by vendors to their customers. This hinders the wide adopt...
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ISBN:
(纸本)9783031783791;9783031783807
OpenGL SC 2 is Khronos' Graphics API for safety critical systems. However, unlike other Khronos' APIs, available OpenGL SC 2 drivers are only provided by vendors to their customers. This hinders the wide adoption of OpenGL SC 2, which is limited to a niche market, since there are very limited available resources for it. In this work, we describe the design and implementation of an Open Source Installable Client Driver (ICD) and offline compiler on top of OpenGL ES 2.0. Thus, our solution enables the development of OpenGL SC 2.0.1 applications on any embedded system, as well as their deployment on selected safety critical platforms, which do not have an available OpenGL SC 2.0.1 driver yet.
The challenges involved in executin Neural Networks (NNs) at the edge include providing diversity, flexibility, and sustainability. That implies, for instance, supporting evolving applications and algorithms energy-ef...
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ISBN:
(数字)9783031783807
ISBN:
(纸本)9783031783791;9783031783807
The challenges involved in executin Neural Networks (NNs) at the edge include providing diversity, flexibility, and sustainability. That implies, for instance, supporting evolving applications and algorithms energy-efficiently. Using hardware (hw) or software accelerators can deliver fast and efficient computation of the NNs, while flexibility can be exploited to support long-term adaptivity. Nonetheless, handcrafting a NN for a specific device, despite the possibility of leading to an optimal solution, takes time and experience, and that's why frameworks for hw accelerators are being developed. This work, starting from a preliminary semi-integrated ONNX-to-hardware toolchain [23], focuses on enabling Approximate Computing (AC) leveraging the distinctive ability of the original toolchain to favor adaptivity. The goal is to allow lightweight adaptable NN inference on FPGAs at the edge.
Digital microfluidic biochips provide a controlled and miniaturized environment to carry out biochemical protocols in an automated fashion. Software-based simulators are essential tools that aid the design of such pro...
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ISBN:
(数字)9783031783807
ISBN:
(纸本)9783031783791;9783031783807
Digital microfluidic biochips provide a controlled and miniaturized environment to carry out biochemical protocols in an automated fashion. Software-based simulators are essential tools that aid the design of such protocols by enabling users to verify correct execution before targeting the physical biochip. To produce a simulation that is faithful to reality, the fluidic behavior of the droplets and their interaction with the driving electrodes must be taken into account. This paper presents a framework for simulating DMF biochips in a resource-constrained web-based environment. The framework is based on a novel droplet model that uses logic-based calculations to capture fluidic behavior. Thus, enabling to faithfully simulate the movement, merging, and splitting of arbitrary-shaped droplets with a low-computational footprint. The simulation framework also includes modular component models to capture the behavior of sensors and actuators, an event-driven simulation engine, and a graphical user interface. The framework is implemented as a client-side web application and runs in a browser. The evaluation carried out using artificial and real-life test cases shows that the framework can deliver real-time simulations with a high level of fidelity.
Efficient processing architectures for irregular data patterns require vector element addressing with flexible indices. Therefore, state-of-the-art SIMD vector extensions implement gather and scatter instructions for ...
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ISBN:
(纸本)9783031783760;9783031783777
Efficient processing architectures for irregular data patterns require vector element addressing with flexible indices. Therefore, state-of-the-art SIMD vector extensions implement gather and scatter instructions for indexed addressing of data in memory. In vertical vector processors, different data is processed sequentially in parallel lanes and can be exchanged via chaining. This paper proposes an extension of such chaining mechanisms in a vertical vector processor architecture (V2PRO) to flexibly chain not only data but also address offsets between vector lanes. The indirect addressing enables vector access patterns with irregular strides for both register file and memory. The extension has a low hardware overhead of +4.8 % lookup tables and +1.8% registers on a Xilinx Ultrascale+ FPGA. A runtime evaluation for two applications from computer vision, namely Deformable Convolutions and point cloud encoding with PointPillars, demonstrates speedups of at least an order of magnitude with the proposed extension.
The evolution of mobile networks (5G/B5G) relies on different hybrid transport architectures that enable flexible and scalable interconnection between devices and services with different interfaces and requirements. D...
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ISBN:
(纸本)9783031783791;9783031783807
The evolution of mobile networks (5G/B5G) relies on different hybrid transport architectures that enable flexible and scalable interconnection between devices and services with different interfaces and requirements. Despite significant improvements in data rates, device capabilities and data volumes compared to previous generations, technology choices are still under consideration and new proposals are constantly emerging. To address these challenges, Int5Gent proposes and develops a 5G/B5G system that integrates innovative data plane technology building blocks within a flexible orchestration framework. The proposed platform provides a complete 5G system for validating advanced services and Internet of Things solutions, facilitating the transition beyond current 5G network capabilities, and evaluating state-of-the-art data transport and edge processing solutions.
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