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检索条件"任意字段=International Conference on Embedded Computer Systems -Architectures, Modeling and Simulation"

共 2875 条记录，以下是231-240 订阅

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System-Level modeling and simulation of MPSoC Run-Time Management Using Execution Traces Analysis 19th

System-Level Modeling and Simulation of MPSoC Run-Time Manag...

引用

19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Yang, S. Le Nours, S. Real, M. Mendez Pillement, S. Univ Nantes CNRS IETR UMR 6164 F-44000 Nantes France

ISBN: (纸本)9783030275624;9783030275617

Dynamic management of modern Multi-Processors System on Chip (MPSoC) become mandatory for optimization purpose. Evaluation of these managers is essential early in the design process to guarantee a reduced design cycle. However, most of the existing system-level simulation-based frameworks consider static application mapping and do not consider the run-time management effects. In this work, we present a modeling and simulation approach that allows integration of run-time management strategies in MPSoC system simulation. We have integrated the proposed approach in an industrial modeling and simulation framework. A case-study with seven applications running on a heterogeneous multicore platform is considered and different management strategies are evaluated according to latency and power consumption criteria.

关键词： System-level simulation Execution trace Run-time management strategies Heterogeneous multicore systems

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DL Based System for On-Board Image Classification in Real Time, Applied to Disaster Mitigation

DL Based System for On-Board Image Classification in Real Ti...

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international conference on Parallel Distributed and Grid Computing (PDGC)

作者： Amogh Shukla Shubh Almal Ankur Gupta Rinisha Jain Rishabh Mishra Dharmesh Dhabliya School of CSE Vellore Institute of Technology Vellore TL India Department of CSE Vaish College of Engineering Rohtak Haryana India Vishwakarma Institute of Information Technology Pune Maharashtra India

ISBN: (纸本)9781665454025

Natural phenomena such as earthquakes that cause the destruction of bridges and can cause tsunamis, among other phenomena and disasters, are on the rise as a result of climate change, which is affecting our planet. This is because of the rise in average global temperature and the development of extreme rains, which causes rivers to overflow. The use of satellites for terrestrial observation has made it possible to keep tabs on events throughout the world in recent years. However, these satellite systems aren't without their drawbacks; one is that cloud cover may make it difficult to accurately record photographs. It is done based on the clouds present, and another drawback is the visiting time that the satellites have, which means that the area that you want to record the image is not always available, so you have to wait for the day and the time in which the satellite orbit can pass through the area of interest that the image is to be recorded. Drones, which fly at low altitudes and do not have cloud problems, are one such alternative, solving a problem of satellites, on cloud cover. In light of this, in the present work, a methodology based on low-cost systems is proposed for on-board processing in drones of such data in the event of an emergency, such as after the effects of rain or an earthquake. Methodology involves processing the image in an embedded device, which is coupled to the drone and connected to the camera, in such a way that the information that is sent to the ground station, concentrates on the affected area; this allows for faster decision-making and lessens the impact of the natural disaster. Therefore, it is shown by testing of the embedded computer based on a Raspberry pi 3 for detecting changes in land cover and transmitting this information to an earth station.

关键词： Training Satellites Rain Clouds Computational modeling simulation Earthquakes

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EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Chip Prototyping on FPGAs

EmuNoC: Hybrid Emulation for Fast and Flexible Network-on-Ch...

引用

international conference on Field Programmable Logic and Applications

作者： Yee Yang Tan Felix Staudigl Lukas Jünger Anna Drewes Rainer Leupers Jan Moritz Joseph Institute for Communication Technologies and Embedded Systems RWTH Aachen University Germany Institute for Information and Communication Technologies Otto-von-Guericke Universität Magdeburg Germany

Networks-on-Chips (NoCs) recently became widely used, from multi-core CPUs to edge-AI accelerators. Emulation on FPGAs promises to accelerate their RTL modeling compared to slow simulations. However, realistic test stimuli are challenging to generate in hardware for diverse applications. In other words, both a fast and flexible design framework is required. The most promising solution is hybrid emulation, in which parts of the design are simulated in software, and the other parts are emulated in hardware. This paper proposes a novel hybrid emulation framework called EmuNoC. We introduce a clock-synchronization method and software-only packet generation that improves the emulation speed by 36.3 × to 79.3 × over state-of-the-art frameworks while retaining the flexibility of a pure-software interface for stimuli simulation. We also increased the area efficiency to model up to an NoC with 169 routers on a single FPGA, while previous frameworks only achieved 64 routers.

关键词： Emulation Network-on-chip computer architecture Benchmark testing Software Hardware Field programmable gate arrays

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Accelerating Fixed-Point simulations Using Width Reconfigurable Hardware architectures

Accelerating Fixed-Point Simulations Using Width Reconfigura...

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international conference on Field Programmable Logic and Applications

作者： Keyvan Shahin Michael Huebner Chair of Computer Engineering Brandenburg University of Technology Cottbus Germany

Digital Signal Processing (DSP) systems can be described using either fixed-point or floating-point for their numeric representations. As the general computers use floating-point representation, software-based simulation tools used for modeling and simulation of the arithmetic operations in DSP systems, use floating-point representation as well. However, synthesizing customized hardware for fixed-point arithmetic operations for FPGAs or ASICs is more efficient compared to their floating-point counterparts. Thus it is necessary to convert the representation of a floating-point simulated algorithm on MATLAB for example, to a fixed-point representation which is more suitable for hardware implementation. While former approaches for this conversion step have always been software-based, like on MATLAB itself, this paper presents a new approach to show the possibility of accelerating it by using hardware width reconfigurable designs.

关键词： computers Computational modeling Signal processing algorithms Digital signal processing Tools Hardware Numerical models

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9th international Workshop on Model-Based Design of Cyber Physical systems, CyPhy 2019 and 15th international Workshop on embedded and Cyber-Physical systems Education, WESE 2019, held in conjunction with ESWeek 2019

9th International Workshop on Model-Based Design of Cyber Ph...

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9th international Workshop on Model-Based Design of Cyber Physical systems, CyPhy 2019 and 15th international Workshop on embedded and Cyber-Physical systems Education, WESE 2019, held in conjunction with ESWeek 2019

ISBN: (纸本)9783030411305

The proceedings contain 13 papers. The special focus in this conference is on Model-Based Design of Cyber Physical systems, embedded and Cyber-Physical systems Education. The topics include: A Remote Test Environment for a Large-Scale Microcontroller Laboratory Course;an embedded Graduate Lab Course with Spirit;Competence Networks in the Era of CPS – Lessons Learnt in the ICES Cross-Disciplinary and Multi-domain Center;multicore Models of Communication for Cyber-Physical systems;towards Creating a Deployable Grasp Type Probability Estimator for a Prosthetic Hand;reactors: A Deterministic Model for Composable Reactive systems;guaranteed simulation of Dynamical systems with Integral Constraints and Application on Delayed Dynamical systems;Advanced Hazard Analysis and Risk Assessment in the ISO 26262 Functional Safety Standard Using Rigorous simulation;practical Multicore Extension of Functionally and Temporally Correct Real-Time simulation for Automotive systems;Constraint-Based modeling and Symbolic simulation of Hybrid systems with HydLa and HyLaGI;guaranteed Optimal Reachability Control of Reaction-Diffusion Equations Using One-Sided Lipschitz Constants and Model Reduction.

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Predictive Resource Management for Next-Generation High-Performance Computing Heterogeneous Platforms 19th

Predictive Resource Management for Next-Generation High-Perf...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Massari, Giuseppe Pupykina, Anna Agosta, Giovanni Fornaciari, William Politecn Milano DEIB Via Ponzio 34-5 Milan Italy

ISBN: (纸本)9783030275624;9783030275617

High-Performance Computing (HPC) is rapidly moving towards the adoption of nodes characterized by an heterogeneous set of processing resources. This has already shown benefits in terms of both performance and energy efficiency. On the other side, heterogeneous systems are challenging from the application development and the resource management perspective. In this work, we discuss some outcomes of the MANGO project, showing the results of the execution of real applications on a emulated deeply heterogeneous systems for HPC. Moreover, we assessed the achievements of a proposed resource allocation policy, aiming at identifying a priori the best resource allocation options for a starting application.

关键词： HPC Heterogeneous systems Resource management

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7th international conference on Model-Driven Engineering and Software Development, MODELSWARD 2019

7th International Conference on Model-Driven Engineering and...

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7th international conference on Model-Driven Engineering and Software Development, MODELSWARD 2019

ISBN: (纸本)9783030378721

The proceedings contain 16 papers. The special focus in this conference is on Model-Driven Engineering and Software Development. The topics include: The Understandability of Models for Behaviour;a Model-Based Combination Language for Scheduling Verification;TRILATERAL: A Model-Based Approach for Industrial CPS – Monitoring and Control;classifying Approaches for Constructing Single Underlying Models;a Framework for Flexible Program Evolution and Verification of Distributed systems;modeling and Analysis of Partitions on Functional architectures Using EAST-ADL;Evaluating the Multi-variant Model Transformation of UML Class Diagrams to Java Models;executing Scenario-Based Specification with Dynamic Generation of Rich Events;towards Multi-editor Support for Domain-Specific Languages Utilizing the Language Server Protocol;Integrating UML and ALF: An Approach to Overcome the Code Generation Dilemma in Model-Driven Software Engineering;preface;a Framework for Multi-level modeling of Analog/Mixed Signal embedded systems;the Art of Bootstrapping;dataset Management Using Metadata.

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Access Interval Prediction for Tightly Coupled Memory systems 19th

Access Interval Prediction for Tightly Coupled Memory System...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Wittig, Robert Hasler, Mattis Matus, Emil Fettweis, Gerhard Tech Univ Dresden Vodafone Chair Mobile Commun Syst Dresden Germany

ISBN: (纸本)9783030275624;9783030275617

Today, processing elements of embedded systems usually share some amount of the available on-chip memory in order to maximize the area utilization. However, sharing memory incurs runtime conflicts, which entail performance penalties. To ease this restriction, we introduce a method for memory Access Interval Prediction. It minimizes conflicts by predicting the interval between two consecutive memory accesses. In contrast to contemporary work, we do not rely on compile time information or other a priori knowledge. Standard benchmarks show that we can predict over 80% of all memory access intervals correctly, thereby significantly reducing the number of access conflicts.

关键词： Memory prediction Access interval Shared memory MPSoC

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A workflow for automatically generating application-level safety mechanisms from UML stereotype model representations 15

A workflow for automatically generating application-level sa...

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15th international conference on Evaluation of Novel Approaches to Software Engineering, ENASE 2020

作者： Huning, Lars Iyenghar, Padma Pulvermueller, Elke Institute of Computer Science University of Osnabrück Wachsbleiche 27 Osnabrück49090 Germany

ISBN: (纸本)9789897584213

Safety-critical systems operate in contexts where failure may lead to serious harm for humans or the environment. Safety standards, e.g., IEC 61508 or ISO 26262, provide development guidelines to improve the safety of such systems. For this, they recommend a variety of safety mechanisms to mitigate possible safety hazards. While these standards recommend certain safety mechanisms, they do not provide any concrete development or implementation assistance for any of these techniques. This paper presents a detailed workflow, how such safety mechanisms may be automatically generated from UML model representations in a model-driven development process. We illustrate this approach by applying it to the modeling and automatic generation of voting mechanisms, which are a wide-spread safety mechanism in safety-critical systems that employ some form of redundancy for fault detection or fault masking. Finally, we study the scalability of the proposed code generation via quantitative experiments. © Copyright 2020 by SCITEPRESS - Science and Technology Publications, Lda. All rights reserved.

关键词： embedded systems

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Optimization and Performance modeling of Stencil Computations on ARM architectures 22

Optimization and Performance Modeling of Stencil Computation...

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22nd IEEE international conference on High Performance Computing and Communications, 18th IEEE international conference on Smart City and 6th IEEE international conference on Data Science and systems, HPCC-SmartCity-DSS 2020

作者： Zhang, Kaifang Su, Huayou Zhang, Peng Dou, Yong National University of Defense Technology National Key Laboratory for Parallel and Distribution Processing Changsha China Caep Software Center for High Performance Numerical Simulation Beijing China Institute of Applied Physics and Computational Mathematics Beijing China

ISBN: (纸本)9781728176499

Stencil Computation has long been an omnipresent kernel of a wide range of scientific and engineering applications. There is much work investigating the stencil performance on x86 processors and accelerators such as GPU. Meanwhile, ARM processors for HPC have been highlighted more and more with Fugaku of Japan becoming the first number one system on the TOP-500 list. In this paper, we focus on modeling and optimizing the performance of stencil computation on ARM architectures. Specifically, we proposed a performance model for stencil computation based on tiling optimization to guide the optimal configuration of tiling parameters for good cache reuse. We validate the proposed model with the Performance Monitor Unit (PMU) provided by the ARM processor. Experimental results show that the prediction error of the execution time can be lower to 1.37%. Furthermore, we can achieve a maximum of 1.26 \times speedup compared to the naive implementation according to the optimization parameters provided from the model. © 2020 IEEE.

关键词： ARM processors

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