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Design of an Autonomous Underwater Vehicle EDYSYS 1

Design of an Autonomous Underwater Vehicle EDYSYS 1

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Multidisciplinary Engineering and Applied Science (ICMEAS), international conference on

作者： Edosa Osa Eguagie Evbuomwan Emmanuel. E. Ajari Faculty of Engineering University of Benin Benin City Nigeria Embedded Firmware Engineering SHYFT Power Solutions Lagos Nigeria

ISBN: (纸本)9781665434942

An Autonomous Underwater Vehicle (AUV) is an underwater robot that can operate in six degrees of freedom (6DOF) thereby carrying out preplanned missions via its propulsion and navigation systems which are controlled by an onboard computer. This paper describes the design of an Autonomous Underwater Vehicle, EDYSYS 1. The AUV was first modeled in SolidWorks and thereafter navigation capabilities were tested in a simulation environment using A* algorithm and Robot Operating System (ROS) platform in Unity 3-D game engine. The design for the mechanical, electronics, control and communication subsystems are described as well as operation states.

关键词： Underwater structures Autonomous underwater vehicles Solid modeling Visualization Navigation Computational modeling Operating systems

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Alternate Coupling for Targeted Supply Chain Attacks 15

Alternate Coupling for Targeted Supply Chain Attacks

引用

15th international conference on Cyber Warfare and Security (ICCWS)

作者： Rohret, David M. Jimenez, Abiud Gen Dynam Informat Technol San Antonio TX 78218 USA Dynetics Inc Huntsville AL 35805 USA

ISBN: (纸本)9781912764532

The authors demonstrate that power-conditioning circuitry on a system's mainboard can be affected using specific power levels, frequencies, and modulation, for an alternative coupling effect to create repeatable results. This effect in-turn triggers embedded code to compromise or exploit targeted systems. Pulse Width Modulation (PWM) circuitry, as part of the power conditioning circuitry, manages power to resources so resource blocks receive sufficient power during heavy usage (i.e. memory during modeling and simulation). To accomplish this task, the PWM maintains a continuous power reading to maintain power consumption efficiency, ensuring an over-voltage condition does not arise. In the event a surge or other external event occurs, the hosts' system bios will react to a surge condition by shutting down or rebooting. Following the reboot or a user-initiated restart, embedded code runs prior to the volatile memory erasure sequence to capture data stored in reserved memory and exfiltrates data using covert communications. computers used for testing were loaded with a payload designed to run on reboot, acquire volatile memory in a file, and starts a network service allowing remote retrieval of the file. For Phase 1 experimentation, an initial state was enabled on each computer to simulate a working environment following each test run, providing researchers the ability to acquire the data in residual memory resulting from an alternative coupling attack. The teams current research has three objectives;to identify if current memory modules in use (DDR3 and DDR4) are susceptible to similar effects identified in early testing, identify covert effects and power requirements using alternative coupling against specific Integrated Circuits (ICs), and covert effects by creating a repeatable 8-bit data stream using alternative coupling.

关键词： Alternative coupling covert communications supply chain attack embedded exploits

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PreSyNC: Hardware realization of the Presynaptic Region of a Biologically Extensive Neuronal Circuitry

PreSyNC: Hardware realization of the Presynaptic Region of a...

引用

international conference on VLSI Design

作者： Rounak Chatterjee Souradeep Chowdhury Soham Mondal Arnab Raha Janet Paluh Amitava Mukherjee Jadavpur University Kolkata India Memory Solutions Samsung Electronics Co. Ltd. Bangalore India Advanced Architecture Research Intel Edge. AI Intel Corporation Santa Clara USA Colleges of Nanoscale Science and Engineering Nanobioscience SUNY Polytechnic Institute Albany New York USA Adamas University Kolkata India

Spiking Neural Networks (SNN) have gained relevance in recent times, due to their ability to mimic the biological nature to communicate and process sparse asynchronous binary signals in a massively parallel fashion. SNN based neuromorphic hardware exhibits highly desired favourable properties such as low power consumption, fast inference, and event-driven information processing. A recognized challenge of standard SNN neuron models is their limited capabilities in biological applications, such as applying neural networks to study network responses arising from variations pertaining to damage, external influence or disruptions in channel transfer dynamics. This paper presents Pre-Synaptic Neuronal Circuit (PreSyNC), a high performance hardware realization of an input-specific presynaptic region of a generic neuron, without abstraction of primary intra-neuronal parameters. PreSyNC is configured to operate on three precision modes: IEEE 754 single precision, double precision and the recently developed universal number posit number system. The developed hardware design is compared to current standards of SNN neuron models as well as biological models in terms of flexibility, resource efficiency and damage modelling capability. Error margins as low as 0.9 % were obtained and suggest the capability of our hardware in handling applications involving large scale neuron networks. These architectures are synthesized on 45 nm process technology where they all operate at a minimum frequency of approximately 1GHz. The three precision modes are compared based on power, accuracy, and sensitivity handling and are expected to benefit implantation oriented applications such as neural prosthesis and Human-computer Interaction (HCI). The posit-based implementation outperforms the rest of the operating modes in terms of RMS error, while having 26.3 % less area and 25.2 % less power consumption compared to double precision implementation. These new architectures can be expanded in the fut

关键词： Human computer interaction Adaptation models Power demand Neuromorphics Biological system modeling Neurons Hardware

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Multicore Performance Prediction - Comparing Three Recent Approaches in a Case Study 25th

Multicore Performance Prediction - Comparing Three Recent Ap...

引用

25th international conference on Parallel and Distributed Computing (Euro-Par)

作者： Lueders, Matthias Arndt, Oliver Jakob Blume, Holger Leibniz Univ Hannover Inst Microelect Syst Hannover Germany

ISBN: (纸本)9783030483401;9783030483395

Even though parallel programs, written in high-level languages, are portable across different architectures, their parallelism does not necessarily scale after migration. Predicting a multicore-application's performance on the target platform in an early development phase can prevent developers from unpromising optimizations and thus significantly reduce development time. However, the vast diversity and heterogeneity of system-design decisions of processor types from HPC and desktop PCs to embedded MPSoCs complicate the modeling due to varying capabilities. Concurrency effects (caching, locks, or bandwidth bottlenecks) influence parallel runtime behavior as well. Complex performance prediction approaches emerged, which can be grouped into: virtual prototyping, analytical models, and statistical methods. In this work, we predict the performance of two algorithms from the field of advanced driver-assistance systems in a case study. With the following three methods, we provide a comparative overview of state-of-the-art predictions: GEM5 (virtual prototype), IBM Exabounds (analytical model), and an in-house developed statistical method. We first describe the theoretical background, describe the experimental- and model-setup, and give a detailed evaluation of the prediction. In addition, we discuss the applicability of all three methods for predicting parallel and heterogeneous systems.

关键词： Performance prediction Virtual prototyping Parallelization Advanced driver-assistance systems Scalability MPSoC

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On Compact Mappings for Multicore systems 19th

On Compact Mappings for Multicore Systems

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Goens, Andres Menard, Christian Castrillon, Jeronimo Tech Univ Dresden Chair Compiler Construct Ctr Adv Elect Dresden Cfaed Dresden Germany

ISBN: (纸本)9783030275624;9783030275617

Application mapping is key for efficient multicore processing, i.e., selecting which resources to allocate to a given application, like computation to cores. Mapping is increasingly difficult in multi-application scenarios, where resource contention might degrade the performance of an application. In order to solve this, a promising avenue is to consider "compact" mappings, those which require a small and (geometrically) compact area within the chip. Compact mappings should decrease contention between applications by providing regional isolation and allowing multiple applications to be mapped simply. Previous work has shown that compact mappings can significantly outperform mappings obtained with a random strategy. In this paper we investigate the promise of compact mappings by running extensive simulations on Noxim, a cycle-accurate network-on-chip simulator. Results show the promises of compact mappings do not hold up in practice. When comparing to mappings selected with a heuristic better than simply choosing cores at random, our experiments do not indicate significant advantages from compact mappings. We outline possible reasons for this.

关键词： Mapping

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Evaluation of Electric Vehicle Hosting Capacity in Campus Microgrid Using Monte Carlo simulation

Evaluation of Electric Vehicle Hosting Capacity in Campus Mi...

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international conference on Electrical Machines and systems (ICEMS)

作者： Tae-Han Kim Dam Kim Seung-Il Moon Electrical and Computer Engineering Seoul National University Seoul South Korea Electrical Electronics & Communication Engineering Education Chungnam National University Daejeon South Korea

The electric vehicle and electric vehicle charger market is rapidly growing due to increased interest in carbon free. When a lot of electric vehicles and chargers are penetrated into the distribution network, various problems such as voltage drop may occur. Therefore, it is essential to accurately determine the hosting capacity of electric vehicles from the point of view of system operation. Electric vehicles have a variety of uncertainties, including arrival and departure times, state of charge and selection of charging station. To evaluate the hosting capacity of electric vehicles, these uncertainties must be taken into account. In this paper, load modeling was performed considering the uncertainty of electric vehicle, and the hosting capacity of electric vehicle was evaluated using monte carlo simulation. In addition, load modeling was performed using the actual power consumption data of buildings in Seoul National University. The network was modeled using the parameters of the actually embedded cable. Based on the modeled data, the hosting capacity was evaluated by assuming an electric vehicle based on the actual vehicle access data.

关键词： Uncertainty Monte Carlo methods Power demand Power cables systems operation Voltage Microgrids

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Software Passports for Automated Performance Anomaly Detection of Cyber-Physical systems 19th

Software Passports for Automated Performance Anomaly Detecti...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Odyurt, Uraz Meyer, Hugo Pimentel, Andy D. Paradas, Evangelos Alonso, Ignacio Gonzalez Univ Amsterdam Informat Inst IvI Amsterdam Netherlands ASML Netherlands BV Veldhoven Netherlands

ISBN: (纸本)9783030275624;9783030275617

Software performance anomaly detection is a major challenge in complex industrial cyber-physical systems. The automated comparison of runtime execution metrics to reference ones provides a potential solution. We introduce the concept of software passports, intended to act as a signature construct for runtime performance behaviour of reference executions. Our software passport design is based on Extra-Functional Behaviour (EFB) metrics. Amongst such metrics, our focus has been especially on CPU time, read and write communication event counts of different processes. The notion of phases for systems with repetitive tasks during their execution and its fundamental role in our software passports has also been elaborated. We employ regression modelling of our collected data for comparative purposes. The comparison reveals inconsistencies between the execution at hand and the software passport, if present. Such inconsistencies are strong indicators for presence of performance anomalies. Our design is capable of detecting synthetically introduced performance anomalies to the real execution tracing data from a semiconductor photolithography machine.

关键词： Software passports Performance anomaly detection Industrial cyber-physical systems Regression modelling

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Efficient Dynamic Device Placement for Deep Neural Network Training on Heterogeneous systems 19th

Efficient Dynamic Device Placement for Deep Neural Network T...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Huang, Zi Xuan Fu, Shen Yu Hsu, Wei Chung Natl Taiwan Univ Dept Comp Sci & Informat Engn Taipei Taiwan

ISBN: (纸本)9783030275624;9783030275617

Deep Neural Networks (DNNs) based learning methods have brought revolutionary advances in computer vision and machine learning. However, training a DNN model often requires very intensive computational resources. For edge incremental learning, more energy efficient learning solutions are called for. Heterogeneous computing is more power efficient, and has been increasingly popular for embedded platforms. Therefore, how to deploy training models on heterogeneous platforms to support edge learning is a critical issue. Due to the increasing size of DNNs, it is rather difficult to determine how to dispatch a large number of operations to proper devices. One state-of-art approach uses reinforcement learning to address this device placement issue, but is too costly to apply in an embedded setting. In this paper, our approach leverages the information available from the computational graph of the model, and the dynamic profiles of run time and communication time of each device, to more efficiently deploy operations on heterogeneous systems. We use Critical Earliest Finish Time (CEFT) algorithm together with the Partitioned Boolean Quadratic Assignment Problem (PBQP) solver to find a cost-effective placement, and dynamically adjust assignments during the training process, which makes our method more adaptive and effective for different computational environments. On AlexNet, VGG, Inception, ResNet, RNNLM and other well-known models, our approach significantly outperforms traditional algorithms and reinforcement learning based methods.

关键词： Deep neural networks

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RRAMSpec: A Design Space Exploration Framework for High Density Resistive RAM 19th

RRAMSpec: A Design Space Exploration Framework for High Dens...

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19th international conference on embedded computer systems: architectures, modeling, and simulation (SAMOS)

作者： Mathew, Deepak M. Chinazzo, Andre Lucas Weis, Christian Jung, Matthias Giraud, Bastien Vivet, Pascal Levisse, Alexandre Wehn, Norbert Tech Univ Kaiserslautern Kaiserslautern Germany Fraunhofer Inst Expt Software Engn IESE Kaiserslautern Germany Univ Grenoble Alpes CEA LETI MINATEC Campus Grenoble France Ecole Polytech Fed Lausanne Embedded Syst Lab ESL Lausanne Switzerland

ISBN: (纸本)9783030275624;9783030275617

Resistive RAM (RRAM) is a promising emerging Non-Volatile Memory candidate due to its scalability and CMOS compatibility, which enables the fabrication of high density RRAM crossbar arrays in Back-End-Of-Line CMOS processes. Fast and accurate architectural models of RRAM crossbar devices are required to perform system level design space explorations of new Storage Class Memory (SCM) architectures using RRAM e.g. Non-Volatile-DIMM-P (NVDIMM-P). The major challenge in architectural modeling is the trade-off between accuracy and computing intensity. In this paper we present RRAMSpec, an architecture design space exploration framework, which enables fast exploration of various architectural trade-offs in designing high density RRAM devices, at accuracy levels close to circuit level simulators. The framework estimates silicon area, timings, and energy for RRAM devices. It outperforms state-of-the-art RRAM modeling tools by conducting architectural explorations at very high accuracy levels within few seconds of execution time. Our evaluations show various trade-offs in designing RRAM crossbar arrays with respect to array sizes, write time and write energy. Finally we present the influence of technology scaling on different RRAM design trade-offs.

关键词： RRAM ReRAM Crossbar NVM

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Modelling of vertical and ferroelectric junctionless technology for efficient 3D neural network compute cube dedicated to embedded artificial intelligence

Modelling of vertical and ferroelectric junctionless technol...

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international Electron Devices Meeting (IEDM)

作者： C. Maneux C. Mukherjee M. Deng M. Dubourg L. Reveil G. Bordea A. Lecestre G. Larrieu J. Trommer E.T. Breyer S. Slesazeck T. Mikolajick O. Baumgartner M. Karner D. Pirker Z. Stanojevic David Atienza A. Levisse G. Ansaloni A. Poittevin A. Bosio D. Deleruyelle C. Marchand I. O'Connor IMS University of Bordeaux UMR CNRS 5218 Bordeaux INP Talence France LAAS-CNRS UPR 8001 CNRS Université de Toulouse Toulouse France NaMLab gGmbH Dresden Germany Global TCAD Solutions GmbH Vienna Austria EPFL Lausanne Switzerland INL University of Lyon CNRS UMR 5270 Ecole Centrale de Lyon Ecully France

ISBN: (纸本)9781665425735

This paper presents the set of simulation means used to develop the concept of N 2 C 2 (neural network compute cube) based on a vertical transistor technology platform. On the basis of state-of-the-art junctionless nanowire transistors (JLNT), TCAD simulation, compact modeling and EM simulation are leveraged through a Design-Technology Co-Optimization (DTCO) to achieve innovative 3D circuit architectures. Further, System-Technology Co-Optimization (STCO) implications on 3D NN system architecture are explored.

关键词： Solid modeling Three-dimensional displays Computational modeling systems architecture computer architecture Artificial neural networks Transistors

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