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Real-time VLSI techniques for processing of computer images 19

Real-time VLSI techniques for processing of computer images

引用

conference on Applications of Digital Image Processing XIX

作者： Farroha, BS Deshmukh, RG Florida Institute of Technology (United States)

ISBN: (纸本)0819422355

The domain of industrial automation has been of heightened interest since the introduction of robotic vision in the work place. The system discussed in this abstract is designed to be utilized in the areas of machine and robotic vision for the industrial field. It can serve as an inspection or location finding device for real-time closed loop automated systems, The performance advantage of this system is gained through the use of a massively parallel architecture. The system is built on a VLSI wafer, where the concept of a full application specific system is fabricated on a chip. These design techniques take advantage of massive parallel hardware at the lower stages of image processing whereby increasing the performance of this stage can significantly improve the total throughput of the system. The design procedure is based on custom ASIC hardware that is optimized for the task at hand. Additionally, the elements have been designed in a modular and reusable manner. The processing of system data is accomplished primarily, by parallel hardware units, with firmware assigned the responsibility of configuring and defining the task. This system incorporates the design theorems of image processing with the fundamentals of high speed architectures. This design technique, in conjunction with parallel processing principles, will overcome the current time limitations that have been persistent in the current approaches. The system is designed with three functional layers, each composed of parallel architectures and local control. A main control system is also present to monitor overall system functionality and issue queuing commands for the processes, in a non-blocking manner. The proposed system theory and design will be presented with the VLSI layout, simulation and modeling with the CADENCE design environment. Test results and prototype examples are used to determine the success of the system and test it's limitations.

关键词： VLSI architecture image processing robotic vision massive parallel processing real-time imaging

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The Augmint multiprocessor simulation toolkit for Intel x86 architectures

The Augmint multiprocessor simulation toolkit for Intel x86 ...

引用

IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： A.-T. Nguyen M. Michael A. Sharma J. Torrellas Center for Supercomputing Research and Development University of Illinois Urbana-Champaign Urbana IL USA Department of Computer Science University of Rochester Rochester NY USA

Most publicly available simulation tools only simulate RISC architectures. These tools cannot capture the instruction mix and memory reference patterns of CISC architectures. We present an overview of Augmint, an execution driven multiprocessor simulation toolkit that fills this gap by supporting Intel x86 architectures. Augmint also supports trace driven simulation for uniprocessors as well as multiprocessors, with minor effort on the part of simulator developers. Augmint runs m4 macro extended C and C++ applications such as those in the SPLASH and SPLASH-2 benchmark suites. Augmint supports a thread based programming model with shared global address space and private stack space. Augmint supports a simulator interface compatible with that of the MINT simulation toolkit for MIPS architectures, thus allowing the reuse of most architecture simulators written for MINT. Augmint simulations run on x8d based uniprocessor systems under Unix or Windows NT. The source code of Augmint is publicly available from http://***/iacoma/augmint.

关键词： Computational modeling computer architecture computer simulation Hardware Software prototyping Analytical models Trademarks computer science Memory architecture Prototypes

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Finite word-length effects of an unified systolic array for 2-D DCT/IDCT

Finite word-length effects of an unified systolic array for ...

引用

international conference on Application Specific systems (ASAP), architectures and Processors

作者： H. Lim C. Yim E.E. Swartzlander Department of Electrical and Computer Engineering University of Texas Austin Austin TX USA

This paper presents a fixed-point error analysis for the unified systolic array implementation of 2-dimensional (2-D) discrete cosine transform (DCT) and 2-D inverse discrete cosine transform (IDCT). Closed form expressions for the mean and variance of fixed-point rounding-errors and truncation-errors are derived. simulation results are provided to verify the analysis. simulations designed to find the minimum word-length which satisfies IEEE requirements for the implementation of an 8/spl times/8 IDCT are also performed. simulation results show that the proposed systolic array is more robust for the fixed-point error than other existing implementations for DCT/IDCT.

关键词： Systolic arrays Discrete cosine transforms Error analysis Analytical models Fixed-point arithmetic Computational modeling Robustness Signal processing Image processing Data compression

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A fine-grain multithreading superscalar architecture

A fine-grain multithreading superscalar architecture

引用

international conference on Parallel Architecture and Compilation Techniques (PACT)

作者： M. Loikkanen N. Bagherzadeh Department of Electrical and Computer Engineering University of California Irvine USA

In this study we show that fine-grain multithreading is an effective way to increase instruction-level parallelism and hide the latencies of long-latency operations in a superscalar processor. The effects of long-latency operations, such as remote memory references, cache-misses, and multi-cycle floating-point calculations, are detrimental to performance since such operations typically cause a stall. Even superscalar processors, that are capable of performing various operations in parallel, are vulnerable. A fine-grain multithreading paradigm and unique multithreaded superscalar architecture is presented. simulation results show significant speedup over single-threaded superscalar execution.

关键词： Multithreading Yarn Parallel processing Delay computer architecture Processor scheduling Computational modeling computer simulation computer science Operating systems

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Effect of task allocation methods for mesh-connected parallel computers considering task size limitation and machine size extension

Effect of task allocation methods for mesh-connected paralle...

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IEEE international conference on Algorithms and architectures for Parallel Processing (ICAP)

作者： K. Suzaki H. Tanuma S. Hirano Y. Ichisugi M. Tukamoto Electro Technical Laboratory Tsukuba Ibaraki Japan

We analyzed the behavior of task allocation methods "Two Dimensional Buddy", "Adaptive Scan" and time sharing systems that use them for mesh-connected parallel computers under task size limitation and machine size extension. The efficiency of task allocation methods for mesh-connected parallel computers is expected to be impressed by the shapes and sizes of rectangular processor partitions which are required by tasks and a machine. In general the task allocation methods are expected to improve packing ability of tasks if the number of processor for a task is limited. However the execution time of the task is expanded. We examined performance trade-off between increased packing ability and task size limitation under task size scalability. Furthermore, we examined how to extend a parallel computer efficiently. From simulation results we confirmed that task size limitation improved performance of task allocation methods and that rectangular extension is better than square extension.

关键词： Concurrent computing Partitioning algorithms Scalability Time sharing computer systems Computational modeling Application software Laboratories Shape computer simulation computer architecture

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System for optimisation of electronic circuits using genetic algorithm

System for optimisation of electronic circuits using genetic...

引用

IEEE international conference on Electronics, Circuits and systems (ICECS)

作者： M. Wojcikowski J. Glinianowicz M. Bialko University of Karlsruhe Karlsruhe Germany Technical University of Gdansk Gdansk Poland

In this paper an automatic system for optimisation of analogue circuits is presented. The improvement of the circuit's parameters is made using the genetic algorithm. The fitness values required by this algorithm are extracted from the results of computer simulations of the circuit. The system runs simultaneously on several computers in order to obtain the results in a short time. As an example the optimisation of MOS Operational Transconductance Amplifier (OTA) was chosen. The system was written in CLIPS expert system shell with C++ functions embedded and runs on PC connected together to Novell network.

关键词： Electronic circuits Genetic algorithms Circuit testing Object oriented modeling Circuit simulation SPICE computer simulation Operational amplifiers Expert systems Algorithm design and analysis

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Integrated design process with MESA/MERLAN

Integrated design process with MESA/MERLAN

引用

IEEE international Symposium on computer Aided Control System Design (CACSD)

作者： Y. Tanurhan S. Schmerler K.D. Muller-Glaser Department of Electronic Systems and Microsystems F Z I Computer Science Research Center Karlsruhe Karlsruhe Germany

In this paper, a methodology for the design of microelectronic systems which include hardware and software for open-loop and closed-loop control will be presented. An integrated approach to specification and design, analysis and simulation of the overall system has been developed. This provides for a systematic, computer aided approach to requirements definition, specification and design as well as verification and validation of the results. As embedded systems often require real-time capabilities, the environment presented gives special consideration to these constraints. For verification purpose of the developed design and specification methodology a software prototype has been implemented and used in concrete example applications, which is also presented in this paper.

关键词： Process design Design methodology Microelectronics Hardware Open loop systems Control systems Computational modeling Analytical models embedded system Real time systems

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Parallel simulation of mesh routing algorithms

Parallel simulation of mesh routing algorithms

引用

international conference on Distributed Computing systems

作者： S. Rahman C.R. Das Strategic Semiconduct or Operations Motorola Inc. Boynton Beach FL USA Department of Computer Science & Engineering Pennsylvania State University University Park PA USA

Performance of a network depends primarily on the network topology, switching mechanism, flow control protocol and the underlying routing algorithm. While many routing algorithms have been proposed recently for direct networks, there is no time efficient technique to evaluate and compare all of them. A conventional routing algorithm simulation of a network on a uniprocessor takes unacceptably large computing time. The simulation can be made very time efficient by parallelizing it and running on a parallel test bed. This research is focussed on designing a parallel routing algorithm simulator for n-dimensional mesh connected networks with wormhole switching and virtual channel flow control. The research addresses partitioning mapping, synchronization issues, and implementation of various routing algorithms for 2-D and 3-D mesh architectures. Experimental results show that the parallel simulator can provide significant speedup compared do a uniprocessor environment.

关键词： Computational modeling Discrete event simulation Network topology computer networks Testing Algorithm design and analysis Clocks Routing protocols Partitioning algorithms Communication system control

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An incremental benchmark suite for performance tuning of parallel discrete event simulation

An incremental benchmark suite for performance tuning of par...

引用

Annual Hawaii international conference on System Sciences (HICSS)

作者： R. Ronngren L. Barriga R. Ayani Department of Teleinformatics Royal Institute of Technology Stockholm Sweden

Parallel simulation has been an active research area for more than a decade, and several parallel simulation algorithms have been proposed. To evaluate parallel simulation environments, there is a need for a common benchmark suite. Such benchmarks should allow the designer of simulation kernels to: (i) evaluate how efficiently the simulation kernel runs on specific architectures; and (ii) evaluate how simulation problems scale on the kernel. A vast majority of benchmarks suggested in the literature focus on the latter problem. The first requirement is however equally important, as such benchmarks are needed to implement efficient simulation systems. In this report, we advocate an incremental benchmark methodology which is primarily intended for performance tuning. The benchmark suite is based on a small set of ping models with which it is possible to effectively isolate and estimate various overheads, contention and latencies encountered in simulation kernels. The use of the benchmark suite is illustrated by its application to performance tuning and evaluation of a time warp kernel.

关键词： Discrete event simulation Computational modeling Kernel computer simulation computer architecture Performance analysis Communication networks Parallel processing Delay Application software

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On the performance verification of embedded systems with concurrent dynamic applications

On the performance verification of embedded systems with con...

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Asilomar conference on Signals, systems & computers

作者： A. Kalavade P. Moghe DSP & VLSI Systems Research Bell Laboratories Holmdel NJ USA Network & Service Management Research Bell Laboratories Holmdel NJ USA

embedded systems that support multiple concurrent applications are becoming increasingly sophisticated. For instance, such systems are beginning to support dynamic applications (that is, applications that exhibit run-time dependence in their behavior). Deploying dynamic concurrent applications introduces new challenges in the design and verification of system architectures that support them. A unique aspect that characterizes the specification of such an application mix is the "temporal skew" between the applications. This skew is not necessarily known a priori. Since different skews could impose different processing requirements on the system, it becomes necessary to verify the system performance under all possible skews. We present a methodology for the rapid verification of such systems. The main idea is to formulate an analytical problem called the skew problem which aims to determine the "worst-case skew" between applications with run-time dependence, for a given system architecture. The worst-case skew is defined as the skew that imposes the most intensive processing requirements on the system architecture. We propose a fast analytical tool that solves the skew problem. The system can be verified by simulating it only for the mix of applications with the worst-case skew. All other skews are guaranteed their performance requirements. This speeds up the verification process since the number of simulation runs required is now decoupled from the combinatorics of the skew search space.

关键词： embedded system System performance computer architecture Runtime Hardware Digital signal processing Very large scale integration Protocols Computational modeling Combinatorial mathematics

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