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ResNet-like Architecture with Low Hardware Requirements

ResNet-like Architecture with Low Hardware Requirements

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international conference on Pattern Recognition

作者： Elena Limonova Daniil Alfonso Dmitry Nikolaev Vladimir V. Arlazarov FRC CSC RAS Smart Engines Service LLC Moscow Russia Moscow Russia Institute for Information Transmission Problems RAS Moscow Russia

ISBN: (纸本)9781728188089;9781728188096

One of the most computationally intensive parts in modern recognition systems is an inference of deep neural networks that are used for image classification, segmentation, enhancement, and recognition. The growing popularity of edge computing makes us look for ways to reduce its time for mobile and embedded devices. One way to decrease the neural network inference time is to modify a neuron model to make it more efficient for computations on a specific device. The example of such a model is a bipolar morphological neuron model. The bipolar morphological neuron is based on the idea of replacing multiplication with addition and maximum operations. This model has been demonstrated for simple image classification with LeNet-like architectures [1]. In the paper, we introduce a bipolar morphological ResNet (BM-ResNet) model obtained from a much more complex ResNet architecture by converting its layers to bipolar morphological ones. We apply BM-ResNet to image classification on MNIST and CIFAR-10 datasets with only a moderate accuracy decrease from 99.3% to 99.1 % and from 85.3% to 85.1 %. We also estimate the computational complexity of the resulting model. We show that for the majority of ResNet layers, the considered model requires 2.1-2.9 times fewer logic gates for implementation and 15-30 % lower latency.

关键词： Training Image recognition Power demand Computational modeling Neurons computer architecture Logic gates

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Model-Based Design for high performance devices oriented to advanced smart solutions

Model-Based Design for high performance devices oriented to ...

引用

international conference on Information Science and Technology (ICIST)

作者： Loubna Belhamel Arturo Buscarino Antonio Cucuccio Luigi Fortuna Gaetano Rascona University of Catania Catania Italy CNR-IASI Italian National Research Council-Institute for Systems Analysis and Computer Science A. Ruberti Rome Italy STMicroelectronics Catania Italy

ISBN: (数字)9781728166469

ISBN: (纸本)9781728166476

This paper applies Model-Based Design methodologies to develop a high-performance device driver model suitable for advanced smart solutions. These modeling techniques are mandatory to use when designing advanced smart applications based on embedded devices. The paper proposes an innovative approach to accurately models the operations of the STM32 analog converter peripheral for both simulation purpose and to generate an optimized code that integrates on the Low-Level STM32 firmware driver. A new Simulink toolbox has been developed to replicate the ADC functions. Finally, an example has been presented to show the effectiveness of this new modeling approach.

关键词： Performance evaluation Information science Software packages Design methodology Encoding Device drivers Microprogramming

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Comprehensive Evaluation of Program Reliability with ComFIDet: An Integrated Fault Injection and Detection Framework for embedded systems

Comprehensive Evaluation of Program Reliability with ComFIDe...

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IEEE international conference on embedded Software and systems (ICESS)

作者： Hosseini, Fateme S. Yang, Chengmo Univ Delaware Dept Elect & Comp Engn Newark DE 19716 USA

ISBN: (纸本)9781728124377

The study of program behavior in unreliable hardware infrastructure via fault injection is of great interest to researchers. By modeling the effect of faults on program behavior, programs can be tuned to be more fault resilient via fault-tolerant approaches, or to be tuned to saved energy via approximate computing techniques. Existing frameworks, however, do not adequately address the need of fault injection/detection simulation. To fill this gap, this paper proposes ComFIDet, a low-overhead and comprehensive instruction-level fault injection/detection framework. ComFIDet allows for the identification of both reliable and unreliable regions of a program via the simulation of a variety of hardware faults and can further be utilized in the tuning of a reliable design or an approximate computing technique through the implementation of run-time fault detection and effortless experiment replay. ComFIDet offers an easy to reconfigure process, iterative fault injection experiments, and requires zero modifications to the program under test. ComFIDet is evaluated through a comprehensive set of tests, exploring the effects of one possible configuration on program behavior.

关键词： Reliability engineering Fault detection Program processors Controllability Hardware Registers

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A Low-Cost Distributed Mapping for Large-Scale Applications of Reconfigurable Computing systems

A Low-Cost Distributed Mapping for Large-Scale Applications ...

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international CSI computer conference, CSICC

作者： Seyed Mehdi Mohtavipour Hadi Shahriar Shahhoseini School of Electrical Engineering Iran University of Science and Technology Tehran Iran

ISBN: (数字)9781728159379

ISBN: (纸本)9781728159386

Reconfiguration capability in nowadays embedded systems such as Reconfigurable Computing (RC) systems improves the execution of applications efficiently. However, the reconfiguration overhead in the mapping process of application compilation degrades the performance of these systems. In this paper, a novel distributed application graph mapping has been proposed to reduce the heavy computations of mapping problem analytically. For this purpose, matrix modifications have been used to derive a distance model in resource graph. Using this model, it is possible to remove heavy-weight values from the search space of solutions and achieve a low-cost solution faster, as well. This model classifies the distance matrix of resource graph into independent regions to transform the mapping problem into suboptimal problems. simulation results show that the proposed approach for application graph mapping outperformed the stateof-art methods in terms of complexity and time overhead, especially for large-scale application graphs.

关键词： distributed processing embedded systems graph theory reconfigurable architectures Reconfigurable architectures Distributed processing embedded systems Graph theory MAPPING(MATHEMATICAL) mapping distance matrix configurability Line graph large sizes

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Reduced Order modeling of Dynamical systems Using Artificial Neural Networks Applied to Water Circulation 35th

Reduced Order Modeling of Dynamical Systems Using Artificial...

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35th international conference on High Performance Computing , ISC High Performance 2020

作者： Costa Nogueira, Alberto de Sousa Almeida, João Lucas Auger, Guillaume Watson, Campbell D. IBM Research HortolandiaSP13186-900 Brazil IBM Research Yorktown HeightsNY10598 United States

ISBN: (纸本)9783030598501

General circulation models are essential tools in weather and hydrodynamic simulation. They solve discretized, complex physical equations in order to compute evolutionary states of dynamical systems, such as the hydrodynamics of a lake. However, high-resolution numerical solutions using such models are extremely computational and time consuming, often requiring a high performance computing architecture to be executed satisfactorily. Machine learning (ML)-based low-dimensional surrogate models are a promising alternative to speed up these simulations without undermining the quality of predictions. In this work, we develop two examples of fast, reliable, low-dimensional surrogate models to produce a 36 h forecast of the depth-averaged hydrodynamics at Lake George NY, USA. Our ML approach uses two widespread artificial neural network (ANN) architectures: fully connected neural networks and long short-term memory. These ANN architectures are first validated in the deterministic and chaotic regimes of the Lorenz system and then combined with proper orthogonal decomposition (to reduce the dimensionality of the incoming input data) to emulate the depth-averaged hydrodynamics of a flow simulator called SUNTANS. Results show the ANN-based reduced order models have promising accuracy levels (within of the prediction range) and advocate for further investigation into hydrodynamic applications. © 2020, Springer Nature Switzerland AG.

关键词： Hydrodynamics

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Statistical Performance Prediction for Multicore Applications Based on Scalability Characteristics 30

Statistical Performance Prediction for Multicore Application...

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30th IEEE international conference on Application-Specific systems, architectures and Processors (ASAP)

作者： Arndt, Oliver Jakob Lueders, Matthias Blume, Holger Leibniz Univ Hannover Inst Microelect Syst D-30167 Hannover Germany

ISBN: (纸本)9781728116013

Multicore processors serve as target platforms in a broad variety of applications ranging from high-performance computing to embedded mobile computing and automotive. But, the required parallel programming opens up a huge design space of parallelization strategies each with potential bottlenecks. Therefore, an early estimation of an application's performance is a desirable development tool. However, out-of-order execution, superscalar instruction pipelines, as well as communication costs and (shared-) cache effects essentially influence the performance of parallel programs. While offering a good modeling and simulation speed, analytic models provide moderate prediction results so far. Virtual prototyping requires a time-consuming simulation, but produces better accuracy. Furthermore, even existing statistical methods often require detailed knowledge of the hardware for characterization. In this work, we present a concept and its evaluation for a statistical approach for performance prediction based on abstract runtime parameters, which describe an application's scalability behavior and can be extracted from profiles without user input. These scalability parameters not only include information on the interference of software demands and hardware capabilities, but indicate bottlenecks as well. Depending on the database setup, we achieve a competitive accuracy of 20 % mean prediction error (11 % median), which we also proof in a case study.

关键词： Performance prediction parallelization scalability MPSoC advanced driver-assistance systems

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Sample-efficient Reinforcement Learning in Robotic Table Tennis

Sample-efficient Reinforcement Learning in Robotic Table Ten...

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IEEE international conference on Robotics and Automation (ICRA)

作者： Jonas Tebbe Lukas Krauch Yapeng Gao Andreas Zell Cognitive Systems Group University of Tuebingen Tuebingen Germany

Reinforcement learning (RL) has achieved some impressive recent successes in various computer games and simulations. Most of these successes are based on having large numbers of episodes from which the agent can learn. In typical robotic applications, however, the number of feasible attempts is very limited. In this paper we present a sample-efficient RL algorithm applied to the example of a table tennis robot. In table tennis every stroke is different, with varying placement, speed and spin. An accurate return therefore has to be found depending on a high-dimensional continuous state space. To make learning in few trials possible the method is embedded into our robot system. In this way we can use a one-step environment. The state space depends on the ball at hitting time (position, velocity, spin) and the action is the racket state (orientation, velocity) at hitting. An actor-critic based deterministic policy gradient algorithm was developed for accelerated learning. Our approach performs competitively both in a simulation and on the real robot in a number of challenging scenarios. Accurate results are obtained without pre-training in under 200 episodes of training. The video presenting our experiments is available at https://***/uRAtdoL6Wpw.

关键词： Training Automation conferences Computational modeling Reinforcement learning Games Robots

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Reliability Optimization Under Severe Uncertainty for NoC Based architectures Using an Info-Gap Decision Approach

Reliability Optimization Under Severe Uncertainty for NoC Ba...

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Midwest Symposium on Circuits and systems (MWSCAS)

作者： Wenkai Guan Jinhua Zhang Cristinel Ababei Department of Electrical and Computer Engineering Marquette University

ISBN: (数字)9781728180588

ISBN: (纸本)9781728180595

Increased uncertainties in design parameters undermine the accuracy of the mapping of embedded applications to Network-on-Chip (NoC) based manycore architectures. In this paper, we attempt for the first time to apply the info-gap theory to uncertainty modeling in the context of embedded systems design. We first propose a novel info-gap based uncertainty-aware reliability model for NoC based manycore platforms. We then develop an uncertainty-aware solution to the problem of mapping in embedded systems. The solution is implemented as a computer program that can generate robust Pareto frontiers. simulation results indicate that the proposed info-gap based uncertainty-aware mapping generates Pareto frontiers that have significant differences from the ones obtained with a traditional deterministic approach. Identifying and quantifying these differences is an important first step towards the development of better mapping optimization processes in order to arrive to optimal rather than suboptimal solutions.

关键词： Uncertainty Optimization embedded systems Robustness Tools Reliability engineering

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Exploiting LabVIEW FPGA Socketed CLIP to Design and Implement Soft-Core Based Complex Digital architectures on PXI FPGA Target Boards 16

Exploiting LabVIEW FPGA Socketed CLIP to Design and Implemen...

引用

16th international conference on Synthesis, modeling, Analysis and simulation Methods and Applications to Circuit Design, SMACD 2019

作者： Sterpaio, Luca Dello Marino, Antonino Nannipieri, Pietro Fanucci, Luca Dept. of Information Engineering University of Pisa Pisa Italy

ISBN: (纸本)9781728112015

PXI FPGA Peripheral Modules by National Instruments are meant to be used in LabView even without any previous knowledge of Hardware Description Languages (HDL) and let users to hardware-accelerate their own test and measurement setups. However, designers fluent in HDL languages avoid such closed technology targets due to impossibility to include third-party designs or the needed over-effort to implement large and complex architectures into it, such as soft-core based systems. In this paper a partially automated workflow to benefit of the PXI environment allowing advanced HDL engineers to implement complex architectures is presented with reference to two successful use-case examples. © 2019 IEEE.

关键词： computer hardware description languages

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Prosthesis Controller-Hardware-in-the Loop simulation

Prosthesis Controller-Hardware-in-the Loop Simulation

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international conference on Control and Robots (ICCR)

作者： Mohamed Abdelhady Dan Simon Embedded Control Systems Research Laboratory Cleveland State University Cleveland Ohio USA

ISBN: (数字)9781728175621

ISBN: (纸本)9781728175638

This paper demonstrates the use of hardware-in-the-loop (HIL) simulation to mimic control action scenarios in an active prosthetic leg. The simulation is used to carry out a comparative assessment for model-based controllers such as computed torque, the Slotine and Li approach, and a regressor free approach using adaptive control based on the function approximation technique (FAT). The controller side comprises an embedded single-board computer (SBC) commanding a simulation computer. On the other side, the simulation computer runs a multibody model of a robotic setup that mimics hip motion. The HIL simulation shows that the adaptive FAT controller has better tracking with less control effort compared to the computed torque and Slotine controllers.

关键词： Legged locomotion Adaptation models Torque Computational modeling Fats Robots Prosthetics

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