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检索条件"任意字段=International Conference on Embedded Computer Systems -Architectures, Modeling and Simulation"
2878 条 记 录,以下是2811-2820 订阅
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Fault tolerance and reliable routing in augmented hypercube architectures
Fault tolerance and reliable routing in augmented hypercube ...
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international Phoenix conference on computers and Communications (IPCCC)
作者: M.S. Alam R. Melhem Dept. of Comput. Sci. Pittsburgh Univ. PA USA Department of Computer Science University of Pittsburgh Pittsburgh PA USA
Two schemes for augmenting hypercubes with spare nodes are presented. In both schemes, fault coverage is local in the sense that only the neighbors of the faulty nodes need to know about the faults. Routing in the pre... 详细信息
来源: 评论
Parallel processing and computational chemistry
Parallel processing and computational chemistry
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Annual international conference of the IEEE Engineering in Medicine and Biology Society (EMBC)
作者: P. Weiner Alliant Computer Systems Corporation Littleton MA USA
Summary form only given, as follows. With the increasing use of such methods as dynamic simulations, free energy perturbation and large-molecule ab initio calculations, chemical researchers find increasing frustration... 详细信息
来源: 评论
Experimentally based parallel architecture evaluation
Experimentally based parallel architecture evaluation
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IEEE Annual international computer Software and Applications conference (COMPSAC)
作者: S.A. Fineberg Parallel Processing Laboratory School of Electrical Engineering Purdue University West Lafayette IN USA
A technique for architectural evaluation that has been used with good results and that is applicable to most experimental and commercial machines is proposed. This technique is that of careful experimentation on a bar... 详细信息
来源: 评论
PARET;an integrated visual tool for the study of parallel systems
PARET;an integrated visual tool for the study of parallel sy...
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IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)
作者: K.M. Nichols J.T. Edmark System Architecture Research Department AT&T Bell Labaratories Holmdel NJ USA
PARET (Parallel Architecture Research and Evaluation Tool) is an object-oriented graphical environment for the study of parallel or multiprocessor systems that provides a laboratory for investigation of alternative ar... 详细信息
来源: 评论
EXIST: an interactive VLSI architectural environment
EXIST: an interactive VLSI architectural environment
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IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)
作者: P.S. van der Meulen M.-D. Huang U. Bar-Gadda E. Lee P. Baltus Signetics division of NAPC Philips Research Laboratories Sunnyvale CA USA
EXIST (Exploration in Smalltalk) is an integrated environment for exploratory VLSI architectural design implemented in the Smalltalk-80 environment. It consists of a functional simulator (INSIST), a floorplanner (FLOO... 详细信息
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Distributed simulation
Distributed simulation
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simulation Winter conference
作者: B.W. Unger Jade Simulations International Calgary AB Canada
Emerging multicomputer architectures provide a platform upon which to realize substantial performance improvements in simulation. Parallel execution is the means to these improvements, yet hurdles remain: the synchron... 详细信息
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APES: an integrated system for behavioral design, simulation and evaluation of array processors
APES: an integrated system for behavioral design, simulation...
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IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)
作者: F. Distante V. Pieuri Dept. of Electron. Politecnico di Milano Italy
The APES system for the design and evaluation of VLSI or WSI array processors is presented. APES makes it possible to study fault-tolerant array architectures and methodologies by simulating the behavior of the system... 详细信息
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A user's perspective on the state of parallel processing
A user's perspective on the state of parallel processing
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IEEE Annual international computer Software and Applications conference (COMPSAC)
作者: J.G. Kuhl Department of Electrical and Computer Engineering University of Iowa Iowa IA USA
The author describes his experience with the development of large-scale, highly parallel applications hosted on a variety of parallel processing architectures. He suggests that researchers should not become so caught ... 详细信息
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A probabilistic model for clock skew
A probabilistic model for clock skew
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Proceedings of the international conference on Systolic Arrays
作者: S.D. Kugelmass K. Steiglitz Department of Computer Science Princeton University Princeton NJ USA
A probabilistic model for the accumulation of clock skew in synchronous systems is presented. The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronou... 详细信息
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1987 PROCEEDINGS - FOURTH international IEEE VLSI MULTILEVEL INTERCONNECTION conference.
1987 PROCEEDINGS - FOURTH INTERNATIONAL IEEE VLSI MULTILEVEL...
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1987 Proceedings - Fourth international IEEE VLSI Multilevel Interconnection conference.
作者: Anon
The following topics are dealt with: fault-tolerant computers;associative processors and memories;defect-tolerant components;systolic array processors;signal processing architectures;emerging architectures;multiproces... 详细信息
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