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Fault tolerance and reliable routing in augmented hypercube architectures

Fault tolerance and reliable routing in augmented hypercube ...

引用

international Phoenix conference on computers and Communications (IPCCC)

作者： M.S. Alam R. Melhem Dept. of Comput. Sci. Pittsburgh Univ. PA USA Department of Computer Science University of Pittsburgh Pittsburgh PA USA

Two schemes for augmenting hypercubes with spare nodes are presented. In both schemes, fault coverage is local in the sense that only the neighbors of the faulty nodes need to know about the faults. Routing in the presence of faults is accomplished by distributed algorithms that deliver messages reliably to their destination nodes. A message destined to a faulty node will be delivered to the spare node that replaces the faulty node. Both node and link failures may be accommodated in both schemes, and because no switches are used for reconfiguration, there is no assumptions about fault-free switches. The two schemes differ in complexity of interconnections between the spare nodes and the original cube nodes. More complex interconnections result in more flexible coverage algorithms and thus, more reliable systems. However, increased flexibility increases the complexity of the routing algorithm because more care has to be given to the possibility of messages looping in cycles and never reaching their destinations. The reliability of the fault coverage schemes and the efficiency of the routing algorithms are evaluated from simulation results.< >

关键词： Fault tolerance Routing Hypercubes Switches computer architecture Degradation computer science Distributed algorithms Computational modeling Multiprocessing systems

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Parallel processing and computational chemistry

Parallel processing and computational chemistry

引用

Annual international conference of the IEEE Engineering in Medicine and Biology Society (EMBC)

作者： P. Weiner Alliant Computer Systems Corporation Littleton MA USA

Summary form only given, as follows. With the increasing use of such methods as dynamic simulations, free energy perturbation and large-molecule ab initio calculations, chemical researchers find increasing frustration in the use of conventional computers to solve their problems. These machines are either too slow or too expensive to be practical for everyday use. However, the advent of parallel computer architectures and parallel algorithms offers a solution to this problem. In addition, the development of tools that detect dependencies and automatically create concurrent code makes the programming of these machines accessible to everyone. The author discusses these tools and their application to widely used chemical codes, such as AMBER and GAUSSIAN. The use of high performance graphics machines in computational chemistry is also discussed. An application, simultaneously running AMBER and GRAMPS, and an analysis program is shown.

关键词： Parallel processing Concurrent computing Chemistry Chemicals Computational modeling computer simulation computer architecture Parallel algorithms Automatic programming Application software

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Experimentally based parallel architecture evaluation

Experimentally based parallel architecture evaluation

引用

IEEE Annual international computer Software and Applications conference (COMPSAC)

作者： S.A. Fineberg Parallel Processing Laboratory School of Electrical Engineering Purdue University West Lafayette IN USA

A technique for architectural evaluation that has been used with good results and that is applicable to most experimental and commercial machines is proposed. This technique is that of careful experimentation on a bare system, i.e. one without a resident kernel, operating system, or high-level language support. The experimentation involves the implementation of simple algorithms designed to utilize the basic features of the architecture and exploit its unique features. This technique makes possible the analysis of an architecture without the complexities introduced by most operating systems and compilers and can yield insight beneficial in future language, compiler, operating system, application, and system design. Hybrid SIMD/MIMD architectures are considered as an example.< >

关键词： Parallel architectures Operating systems Hardware Partitioning algorithms Parallel processing Laboratories computer architecture Computational modeling Analytical models computer simulation

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PARET;an integrated visual tool for the study of parallel systems

PARET;an integrated visual tool for the study of parallel sy...

引用

IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： K.M. Nichols J.T. Edmark System Architecture Research Department AT&T Bell Labaratories Holmdel NJ USA

PARET (Parallel Architecture Research and Evaluation Tool) is an object-oriented graphical environment for the study of parallel or multiprocessor systems that provides a laboratory for investigation of alternative architectural decisions and experiments with such issues as scheduling, mapping, and routing policies. PARET is unique in providing an animated interactive visual tool for parallel systems with a modeling paradigm that is closely linked to its graphical representation. Models have the same morphology regardless of the subsystem represented or the level of detail in the model. Presently, PARET runs on SUN workstations, using color graphics, mouse input, and pop-up menus to control and observe a simulation engine. Ongoing projects using PARET include evaluation of a special-purpose multiprocessor system and use of PARET in a system to create application-specific ICs for signal processing.< >

关键词： Object oriented modeling Multiprocessing systems Parallel architectures Routing Animation Morphology Sun Workstations Graphics Mice

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EXIST: an interactive VLSI architectural environment

EXIST: an interactive VLSI architectural environment

引用

IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： P.S. van der Meulen M.-D. Huang U. Bar-Gadda E. Lee P. Baltus Signetics division of NAPC Philips Research Laboratories Sunnyvale CA USA

EXIST (Exploration in Smalltalk) is an integrated environment for exploratory VLSI architectural design implemented in the Smalltalk-80 environment. It consists of a functional simulator (INSIST), a floorplanner (FLOORIST) and a database (DATABIST). EXIST contains several unique features including: editing while in simulation, manual and automated hierarchical floorplan optimization, and user-friendly interface based on the model-view controller paradigm of Smalltalk. These features make EXIST a promising environment for exploration of alternative VLSI architectures, such as RISC (reduced instruction-set computer) controllers.< >

关键词： Very large scale integration Object oriented modeling Circuit simulation Design automation Reduced instruction set computing Programming Spatial databases Automatic control Control systems Design optimization

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Distributed simulation

Distributed simulation

引用

simulation Winter conference

作者： B.W. Unger Jade Simulations International Calgary AB Canada

Emerging multicomputer architectures provide a platform upon which to realize substantial performance improvements in simulation. Parallel execution is the means to these improvements, yet hurdles remain: the synchronization of simulation time across multicomputer nodes and whether sufficient model parallelism can be identified to enable substantial speedup. Overcoming these obstacles will make speeding up the execution of simulations by several orders of magnitude practical. simulation environments of the future must build on traditional object-oriented methods and the new logic program paradigms in a way which does not hide the parallelism inherent in models. Distributed operating system kernals and language run-time systems must then be able to exploit this parallelism to support concurrent execution of simulations on multicomputers. Finally, these simulation kernels must support this parallelism transparently, that is, without modification at the model source code levels. Without this transparency, models will have to be continually re- written when moving from model develpment, testing, and validation on sequential hardware to parallel hardware for simulation experiments.

关键词： Object oriented modeling Computational modeling Parallel processing Synchronization Hardware computer architecture Clocks Kernel Sequential analysis computer simulation

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APES: an integrated system for behavioral design, simulation and evaluation of array processors

APES: an integrated system for behavioral design, simulation...

引用

IEEE international conference on computer Design: VLSI in computers and Processors, (ICCD)

作者： F. Distante V. Pieuri Dept. of Electron. Politecnico di Milano Italy

The APES system for the design and evaluation of VLSI or WSI array processors is presented. APES makes it possible to study fault-tolerant array architectures and methodologies by simulating the behavior of the system when faults occur: the type and distribution of faults can be defined by the designer. A diagnostic tool is integrated in APES to evaluate the fault-detection and error-correction capabilities of the system under observation. Another tool makes it possible to perform and evaluate the array reconfiguration after fault occurrence by adopting a user-defined strategy. Features including data entry (using a graphic editor or a hardware description language), the simulation engine, the fault injector, the diagnostic evaluator, and the restructuring/reconfiguration manager are discussed.< >

关键词： Design automation Graphics Performance evaluation Computational modeling Fault tolerance Fault tolerant systems Throughput Very large scale integration Algorithm design and analysis Logic arrays

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A user's perspective on the state of parallel processing

A user's perspective on the state of parallel processing

引用

IEEE Annual international computer Software and Applications conference (COMPSAC)

作者： J.G. Kuhl Department of Electrical and Computer Engineering University of Iowa Iowa IA USA

The author describes his experience with the development of large-scale, highly parallel applications hosted on a variety of parallel processing architectures. He suggests that researchers should not become so caught up in the search for general and consistent models and programming tools for parallel processing that they forsake the ability to tailor the processing resources of the system to the requirements of the problem, and vice versa. High-level abstractions that hide architectural details may obscure performance issues that are important to the algorithm design process. It is concluded that the parallel processing community does not need a single, uniform set of models, tools or paradigms to achieve success. All that is needed is the same sort of basic design and analysis tools that have served the sequential processing community for a number of years.< >

关键词： Parallel processing computer architecture Concurrent computing Mechanical systems Computational modeling Visualization Workstations Algorithm design and analysis computer simulation Parallel algorithms

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A probabilistic model for clock skew

A probabilistic model for clock skew

引用

Proceedings of the international conference on Systolic Arrays

作者： S.D. Kugelmass K. Steiglitz Department of Computer Science Princeton University Princeton NJ USA

A probabilistic model for the accumulation of clock skew in synchronous systems is presented. The model is used to derive upper bounds for expected skew and its variance, in tree distribution systems with N synchronously clocked processing elements. The results are applied to two specific models for clock distribution. In the first, which is called metric-free, the skew in a buffer stage is Gaussian with a variance independent of wire length. The second, metric, model, is intended to reflect VLSI constraints: the clock skew in a stage is Gaussian with a variance proportional to wire length, and the distribution tree is an H-tree embedded in the plane. Upper bounds on skew are obtained for both models. Estimates of the constants of proportionality as well as the asymptotic behavior have been obtained and verified by simulation.< >

关键词： Clocks Upper bound Wire Predictive models Solid modeling Topology Equations Timing computer science Very large scale integration

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1987 PROCEEDINGS - FOURTH international IEEE VLSI MULTILEVEL INTERCONNECTION conference.

1987 PROCEEDINGS - FOURTH INTERNATIONAL IEEE VLSI MULTILEVEL...

引用

1987 Proceedings - Fourth international IEEE VLSI Multilevel Interconnection conference.

作者： Anon

The following topics are dealt with: fault-tolerant computers;associative processors and memories;defect-tolerant components;systolic array processors;signal processing architectures;emerging architectures;multiprocessors;distributed systems;image processing architectures;logic and system simulation;circuit and interconnection simulation;hierarchical design and silicon compilers;logic synthesis and design languages;device modeling and simulation;testing;hardware accelerators;knowledge-based tools;WSI;packaging;physical design;automation and robotics;image processing and graphics;computer networks;parallel/multiprocessing systems;supercomputers;application-specific ICs;intelligent workstations;technology transfer;and reliabiity and maintainability. 251 papers were presented, of which 243 are published in full in the present proceedings, and 8 as abstracts only.

关键词： INTEGRATED CIRCUITS, VLSI

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