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检索条件"任意字段=International Conference on Embedded Computer Systems -Architectures, Modeling and Simulation"

共 2877 条记录，以下是21-30 订阅

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SafeFloatZone: Identify Safe Domains for Elementary Functions 24th

SafeFloatZone: Identify Safe Domains for Elementary Function...

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24th international conference on embedded computer systems: architectures, modeling, and simulation

作者： Krahl, Markus Guedemann, Matthias Wallentowitz, Stefan Hsch Munchen Univ Appl Sci Munich Germany TASKING Germany GmbH Munich Germany

ISBN: (纸本)9783031783760;9783031783777

Formal verification of embedded system software can profoundly influence both safety and security, and has the potential to alter the development process substantially. However, the complexity of formal verification, along with stringent time-to-market and resource constraints of embedded systems, has posed significant barriers to its adoption. Moreover, ensuring the accessibility of formal methods in the design and implementation of embedded systems remains a major challenge. In our paper, we evaluate formal methods and demonstrate the accessibility and benefits within a critical area of many industries: IEEE754 floating-point values are widely used and due to their fixed size, they can only approximate real numbers. For the most part, their behavior aligns with programmer expectations;however, certain corner cases exist in which they are susceptible to value cancellation, rounding errors, and deviations from standard mathematical rules. Such discrepancies can be problematic when calculated results diverge from software developer expectations, potentially leading to fatal errors. We propose SafeFloatZone which allows for the identification of safe domains for algorithms utilizing IEEE754 floating-point numbers. The approach is rooted in formal verification, leveraging modern, efficient Satisfiability Modulo Theories (SMT) solvers to deduce preconditions for functions, thereby providing stronger guarantees of correctness. In this work we demonstrate how SafeFloatZone can readily benefit embedded system developers and show that it is transferable to a variety of algorithms based on IEEE754 floating-point numbers.

关键词： embedded systems IEEE754 Floating-Point Formal Verification

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PMDI: An AI-Enabled Ecosystem for Cooperative Urban Mobility 24th

PMDI: An AI-Enabled Ecosystem for Cooperative Urban Mobility

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24th international conference on embedded computer systems: architectures, modeling, and simulation

作者： Fornaciari, William Agosta, Giovanni Fioravanti, Massimo Giuseppetti, Paolo Solinas, Alessandro Gallo, Luigi Pernigotto, Manuel Pedol, Mario Pro, Francesco Amerini, Irene Papa, Lorenzo Maiano, Luca Trovini, Giovanni Di Giamberardino, Mauro Satta, Paolo Politecn Milan Milan Italy Univ Roma La Sapienza Rome Italy Smart Interact Rome Italy Vodafone Automot Italia Italy

ISBN: (纸本)9783031783791;9783031783807

The PMDI project aims at radically improving the safety of urban mobility by extending STEP, an automotive data management and analytics platform, to support real-time and near-real-time use cases, particularly focusing on dangerous crossings at urban intersections. Such capabilities will be achieved by deploying STEP on Multi-access Edge Computing (MEC) hardware modules, and integrating within the platform fast AI video and image analytics as well as danger detection algorithms taking as inputs V2X messages from a variety of sources, including (virtual) on-board units and infrastructural sensors. To ensure that dangerous conditions are correctly learnt by AI algorithms, digital twins of the road sections under examination will be built leveraging domain specific language technologies designed to ease the integration.

关键词： Urban Mobility V2X Cooperative Cyber-physical systems AI video analytics

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It's All About PR Smart Benchmarking AI Accelerators Using Performance Representatives 24th

It's All About PR Smart Benchmarking AI Accelerators Using P...

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24th international conference on embedded computer systems: architectures, modeling, and simulation

作者： Jung, Alexander Louis-Ferdinand Steinmetz, Jannik Gietz, Jonathan Luebeck, Konstantin Bringmann, Oliver Univ Tubingen Embedded Syst Tubingen Germany

ISBN: (纸本)9783031783760;9783031783777

Statistical models are widely used to estimate the performance of commercial off-the-shelf (COTS) AI hardware accelerators. However, training of statistical performance models often requires vast amounts of data, leading to a significant time investment and can be difficult in case of limited hardware availability. To alleviate this problem, we propose a novel performance modeling methodology that significantly reduces the number of training samples while maintaining good accuracy. Our approach leverages knowledge of the target hardware architecture and initial parameter sweeps to identify a set of Performance Representatives (PR) for deep neural network (DNN) layers. These PRs are then used for benchmarking, building a statistical performance model, and making estimations. This targeted approach drastically reduces the number of training samples needed, opposed to random sampling, to achieve a better estimation accuracy. We achieve a Mean Absolute Percentage Error (MAPE) of as low as 0.02% for single-layer estimations and 0.68% for whole DNN estimations with less than 10 000 training samples. The results demonstrate the superiority of our method for single-layer estimations compared to models trained with randomly sampled datasets of the same size.

关键词： Performance Estimation Benchmarking AI Hardware Accelerators Statistical Modelling Deep Neural Networks

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NanoSoftController: A Minimal Soft Processor for System State Control in FPGA systems 24th

NanoSoftController: A Minimal Soft Processor for System Stat...

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24th international conference on embedded computer systems: architectures, modeling, and simulation

作者： Weissbrich, Moritz Seidlitz, Germain Paya-Vaya, Guillermo Tech Univ Carolo Wilhelmina Braunschweig Chair Chip Design Embedded Comp Muhlenpfordtstr 22-23 D-38106 Braunschweig Germany

ISBN: (纸本)9783031783760;9783031783777

In many FPGA-based systems, only sequential system control structures modeled by finite state machines are actually required. In order to deal with complexity, design time, and verification issues, which are weaknesses of traditional hardware description languages, it may be preferred to describe the control flow behaviorally in software. However, it is reported that high-level synthesis for FPGA often generates inferior results in terms of resources and performance when translating software-style control flow description to hardware. In this paper, the NanoSoftController is proposed as an open-source soft processor, which is optimized for minimal and efficient logic resource usage on FPGA platforms. It is targeted at processing sequential finite state machine functionality in software, featuring a compact ISA for control flow in embedded systems and a tiny accumulator-based data path. Furthermore, an efficient mapping of memory to small distributed LUT RAM instances enables its use as a system state machine controller in even very resource-constrained FPGA designs, requiring only 104 slice LUTs and 76 slice registers in total. However, despite all optimizations, in a case study with high-level synthesis results of three reference software-style control applications, i.e., electronic door lock, smart glucose sensor, and sequential sensor network node, a better resource efficiency could not be shown. We evaluate the negative results and provide lessons we learned from them.

关键词： Accumulator architecture FPGA High-level synthesis Microcontroller Programmable state machine Soft processor

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I2DS: FPGA-Based Deep Learning Industrial Intrusion Detection System 24th

I2DS: FPGA-Based Deep Learning Industrial Intrusion Detectio...

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24th international conference on embedded computer systems: architectures, modeling, and simulation

作者： Morianos, Ioannis Georgopoulos, Konstantinos Brokalakis, Andreas Kyriakakis, Thomas Ioannidis, Sotiris Tech Univ Crete Khania Greece Dienekes Iraklion Greece

ISBN: (纸本)9783031783791;9783031783807

The use of IoT systems in industrial environments provides tremendous benefits and economic value leading to an exponential rise in their adoption. Their extended use, however, does not come without concerns related to potential security threats, thereby creating an obstacle in their further use in the field. To address these security concerns, we introduce a specialized Industrial Intrusion Detection System (I2DS). Our proposed system merges the capabilities of deep learning (DL) with FPGA-based hardware acceleration techniques, enabling it to detect subtle anomalies and potential cyber threats that may evade conventional rule-based intrusion detection systems (IDS) in an effective way. More specifically, by implementing the system on FPGA hardware, we achieve low-latency, high-throughput processing of network traffic, essential for real-time intrusion detection in industrial settings. Our architecture is scalable and can be adapted according to network bandwidth requirements, while remaining lightweight, making it an ideal solution for the stringent resource constraints often encountered in IoT environments. The proposed solution has been validated with the modbus TON-IoT dataset, achieving up to two orders of magnitude higher performance compared to a software equivalent implementation.

关键词： Intrusion detection systems Deep learning Industrial environments Hardware Acceleration FPGA

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A Novel System simulation Framework for HBM2 FPGA Platforms 1

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24th international conference on embedded computer systems: architectures, modeling, and simulation

作者： Hernandez, Hector Gerardo Munoz Iskandar, Veronia Steiner, Lukas Holzinger, Philipp Jung, Matthias Goehringer, Diana Huebner, Michael Wehn, Norbert Reichenbach, Marc Brandenburg Univ Technol Cottbus Senftenberg Chair Comp Engn Cottbus Germany Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany Univ Kaiserslautern Landau Microelect Syst Design Kaiserslautern Germany Friedrich Alexander Univ Chair Comp Architecture Erlangen Germany Fraunhofer IESE Kaiserslautern Germany Univ Wurzburg Wurzburg Germany Univ Rostock Chair Integrated Syst Rostock Germany

ISBN: (数字)9783031783807

ISBN: (纸本)9783031783791;9783031783807

Every year, the disparity between processing power and memory bandwidth continues to expand. This well-established trend has been recognized for several years. Recently, innovative concepts have emerged to address and narrow this growing gap. One notable example of such technology is High Bandwidth Memory (HBM), which is specifically designed to tackle this challenge. HBM has a much higher throughput thanks to their wider data buses, making it an innovative solution for this problem. Due to its configurability and timing requirements, HBM and Field-Programmable Gate Arrays (FPGAs) offer a great combination for prototyping, and the hardware that includes both is slowly gaining popularity and accessibility. In this work, we introduce an open-source simulator capable of accurately predicting and modeling HBM based FPGA systems in a fast-prototyping manner. This design not only simulates an HBM but also a memory controller and a memory interconnect, like the one used by AMD/Xilinx. To prove accuracy, this work shows side-byside comparison between the real hardware and simulated benchmarks of different specific types of memory access patterns, where we measure an overall error of 9.91%. Finally, we compare the performance of some real-life applications where we report an average error of 2.72%.

关键词： High Bandwidth Memory Memory system simulation Approximately timed simulation

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Post Quantum Cryptography Research Lines in the Italian Center for Security and Rights in Cyberspace 24th

Post Quantum Cryptography Research Lines in the Italian Cent...

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24th international conference on embedded computer systems: architectures, modeling, and simulation

作者： Barenghi, Alessandro Pelosi, Gerardo Politecn Milan I-20133 Milan Italy

ISBN: (纸本)9783031783791;9783031783807

The Italian foundation for Security and Rights in Cyberspace (SERICS) is in charge of managing the current, broad range, research in a variety of computer security domains, ranging from strictly computer related aspects, such as OS and Virtualization security, to the development of new cryptographic techniques, up to tackling human, social and legal problems related to computer security and privacy. The SERICS project is founded by the Italian National Recovery and Resilience Plan (NRRP), which in turn receives funding from the EU - NextGenerationEU programme. The SERICS foundation is managing the STRIDE project, to tackle the aforementioned research challenges. In the context of the STRIDE projects, a cascade call was made to tackle specific aspects of the overall reseach challenges. The two-years AQuSDIT project, winner of the aforementioned cascade call, aims to tackle the current open problems in the digital identity realm, with a particular focus on resistance to quantum computer-based attacks, and ledger-based technologies for identification and supply chain tracking. In this context, the research activities at Politecnico di Milano focus on the design of post quantum cryptosystems, and their secure and efficient realization as hardware components, either in the form of full accelerators, or support to existing computing infrastructures. In the following, we will present an overview of the research activities of the 2-year AQuSDIT project, together with an outlook on the first research results which have been obtained by the group of participants from Politecnico di Milano.

关键词： computer security Cryptography Post quantum cryptography

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RV-VP²: Unlocking the Potential of RISC-V Packed-SIMD for embedded Processing 24th

RV-VP<SUP>2</SUP>: Unlocking the Potential of RISC-V Packed-...

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24th international conference on embedded computer systems: architectures, modeling, and simulation

作者： Ali, Muhammad Aliagha, Ensieh Elnashar, Mahmoud Goehringer, Diana Tech Univ Dresden Chair Adapt Dynam Syst Dresden Germany

ISBN: (纸本)9783031783791;9783031783807

The RISC-V instruction set architecture (ISA) is increasingly gaining traction as an open-source standard, enabling the development of a variety of processor designs. These designs are capable of addressing a broad spectrum of application needs, spanning from embedded systems to high-performance computing. The RISC-V ISA features a modular structure, offering a selection of base ISAs and standardized extensions for customization. In this work, we present the first and open-source extension of a SystemC TLM-based RISC-V Virtual Prototype (VP) which supports the RISC-V "P" Packed-SIMD Version 0.9.11-draft-20211209 called RV-VP2. The RISC-V VP is an open-source simulation platform in SystemC TLM that supports RV32GC and RV64GC. The RISC-V VP is extended for the P-extension of the RISC-V for RV32 specification to focus on simulating embedded application scenarios. A total of 243 instructions are added in the RISC-V VP simulator, which belongs to the mandatory specification of P-extension for RV32. The extended RISC-V VP simulator is evaluated for different test cases;matrix multiplication, convolution, max-pooling, and fully connected layer, to demonstrate the efficiency of P-extension in comparison to base ISA. A convolution neural network called Lenet-5 is also used as a test case to compare performance with the base RV32IM. The results show a maximum speed-up of 5.87x and 2.97x when using P-extension for a 4-way (8-bit) SIMD and a 2-way (16-bit) SIMD for matrix multiplication respectively. For Lenet-5 a speed-up of 4.08x when using P-extension (4-way (8-bit) SIMD) was observed.

关键词： RISC-V VP Instruction Set Architecture SystemC TLM Simulator Machine Learning Deep Learning

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Open Source Software Randomisation Framework for Probabilistic WCET Prediction on Multicore CPUs, GPUs and Accelerators 24th

Open Source Software Randomisation Framework for Probabilist...

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24th international conference on embedded computer systems: architectures, modeling, and simulation

作者： Kosmidis, Leonidas Maria Trompouki, Matina Lopez Castillon, Pau Rufart Blasco, Eric Fernandez Salgado, Javier Jung, Andreas Barcelona Supercomp Ctr BSC Barcelona Spain Univ Politecn Catalunya UPC Barcelona Spain European Space Agcy ESA Noordwijk Netherlands

ISBN: (纸本)9783031783791;9783031783807

High criticality space systems frequently have real-time requirements. Therefore, it is important to be able to compute the Worst Case Execution Time (WCET) of its software. However, with the complexity of modern processor architectures, it is very difficult to compute the WCET with traditional methods, such as static timing analysis or measurement based solutions. Recently, a novel timing analysis method was introduced, known as Measurement Based Probabilistic Timing Analysis (MBPTA). A unique characteristic of MBPTA compared to traditional methods is that it produces a Probabilistic WCET (pWCET) which instead of a single overestimated value is a curve that associates execution times with probabilities which can reach arbitrary low values (e.g. 10(-14)). MBPTA simplifies the estimation of pWCET by simply requiring the collection of execution times which are independent and identically distributed (i.i.d.). However, this property is not satisfied in conventional hardware and software systems. Special hardware designs have been proposed which provide hardware-based time-randomisation, including a probabilistic version of Cobham Gaisler's LEON3 as well as software solutions in the form of software randomisation. However, existing software randomisation methods only support CPUs, are very restrictive (i.e. support only ANSI C) and more importantly are not open source. This limits significantly the applicability of these methods in space, although ESA has supported in the past activities related to MBPTA hardware and software (P4S-PROARTIS for Space and EFL-Eviction Frequency Limitation). In this ESA-funded project, we implement an open source, qualifiable software randomisation tool which will be able to software randomise code for CPUs, including multicores as well as GPUs, which to our knowledge are not amenable to any WCET solution.

关键词： Real-time systems Worst Cased Execution Time (WCET) Open Source Source-to-source Compiler Measurement Based Probabilistic Timing Analysis (MBPTA) Software Randomisation

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modeling a microprocessor with RISC architecture

Modeling a microprocessor with RISC architecture

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2024 international conference Automatics and Informatics, ICAI 2024

作者： Varbov, Ilian Minev, Petar Dinev, Matyo Kukenska, Valentina Technical University-Gabrovo Computer Systems and Technologies Gabrovo Bulgaria

ISBN: (纸本)9798350353907

Microprocessors with RISC architecture are widely used in various fields, including mobile devices, embedded systems, and high-performance computing. They are an essential component of computer systems. The selection of a suitable microprocessor architecture is required in the automated design and implementation of various computer configurations. This makes the development of various computer models of microprocessors *** (Reduced Instruction Set computer) is an architectural approach to processor design that is characterized by the use of a small set of simple and fast instructions. The main idea behind this approach is to simplify the processor hardware, allowing more instructions to be executed in less time. Microprocessors with RISC architectures are optimized for performance by:•Use of fixed instruction length.•Maintaining a large set of registers for fast data access.•Avoidance of complex operations and instructions that execute slowly.•Using techniques such as pipelining to improve *** this report, the developed Verilog model of a microprocessor with RISC architecture is presented. A description of the modeled architecture and the Verilog models of its building blocks is made. The Vivado development environment and its built-in visual simulation tools were used for model *** is a hardware description language. It allows the description of the structure and behavior of digital systems at different levels of abstraction: logical, behavioral and register level. This makes it a convenient and appropriate tool in the process of designing and verifying integrated circuits, as well as computer system components. © 2024 IEEE.

关键词： embedded systems

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