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检索条件"任意字段=International Conference on Embedded Computer Systems -Architectures, Modeling and Simulation"

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Towards the Performance Analysis of Elastic systems with e-Motions 15th

Towards the Performance Analysis of Elastic Systems with e-M...

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15th international conference on Software Engineering and Formal Methods (SEFM)

作者： de Oliveira, Patricia Araujo Duran, Francisco Pimentel, Ernesto Univ Malaga Malaga Spain

ISBN: (纸本)9783319747811;9783319747804

We use graph transformation to define an adaptive component model, what allows us to carry on predictive analysis of dynamic architectures through simulations. Specifically, we build on an e-Motions definition of the Palladio component model, and then specify adaptation mechanisms as generic adaptation rules. We show how the simulation based analysis available in such a static definition can be extended in order to use the collected information on metrics such as response time, throughput and resource usage to adapt to the workload of the system and the environmental conditions. We illustrate our approach with rules modeling the scale in and out of servers, fired in response to the violation of specified constraints on the usage of resources. We evaluate this scenario by analyzing its performance, and discuss on its consequences in practice.

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System simulation with gem5 and SystemC The Keystone for Full Interoperability 17

System Simulation with gem5 and SystemC The Keystone for Ful...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Menard, Christian Castrillon, Jeronimo Jung, Matthias Wehn, Norbert Tech Univ Dresden Dresden Germany Fraunhofer IESE Kaiserslautern Germany Univ Kaiserslautern Kaiserslautern Germany

ISBN: (纸本)9781538634370

SystemC TLM based virtual prototypes have become the main tool in industry and research for concurrent hardware and software development, as well as hardware design space exploration. However, there exists a lack of accurate, free, changeable and realistic SystemC models of modern CPUs. Therefore, many researchers use the cycle accurate open source system simulator gem5, which has been developed in parallel to the SystemC standard. In this paper we present a coupling of gem5 with SystemC that offers full interoperability between both simulation frameworks, and therefore enables a huge set of possibilities for system level design space exploration. Furthermore, we show that the coupling itself only induces a relatively small overhead to the total execution time of the simulation.

关键词： Time-varying systems Time-domain analysis Couplings Timing Protocols Hardware Industries Time domain analysis Couplings time-varying systems computer hardware execution time systems simulation protocols industries coupling Interoperability Space Exploration keystone

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Energy-Efficient Scheduling of Throughput-Constrained Streaming Applications by Periodic Mode Switching 17

Energy-Efficient Scheduling of Throughput-Constrained Stream...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Niknam, Sobhan Stefanov, Todor Leiden Univ Leiden Inst Adv Comp Sci Leiden Netherlands

ISBN: (纸本)9781538634370

In this paper, we address the problem of energy reduction when scheduling streaming applications with throughput constraints on homogeneous multiprocessor systems with voltage and frequency scaling capability. We propose a novel periodic scheduling framework which allows streaming applications to switch their execution periodically between a few energy-efficient schedules at run-time in order to meet a throughput constraint at long run. Using such periodic switching, we can benefit from adopting Dynamic Voltage and Frequency Scaling (DVFS) techniques to exploit available static slack time in the schedule of an application efficiently. The experimental results, on a set of real-life streaming applications, show that our novel scheduling approach can achieve up to 68% energy reduction depending on the application and the throughput constraint compared to related approaches.

关键词： energy conservation multiprocessing systems power aware computing processor scheduling scheduling power aware computing Energy conservation Multiprocessing systems scheduling of multiprocessor Energy efficiency Streaming Throughput homogeneous multiprocessor

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Modelled, simulation and Design of Collecting Grid of Stray Currents in Slab Track in DC Electrified Railway systems

Modelled, Simulation and Design of Collecting Grid of Stray ...

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2018 IEEE international conference on Electrical systems for Aircraft, Railway, Ship Propulsion and Road Vehicles and international Transportation Electrification conference, ESARS-ITEC 2018

作者： Coves, Jordi Aguilar, Jose Sanchez Rull-Duran, Joan Electric Traction Technology IDOM Barcelona Spain MEP Department IDOM Bilbao Spain Electrical Department UPC Barcelona Spain

ISBN: (纸本)9781538641927

The stray currents are the fraction of traction return current returning by earth in at grade configurations, or by metallic structures (reinforcement bars) in case of viaducts and tunnels. These currents expose steel reinforcement bars to corrosion. The obvious alternative to minimize the risk of corrosion is to minimize the stray current, using insulation sleeper insulating pads and insulated bolts in fastener blocks. However, due to mechanic wearing by train operation, aging, or accumulation of waste, the level of insulation between rail and structures decreases with time, which increases the stray currents. A common palliative method for this is to install a Stray Current Collector (SCC), a conductive grid or mat, embedded in the concrete structure below the rails. The SCC can be connected to earth and to return circuit in different ways. The objectives of the paper are to get a model of leakage resistances including the SCC system, to determine the effectiveness of SCC and the best connection scheme. © 2018 IEEE.

关键词： Insulation

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DVFS-Enabled Power-Performance Trade-Off in MPSoC SW Application Mapping 17

DVFS-Enabled Power-Performance Trade-Off in MPSoC SW Applica...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Onnebrink, Gereon Walbroel, Florian Klimt, Jonathan Leupers, Rainer Ascheid, Gerd Murillo, Luis Gabriel Schurmans, Stefan Chen, Xiaotao Harn, YwhPyng Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silexica GmbH Cologne Germany Huawei Technol Co Ltd Bridgewater NJ USA

ISBN: (纸本)9781538634370

Heterogeneous MPSoCs are seen as the solution to tackle performance and power demands in the embedded domain. Their HW and SW complexity necessitates an automatic approach to find the most efficient task-to-processor mapping of parallel applications. Tight power budgets require efficient task mapping, and optimally setting the voltage and frequency of each processor. This paper proposes a novel heuristic that minimises the average power consumption, while meeting performance constraints. Integrated into an industrial SW mapping framework, the applicability is validated using three different case studies and representative benchmarks. Moreover, the power-performance trade-off is discussed. A comparison with the optimal solution complements the evaluation, revealing a loss of 19% by the heuristic, but 700x faster execution.

关键词： Power demand Task analysis Optimization Benchmark testing Switches Leakage currents Clocks Benchmark testing Power demand task analysis Timing devices Switches leakage currents Leakage currents power budget MAPPING(MATHEMATICAL) tradeoffs Heuristics

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Pipelined FPGA coprocessor for Elliptic Curve Cryptography based on Residue Number System 17

Pipelined FPGA coprocessor for Elliptic Curve Cryptography b...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Matutino, Pedro Miguens Araujo, Juvenal Sousa, Leonel Chaves, Ricardo INESC ID ISEL IPL Lisbon Portugal Univ Lisbon INESC ID IST Lisbon Portugal

ISBN: (纸本)9781538634370

In this paper a novel pipelined FPGA coprocessor for ECC is proposed, exploiting the parallelism capabilities of RNS to the computation of large operand algorithms. This intrinsic characteristic of representing large integer numbers as a set of smaller and independent values allows for the parallelization of the computationally heavy large operand multiplications, required in asymmetrical cryptographic algorithms. Towards a compact and performance efficient design, the RNS coprocessor supports a single highly pipelined multi-modulo arithmetic unit. Implementation results, on FPGA of this RNS based ECC coprocessor, suggest one of the smallest programmable designs with a proportional performance when compared with related state of the art. Additionally, the resulting architecture allows for the computation of varying key sizes without changing the design or its implementation.

关键词： Elliptic curve cryptography Coprocessors computer architecture Field programmable gate arrays Encryption Elliptic curves Elliptic curve cryptography Coprocessors Field programmable gate arrays residue number systems computer Architecture Elliptic curves cryptography state of the art EMERGENCY CONTROL CENTERS Error correction codes

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Can a reconfigurable architecture beat ASIC as a CNN accelerator? 17

Can a reconfigurable architecture beat ASIC as a CNN acceler...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Jafri, Syed M. A. H. Hemani, Ahmed Stathis, Dimmitrios Royal Inst Technol KTH Stockholm Sweden

ISBN: (纸本)9781538634370

To exploit the high accuracy, inherent redundancy, and embarrassingly parallel nature of Convolutional Neural Networks (CNN), for intelligent embedded systems, many dedicated CNN accelerators have been presented. These accelerators are optimized to employ compression, tiling, and layer merging for a specific data flow/parallelism pattern. However, the dimension of a CNN differ widely from one application to another (and also from one layer to another). Therefore, the optimal parallelism and data flow pattern also differs significantly in different CNN layers. An efficient accelerator should have flexibility to not only efficiently support different data flow patterns but also to interleave and cascade them. To achieve this ability requires configuration overheads. This paper analyzes whether the reconfiguration overheads for interleaving and cascading multiple data flow and parallelism patterns are justified. To answer this question, we first design a reconfigurable CNN accelerator, called ReCon. ReCon is the compared with state-of-the-art accelerators. Post-layout synthesis results reveal that ReCon provides up to 2.2X higher throughput and up to 2.3X better energy efficiency at the cost of 26-35% additional area.

关键词： Kernel Parallel processing Random access memory Convolution Merging Feature extraction computer architecture random access machine merger computer Architecture PARALLEL PROCESSING (computerS) Convolution data flow Feature extraction Kernel Accelerators Reconfigurable architectures one layer

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Network/System Co-simulation for Design Space Exploration of IoT Applications 17

Network/System Co-Simulation for Design Space Exploration of...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Zhao, Zhuoran Tsoutsouras, Vasileios Soudris, Dimitrios Gerstlauer, Andreas Univ Texas Austin Austin TX 78712 USA Natl Tech Univ Athens Athens Greece

ISBN: (纸本)9781538634370

With the growing complexity and scale of future Internet of Things (IoT) applications, there is a need for effectively exploring associated design spaces. IoT applications make use of inherently distributed processing. In such networks-of-systems (NoS), computation and communication is tightly coupled. Traditional design of networks and systems in isolation ignores how choices in one influence the other, and approaches for joint network/system co-exploration are lacking. In this paper, we propose a novel prototyping platform to enable comprehensive NoS design space exploration. Fast and accurate host-compiled system models are combined with a standard network simulator to provide a unified network/system co-simulation framework. Furthermore, detailed models of network interfaces and protocol stacks are integrated into host-compiled system and OS models to allow accurately capturing of network and system interactions. We apply our NoS simulator to two case studies from smart camera and healthcare application domains, and we demonstrate benefits and opportunities for exploration and optimization in network/system co-design. Results indicate that, depending on application, network and system configurations, application throughput can vary by an average of 26%, while device core utilization can vary by as much as 130%. These results confirm strong network and system interactions that could not be observed or optimized without novel co-simulation tools.

关键词： Task analysis Measurement Protocols Data models Kernel Hardware Computational modeling task analysis data models Space Exploration Computational modeling protocols computer hardware Kernel Network design Network interfaces Smart cameras network simulator

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Shallow Water Waves on a Deep Technology Stack: Accelerating a Finite Volume Tsunami Model Using Reconfigurable Hardware in Invasive Computing 1

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23rd international conference on Parallel and Distributed Computing (Euro-Par)

作者： Poeppl, Alexander Damschen, Marvin Schmaus, Florian Fried, Andreas Mohr, Manuel Blankertz, Matthias Bauer, Lars Henkel, Jorg Schroeder-Preikschat, Wolfgang Bader, Michael Tech Univ Munich Dept Informat Boltzmannstr 3 D-85748 Garching Germany Karlsruhe Inst Technol Dept Informat Kaiserstr 12 D-76131 Karlsruhe Germany Friedrich Alexander Univ Erlangen Nurnberg FAU Dept Comp Sci 4 Martensstr 1 D-91058 Erlangen Germany

ISBN: (数字)9783319751788

ISBN: (纸本)9783319751788;9783319751771

Reconfigurable architectures are commonly used in the embedded systems domain to speed up compute-intensive tasks. They combine a reconfigurable fabric with a general-purpose microprocessor to accelerate compute-intensive tasks on the fabric while the general-purpose CPU is used for the rest of the workload. Through the use of invasive computing, we aim to show the feasibility of this technology for HPC scenarios. We demonstrate this by accelerating a proxy application for the simulation of shallow water waves using the i-Core, a reconfigurable processor that is part of the invasive computing multiprocessor system-on-chip. Using a floating-point custom instruction, the entire computation of numerical fluxes occurring in the application's finite volume scheme is performed by hardware accelerators.

关键词： Invasive computing High Performance Computing Tsunami simulation Reconfigurable processor Resource-aware computing

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Virtual Environment for Developing Real-Time Image Processing for Vehicle Control 17

Virtual Environment for Developing Real-Time Image Processin...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Kitrungrotsakul, Yuranan Tanaka, Kiyofumi Hashimoto, Masanobu Onishi, Shuichi Japan Adv Inst Sci & Technol Sch Informat Sci Nomi Japan WITZ Corp Kyoto Japan

ISBN: (纸本)9781538634370

Virtual prototyping is an alternative way to simulate the real product without the physical object. The product is created in simulator before making a physical prototype. In this research, a vehicle controller is the target system for prototyping. The vehicle navigation system is the target program to execute in a vehicle controller system. One of critical factors in a vehicle controller is response time. Thus, this paper aims to create the virtual prototype with real response time for a vehicle controller. The hardware accelerators are used to improve system performance. The hardware accelerators are implemented into two bases, which are GPU and programmable logic (PL). In addition, the overclocking method is applied to increase the operating speed in GPU hardware accelerator. The result from improvement is evaluated in terms of execution time per frame, which is the metric for measurement of the ability of real-time response. To achieve real-time response, the execution time per frame must be below 33.33 ms. The GPU based version achieves run-time response by running at 14.43 ms per frame. The PL based version runs at 16.332 ms per frame, which achieves run-time response.

关键词： virtual prototype hardware accelerator GPU programmable logic embedded system

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