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Algorithmic and memory optimizations on multiple application mapping onto FPGAs 17

Algorithmic and memory optimizations on multiple application...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Sidiropoulos, Harry Koutras, Ioannis Soudris, Dimitrios Siozios, Kostas Natl Tech Univ Athens Sch Elect & Comp Engn Zografos Greece Aristotle Univ Thessaloniki Dept Phys Thessaloniki Greece

ISBN: (纸本)9781538634370

Field Programmable Gate Arrays (FPGAs) offer a low power flexible accelerator alternative due to their inherent parallelism. Reprogrammability, although its their key feature, it is used almost exclusively on design time due to the constrains imposed by the modern CAD tools that require even days to run and tens of GB of RAM. In order to effectively utilize FPGAs on run time we propose a novel methodology and the supporting toolflow that enable efficient mapping of multiple applications onto heterogeneous FPGAs. With the use of a floorplanning step, memory optimizations and custom memory allocators, we alleviate the constrains imposed by CAD tools, and provide a proof of concept that application mapping onto FPGAs can be done on run time. Experimental results prove the efficiency of the introduced solution, as we achieve application's mapping 40x faster on average compared to a state-of-art approach, without performance degradation and with 12x on average reduced memory usage.

关键词： Field programmable gate arrays Tools Kernel Random access memory Memory management Optimization Hardware Field programmable gate arrays random access machine Store management computer hardware Mapping onto Runtime Kernel Memory Memory design year

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An event-based Network-on-Chip debugging system for FPGA-based MPSoCs 17

An event-based Network-on-Chip debugging system for FPGA-bas...

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17th international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2017

作者： Ul Hasan Khan, Habib Rettkowski, Jens Eldafrawy, Mohamed Gohringer, Diana Application-Specific Multi-Core Architectures Group Ruhr-University Bochum Germany German University in Cairo Egypt Chai. of Adaptive Dynamic Systems Technische Universität Dresden Germany

ISBN: (纸本)9781538634370

Nowadays, Multiprocessor systems-on-Chip (MPSoCs) have high computation power due to the parallel processing using multiple processing elements (PEs). However, the communication costs increase with the number of PEs. Networks-on-Chip (NoCs) are the most promising solution for addressing the communication issues. This paper discusses the implementation of a user interactive NoC debugger. The system consists of two main parts;an on-chip hardware debugging system and an off-chip C++based computer application. The data debugging is transaction based and allows fault detection and reliable data analysis such as data logging, utilization report and dataflow visualization. The NoC debugger was implemented on a runtime reconfigurable and adaptive routable NoC and tested with a traffic generation technique. © 2017 IEEE.

关键词： Field programmable gate arrays (FPGA)

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RACOS: Transparent Access and Virtualization of Reconfigurable Hardware Accelerators 17

RACOS: Transparent Access and Virtualization of Reconfigurab...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Vatsolakis, Charalampos Pnevmatikatos, Dionisios Tech Univ Crete Sch Elect & Comp Engn Khania Greece Fdn Res & Technol Hellas Inst Comp Sci Iraklion Greece

ISBN: (纸本)9781538634370

Crafting accelerators using reconfigurable hardware is a promising way to achieve improved performance and power/energy efficiency. However, deploying reconfigurable accelerators is still cumbersome as it involves overall system integration issues and and runtime reconfigurable resource management. We describe the design and implementation of RACOS, a Reconfigurable ACcelerator OS, that provides a simple and intuitive software interface to load/unload reconfigurable hardware accelerators and perform data I/Os transparently to the user. Multiple partially reconfigurable regions are supported, and each region can host either single- or dual-threaded accelerators, effectively virtualizing the reconfigurable resources. RACOS allows multiple applications to use one or more accelerators each, and schedules accelerators for execution according to four policies: simple and inorder that respect the order of request, and out of order and forced that aim to reduce the number of reconfigurations. We evaluate our proposed system varying the number of instances of an accelerated application and show that, despite its generality, RACOS can achieve both high reconfiguration and data communication throughput, close to the maximum reported in bibliography, with a very small resource cost comparable or better than the current state of the art.

关键词： Hardware Software Field programmable gate arrays Throughput Acceleration Libraries Linux Field programmable gate arrays Accelerators hardware accelerator Linux reconfigurable hardware Throughput computer hardware acceleration Libraries computer software Virtualization configurability systems Integration software interface

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Balanced Application-Specific Processor System for Efficient SIFT-Feature Detection 17

Balanced Application-Specific Processor System for Efficient...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Hartig, Julian Paya-Vaya, Guillermo Mentzer, Nico Blume, Holger Leibniz Univ Hannover Inst Microelect Syst Appelstr 4 D-30167 Hannover Germany

ISBN: (纸本)9781538634370

Due to its computational complexity, the Scale-Invariant Feature Transform (SIFT) algorithm poses a challenge for use in embedded applications. To meet real-time at low power, hardware acceleration is necessary. This paper presents an FPGA-based balanced processor system for real-time SIFT feature detection, containing a dedicated hardware coprocessor coupled to a custom VLIW soft-core processor using a FIFO memory. The coprocessor calculates the scale-space and performs the extrema detection for the extraction of feature candidates, whereas the VLIW soft-core processor performs sub-pixel localization and stability checks to get stable SIFT-features. The system achieves a peak frame rate of up to 338 fps on 1,024x376 px images at less than 3 W on a Xilinx Virtex-6 FPGA. The filters within the Gaussian pyramid operate in a time-multiplexed scheme on clock frequencies up to 400 MHz. Furthermore, this paper presents a comprehensive design space exploration, evaluating architectural performance, hardware resources and power consumption trade-offs as well as exposing performance-balanced and pareto-optimal design variants.

关键词： Feature extraction Hardware Field programmable gate arrays Coprocessors VLIW Throughput Real-time systems Field programmable gate arrays Coprocessors Very long instruction word computer hardware real-time systems Feature extraction Throughput PROCESSOR feature detections soft-core

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The Design Space of the Number Theoretic Transform: a Survey 17

The Design Space of the Number Theoretic Transform: a Survey

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Valencia, Felipe Khalid, Ayesha O'Sullivan, Elizabeth Regazzoni, Francesco USI ALaRI Lugano Switzerland QUB CSIT Belfast North Ireland

ISBN: (纸本)9781538634370

The Number Theoretic Transform (NTT) is a necessary part of most Lattice-based cryptographic schemes. In particular, it offers an efficient means to achieve polynomial multiplication within the more efficient ring-based schemes. The NTT is also a crucial component which needs to be implemented in a critical way, since it is often the bottle-neck and the most resource consuming block of the whole design. As a result, the NTT is an appealing target for exploring different architectures and design trade-offs. In this paper, we compare various optimization strategies applied to maximize the performance or to reduce the resource utilization. Our analysis covers general purpose processors as well as dedicated hardware implemented on reconfigurable platforms and on ASIC. Previously explored design strategies range from the traditional computation where the multiplicative factors (called twiddle factors) are calculated on-the-fly versus memory trade-off exploration (using memory to store pre-computed twiddle factors), to the use of different butterfly designs for implementing the Fast Fourier Transform and its inverse in software, or the sharing of resources for hardware implementations of the forward and inverse NTT. The problem of side channel resistance is also addressed, discussing designs which are robust against power analysis attacks.

关键词： Cryptography Hardware Discrete Fourier transforms Lattices Software Resistance discrete Fourier transform computer hardware cryptography crystal lattices computer software Resource utilization computer programs Transform power analysis Inverse

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An Efficient End-to-End Channel Level Pruning Method for Deep Neural Networks Compression

An Efficient End-to-End Channel Level Pruning Method for Dee...

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IEEE international conference on Software Engineering and Service Sciences (ICSESS)

作者： Lei Zeng Shi Chen Sen Zeng Department of Computer Science University of Science and Techonology of China Hefei Anhui Province China Department of Gree Electric Appliances Zhuhai Guangdong Province China

ISBN: (数字)9781728109459

ISBN: (纸本)9781728109466

Deep neural networks (DNNS) have obtained compelling performance among many visual tasks by a significant increase in the computation and memory consumption, which severely impede their applications on resource-constrained systems like smart mobiles or embedded devices. To solve these problems, recent efforts toward compressing DNNS have received increased focus. In this paper, we proposed an effective end-to-end channel pruning approach to compress DNNS. To this end, firstly, we introduce additional auxiliary classifiers to enhance the discriminative power of shallow and intermediate layers. Secondly, we impose Ll-regularization on the scaling factors and shifting factors in batch normalization (BN) layer, and adopt the fast and iterative shrinkage-thresholding algorithm (FISTA) to effectively prune the redundant channels. Finally, by forcing selected factors to zero, we can prune the corresponding unimportant channels safely, thus obtaining a compact model. We empirically reveal the prominent performance of our approach with several state-of-theart DNNS architectures, including VGGNet, and MobileNet, on different datasets. For instance, on cifar10 dataset, the pruned MobileNet achieves 26. 9x reduction in model parameters and 3. 9x reduction in computational operations with only 0.04% increase of classification error.

关键词： Training Neural networks Classification algorithms Acceleration Hardware Iterative methods Computational modeling

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Enhancing Sensor Capabilities of Open-Source simulation Tools to Support Autonomous Vehicles Safety Validation

Enhancing Sensor Capabilities of Open-Source Simulation Tool...

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37th international conference on computer Safety, Reliability, and Security (SAFECOMP)

作者： Molina, C. B. S. T. Vismari, L. F. Fuji, T. Camargo, J. B., Jr. de Almeida, J. R., Jr. Inam, R. Fersman, E. Hata, A. Marquezini, M. V. Univ Sao Paulo Sch Engn Sao Paulo SP Brazil Ericsson AB Ericsson Res Stockholm Sweden Ericsson Telecomunicacoes SA Indaiatuba SP Brazil

ISBN: (纸本)9783319992297;9783319992280

Autonomous Vehicles (AVs) are expected to provide relevant benefits to the society in terms of safety, efficiency and accessibility. However, AVs are safety-critical systems, and it is mandatory to assure that they are going to be safe when operating on public roads. However, the safety of AV is still an open, and challenging issue. A combination of simulation, test track, and on-road testing approaches is being recommended to validate the AV safety performance. Testing AVs in real-world scenarios is a widely used, but neither an efficient nor a safe approach to validate safety. Therefore, simulation-based approaches are demanded. Motivated by this challenge, we have developed a simulation-based safety analysis framework, based on open-source tools, to be applied to the future of the road transportation systems. However, the open-source tools we have adopted for the framework have limitations to model real-world elements, especially perception sensors. We thus here present the extensions made to these open-source tools, focused on the development of a perception sensor model in the native OpenDS tool, which enables detecting obstacles around the vehicle, considering the same main characteristics observed in Radar and LiDAR sensors. As the main conclusion, these tools enhancements have improved the simulation based safety analysis framework capabilities for modeling, simulating and analyzing -in a more precise way and for safety validation purposes - the behavior of AV in simulated traffic scenarios when different embedded detection sensor characteristics are considered in its deployment.

关键词： Autonomous vehicle Safety simulation OpenDS Sensor

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SPynq: Acceleration of Machine Learning Applications over Spark on Pynq 17

SPynq: Acceleration of Machine Learning Applications over Sp...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Kachris, Christoforos Koromilas, Elias Stamelos, Ioannis Soudris, Dimitrios NTUA Inst Commun & Comp Syst ICCS Athens Greece Natl Tech Univ Athens Dept Elect & Comp Engn Athens Greece

ISBN: (纸本)9781538634370

Spark is one of the most widely used frameworks for data analytics that offers fast development of applications like machine learning and graph computations in distributed systems. In this paper, we present SPynq: A framework for the efficient utilization of hardware accelerators over the Spark framework on heterogeneous MPSoC FPGAs, such as Zynq. Spark has been mapped to the Pynq platform and the proposed framework allows the seamlessly utilization of the programmable logic for the hardware acceleration of computational intensive Spark kernels. We have also developed the required libraries in Spark that hides the accelerator's details to minimize the design effort to utilize the accelerators. A cluster of 4 nodes (workers) based on the all-programmable MPSoCs has been implemented and the proposed platform is evaluated in a typical machine learning application based on logistic regression. The logistic regression kernel has been developed as an accelerator and incorporated to the Spark. The developed system is compared to a high-performance Xeon cluster that is typically used in cloud computing. The performance evaluation shows that the heterogeneous accelerator-based MpSoC can achieve up to 2.3x system speedup compared with a Xeon system (with 90% accuracy) and 20x better energy-efficiency. For embedded application, the proposed system can achieve up to 40x speedup compared to the software only implementation on low-power embedded processors and 30x lower energy consumption.

关键词： Sparks Hardware Program processors Libraries Machine learning Field programmable gate arrays Cloud computing Field programmable gate arrays Program processors sparks Cloud Computing computer hardware Artificial Intelligence Machine Learning Libraries Accelerators design effort Performance Evaluation hardware accelerator

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Thermal Characterization of Next-Generation Workloads on Heterogeneous MPSoCs 17

Thermal Characterization of Next-Generation Workloads on Het...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Iranfar, Arman Terraneo, Federico Simon, William Andrew Dragic, Leon Piljic, Igor Zapater, Marina Fornaciari, William Kovac, Mario Atienza, David Swiss Fed Inst Technol Lausanne Embedded Syst Lab Lausanne Switzerland Politecn Milan Dipartimento Elettron Informaz & Bioingegneria Milan Italy Univ Zagreb Fac Elect Engn & Comp Zagreb Croatia

ISBN: (纸本)9781538634370

Next-generation High-Performance Computing (HPC) applications need to tackle outstanding computational complexity while meeting latency and Quality-of-Service constraints. Heterogeneous Multi-Processor systems-on-Chip (MPSoCs), equipped with a mix of general-purpose cores and reconfigurable fabric for custom acceleration of computational blocks, are key in providing the flexibility to meet the requirements of next-generation HPC. However, heterogeneity brings new challenges to efficient chip thermal management. In this context, accurate and fast thermal simulators are becoming crucial to understand and exploit the trade-offs brought by heterogeneous MPSoCs. In this paper, we first thermally characterize a next-generation HPC workload, the online video transcoding application, using a highly-accurate Infra-Red (IR) microscope. Second, we extend the 3D-ICE thermal simulation tool with a new generic heat spreader model capable of accurately reproducing package surface temperature, with an average error of 6.8% for the hot spots of the chip. Our model is used to characterize the thermal behaviour of the online transcoding application when running on a heterogeneous MPSoC. Moreover, by using our detailed thermal system characterization we are able to explore different application mappings as well as the thermal limits of such heterogeneous platforms.

关键词： Transcoding Heating systems Thermal management Heat sinks Streaming media Thermal sensors Quality of service transcoding THERMAL SENSOR Streaming Video Heating systems heat sinks Thermal management Quality of service High Performance Computing infrared microscopy Workload

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Exposed Datapath Optimizations for Loop Scheduling 17

Exposed Datapath Optimizations for Loop Scheduling

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Kultala, Heikki O. Jaaskelainen, Pekka O. IJzerman, Johannes Lehtonen, Lasse K. Viitanen, Timo T. Makitalo, Markku J. Takala, Jarmo H. Tampere Univ Technol Tampere Finland

ISBN: (纸本)9781538634370

Transport Triggered Architecture (TTA) processors allow unique low level compiler optimizations such as software bypassing and operand sharing. Previously, these optimizations have mostly been performed inside single basic blocks, leaving much of their potential unused. In this work, software bypassing and operand sharing are integrated with loop scheduling, allowing optimizations over loop iteration boundaries. This considerably further reduces register file accesses and immediate value transfers on tight loops - in some cases even eliminating all register file accesses from the loop body. In the benchmarked 12 small loops, compared to traditional VLIW-style processors, on average 63% of register file reads and 77% of register file writes could be eliminated. Compared to a compiler which performs these optimizations only inside a basic block, on average 58% of register file reads, 28% of register file writes could be eliminated. The additional register access reductions allow both direct energy savings from fewer register accesses and indirect energy savings by allowing the use of simpler register files with less read and write ports and a simpler interconnect network with less transport buses.

关键词： Registers Program processors Optimization VLIW Processor scheduling computer architecture

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