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检索条件"任意字段=International Conference on Embedded Computer Systems -Architectures, Modeling and Simulation"

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Hard Edges: Hardware-Based Control-Flow Integrity for embedded Devices 21st

Hard Edges: Hardware-Based Control-Flow Integrity for Embedd...

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21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Christou, George Vasiliadis, Giorgos Athanasopoulos, Elias Ioannidis, Sotiris Fdn Res & Technol Hellas FORTH ICS Iraklion Greece Univ Cyprus Nicosia Cyprus Tech Univ Crete TUC ECE Khania Greece

ISBN: (纸本)9783031045806;9783031045790

Control-Flow Integrity (CFI) is a popular technique to defend against State-of-the-Art exploits, by ensuring that every (indirect) control-flow transfer points to a legitimate address and it is part of the Control-flow Graph (CFG) of a program. Enabling CFI in real systems is not straightforward, since in many cases the actual CFG of a program can only be approximated. Even in the case where there is perfect knowledge of the CFG, ensuring that all return instructions will return to their actual call sites, without employing a shadow stack, is questionable. In this work, we explore the implementation of a full-featured CFI-enabled Instruction Set Architecture (ISA) on actual hardware. Our new instructions provide the finest possible granularity for both intra-function and inter-function Control-Flow Integrity. We implement hardware-based CFI (HCFI) by modifying a SPARC SoC and evaluate the prototype on an FPGA board by running SPECInt benchmarks instrumented with a fine-grained CFI policy. HCFI can effectively protect applications from code-reuse attacks, while adding less than 1% average runtime and 2% power consumption overhead, making it particularly suitable for embedded systems.

关键词： System-on-chip

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The Dataflow Abstract Machine Simulator Framework 51

The Dataflow Abstract Machine Simulator Framework

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ACM/IEEE 51st Annual international Symposium on computer Architecture (ISCA)

作者： Zhang, Nathan Lacouture, Rubens Sohn, Gina Mure, Paul Zhang, Qizheng Kjolstad, Fredrik Olukotun, Kunle Stanford Univ Stanford CA 94305 USA MIT 77 Massachusetts Ave Cambridge MA 02139 USA

ISBN: (纸本)9798350326598;9798350326581

The growing interest in novel dataflow architectures and streaming execution paradigms has created the need for a simulator optimized for modeling dataflow systems. To fill this need, we present three new techniques that make it feasible to simulate complex systems consisting of thousands of components. First, we introduce an interface based on Communicating Sequential Processes which allows users to simultaneously describe functional and timing characteristics. Second, we introduce a scalable point-to-point synchronization scheme that avoids global synchronization. Finally, we demonstrate a technique to exploit slack in the simulated system, such as FIFOs, to increase simulation parallelism. We implement these techniques in the Dataflow Abstract Machine (DAM), a parallel simulator framework for dataflow systems. We demonstrate the benefits of using DAM by highlighting three case studies using the framework. First, we use DAM directly as an exploration tool for streaming algorithms on dataflow hardware. We simulate two different implementations of the attention algorithm used in large language models, and use DAM to show that the second implementation only requires a constant amount of local memory. Second, we re-implement a simulator for a sparse tensor algebra accelerator, resulting in 57% less code and a simulation speedup of up to four orders of magnitude. Finally, we demonstrate a general technique for time-multiplexing real hardware to simulate multiple virtual copies of the hardware using DAM.

关键词： Dataflow Accelerators modeling Parallel Discrete Event simulation

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RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors 21st

RVfplib: A Fast and Compact Open-Source Floating-Point Emula...

引用

21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Perotti, Matteo Tagliavini, Giuseppe Mach, Stefan Bertaccini, Luca Benini, Luca Swiss Fed Inst Technol Gloriastr 35 CH-8092 Zurich Switzerland Univ Bologna Viale Risorgimento 2 I-40136 Bologna Italy

ISBN: (纸本)9783031045806;9783031045790

Small, low-cost IoT devices rely on floating-point (FP) software emulation on 32-bit integer cores when the cost of a full-fledged FPU is not affordable. Thus, the performance and code size of the FP emulation library are decisive for meeting energy and memory-size constraints. We propose RVfplib, the first ISA-optimized open-source library for single and double-precision IEEE 754 FP emulation on RV32IM[C] cores. RVfplib is 59% smaller and 2x faster than the GCC emulation library, on average. On benchmark programs, code size reduction is 39%, and performance boost 1.5x. RVfplib is 5.3% smaller than the leading closed-source RISC-V commercial library.

关键词： RISC-V embedded IoT Floating-point Library Size Performance

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NanoController: A Minimal and Flexible Processor Architecture for Ultra-Low-Power Always-On System State Controllers 22nd

NanoController: A Minimal and Flexible Processor Architectur...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Weissbrich, Moritz Paya-Vaya, Guillermo Tech Univ Carolo Wilhelmina Braunschweig Chair Chip Design Embedded Comp Muhlenpfordtstr 22-23 D-38106 Braunschweig Germany

ISBN: (纸本)9783031150746;9783031150739

Distributed nodes in IoT and wireless sensor networks, which are powered by small batteries or energy harvesting, are constrained to very limited energy budgets. By intelligent power management and power gating strategies for the main microcontroller of the system, the energy efficiency can be significantly increased. However, timer-based, periodical power-up sequences are too inflexible to implement these strategies, and the use of a programmable power management controller demands minimum area and ultra-low power consumption from this system part itself. In this paper, the NanoController processor architecture is proposed, which is intended to be used as a flexible system state controller in the always-on domain of smart devices. The NanoController features a compact ISA, minimal silicon area and power consumption, and enables the implementation of efficient power management strategies in comparison to much simpler and constrained always-on timer circuits. For a power management control application of an electronic door lock, the NanoController is compared to small state-of-the-art controller architectures and has up to 86% smaller code size and up to 92% less silicon area and power consumption for 65 nm standard cell ASIC implementations.

关键词： Instruction-set architecture Processor architecture Ultra-low-power microcontroller

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Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PANACA-Based Approach to simulation and modeling 23rd

Unlocking the Potential of RISC-V Heterogeneous MPSoC: A PAN...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Haase, Julian Ali, Muhammad Göhringer, Diana Chair of Adaptive Dynamic Systems Technische Universität Dresden Dresden Germany Technische Universität Dresden Dresden Germany

ISBN: (纸本)9783031460760

Very early in the hardware development lifecycle, highly abstract simulations are essential to evaluate the performance and functionality of complex designs before they are implemented physically. For Multi-Processor System-on-Chip (MPSoC) designs that incorporate Network-on-Chip (NoC) architectures and RISC-V processors, such simulation platforms are needed. In this work, we extend and combine the PANACA simulation platform with a RISC-V Virtual Prototype to create a highly efficient and flexible MPSoC simulation platform written in SystemC-TLM. This simulation platform is capable of running a variety of applications, e.g. machine learning application, and can even support the use of real-time operating systems such as FreeRTOS. The developed memory mapped network adapters with and without interrupt support provide a seamless interface between the RISC-V processors and the NoC and enables efficient communication between the components via a unified API. This API is written in such a way that the application that uses it can be applied to simulation and hardware without the need to change the application code. Our novel simulation platform has undergone extensively testing against diverse use cases, hardware implementation, and experimental simulations, establishing its accuracy and reliability as an invaluable tool for early-stage hardware development and research. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Network-on-chip

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High-Level Synthesis of Digital Circuits from Template Haskell and SDF-AP 22nd

High-Level Synthesis of Digital Circuits from Template Haske...

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22nd international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Folmer, H. H. de Groote, R. Bekooij, M. J. G. Univ Twente CAES Comp Architectures Embedded Syst Enschede Netherlands Sax Hogesch Enschede Netherlands

ISBN: (纸本)9783031150746;9783031150739

Functional languages as input specifications for HLS-tools allow to specify data dependencies but do not contain a notion of time nor execution order. In this paper, we propose a method to add this notion to the functional description using the dataflow model SDF-AP. SDF-AP consists of patterns that express consumption and production that we can use to enforce resource usage. We created an HLS-tool that can synthesize parallel hardware, both data and control path, based on the repetition, expressed in Higher-Order Functions, combined with specified SDF-AP patterns. Our HLS-tool, based on Template Haskell, generates an Abstract Syntax Tree based on the given patterns and the functional description uses the Clash-compiler to generate VHDL/Verilog. Case studies show consistent resource consumption and temporal behavior for our HLS-tool. A comparison with a commercially available HLS-tool shows that our tool outperforms in terms of latency and sometimes in resource consumption. The method and tool presented in this paper offer more transparency to the developer and allow to specify more accurately the synthesized hardware compared to what is possible with pragmas of the Vitis HLS-tool.

关键词： High level synthesis

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Exploring Multi-core systems with Lifetime Reliability and Power Consumption Trade-offs 23rd

Exploring Multi-core Systems with Lifetime Reliability and P...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Sapra, Dolly Pimentel, Andy D. University of Amsterdam Amsterdam Netherlands

ISBN: (纸本)9783031460760

embedded multicore systems are often built for a specific application, operating a combination of homogeneous and heterogeneous cores. These devices are often deployed for a long term and therefore system lifetime reliability is an important consideration while designing them. In principle, placing extra cores increases the lifetime reliability albeit at the cost of increased power consumption and chip area. We propose a framework to explore platform architectures and their floorplans, highlighting the trade-offs between lifetime reliability and power consumption. The framework is based on a Genetic Algorithm and employs a high level simulator to calculate the Mean Time to Failure (MTTF) of the chip. The simulator runs multiple times, also called Monte Carlo simulation, to take the averages of both failure times and power usage. The high number of simulations required makes the framework compute intensive. We therefore propose two variations of the design space exploration to reduce the number of simulations. Our results show that total number of simulations is reduced by ≈30% and the total GA convergence time by ≈55%, while the resulting floorplan designs are similar in their characteristics across all exploration varieties. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Electric power utilization

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Micro-architecture and Control Electronics simulation of Modular Color Center-Based Quantum computers 23rd

Micro-architecture and Control Electronics Simulation of Mod...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Ronde, Folkert de Dreef, Matti Wong, Stephan Elkouss, David Delft University of Technology Delft Netherlands Okinawa Institute of Science and Technology Graduate University Onna Japan

ISBN: (纸本)9783031460760

In the world of quantum computing, developments of electronics needed to control (a) qubit(s) rapidly follow one another. Consequently, (micro-)architectures need to be defined to ultimately build control logic. In this paper, we present the (micro-)architecture of a quantum computer based on nitrogen-vacancy (NV) centers in diamonds and a comprehensive simulator capable of mimicking all related (electronic) components as well as quantum operations. We demonstrate that, using our simulator (utilizing noiseless models), we can correctly emulate past (physical) experiments carried out prior to the definition of our architecture. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Computation theory

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Examining The Performance of Sense Amplifiers for In-Memory Computing systems

Examining The Performance of Sense Amplifiers for In-Memory ...

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2024 IEEE international conference on modeling, simulation and Intelligent Computing, MoSICom 2024

作者： Kumar, Sreeja S Nayak, Jagadish Bits Pilani Dubai Campus Dept. of Electrical&Electronics Engineering Dubai United Arab Emirates

ISBN: (纸本)9798331533311

The principle of in-memory computing offers a highly promising framework that may effectively tackle the discrepancy between memory and computing, leading to exceptionally fast and energy-efficient data processing. The sense amplifier serves a vital role in the realm of in-memory computer architectures. The effectiveness and energy efficiency of in-memory computing systems are heavily reliant on the suitability of their sense amplifiers. This paper offers a comprehensive insight into the main goal of pinpointing sense amplifiers designed specifically for in-memory computing applications. It involves an examination of the requisites and inherent challenges linked to in-memory computing. This encompasses various factors, such as delay, energy efficiency, and resilience to process changes. A careful examination was conducted to analyze the intricate trade-offs associated with power consumption, energy efficiency, and processing speed. The considerations play a pivotal function in providing designers with the essential knowledge and confidence to proficiently include sense amplifiers into diverse in-memory computing systems. This paper presents a systematic approach to selecting and constructing sense amplifiers to enhance our understanding of in-memory computing. We tailor our approach to match the distinct requirements of different inmemory computing applications. The results gained are anticipated to have a substantial influence on the progression of memory-centric computing systems in the forthcoming years. © 2024 IEEE.

关键词： Memory architecture

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DD-MPU: Dynamic and Distributed Memory Protection Unit for embedded System-on-Chips 23rd

DD-MPU: Dynamic and Distributed Memory Protection Unit for E...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Heinz, Carsten Koch, Andreas Embedded Systems and Applications Group TU Darmstadt Darmstadt Germany

ISBN: (纸本)9783031460760

The integration of potentially untrustworthy intellectual property (IP) blocks into a System-on-Chip (SoC) poses significant risks, including data exfiltration and corruption due to unauthorized writes to memory or peripheral devices. Conventional countermeasures, such as memory protection or management units, tend to provide coarse protection granularity and impose substantial hardware overhead for embedded devices. In this paper, we introduce DD-MPU, a custom memory protection unit specifically designed for individual third-party IPs. Our proposed solution features low area overhead and fine protection granularity while automatically adapting to dynamic system states by actively monitoring bus transfers and switching between different protection rules. In our evaluation, we demonstrate the efficacy of the DD-MPU by integrating it into an SoC to isolate a potentially malicious accelerator block from the rest of the system. The area overhead of our approach for a single instance in a 22 nm technology ASIC node is a mere 0.3%. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： System-on-chip

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