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检索条件"任意字段=International Conference on Embedded Computer Systems -Architectures, Modeling and Simulation"

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A configurable SIMD architecture with explicit datapath for intelligent learning 16

A configurable SIMD architecture with explicit datapath for ...

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16th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2016

作者： He, Yifan Peemen, Maurice Waeijen, Luc Diken, Erkan Fiumara, Mattia Rauwerda, Gerard Corporaal, Henk Geng, Tong Xiamen University of Technology China Eindhoven University of Technology Netherlands Recore Systems B.V. Netherlands

ISBN: (纸本)9781509030767

The use of a wide Single-Instruction-Multiple-Data (SIMD) architecture is a promising approach to build energy-efficient high performance embedded processors. In this paper, based on our design framework for low-power SIMD processors, we propose a multiply-accumulate (MAC) unit with variable number of accumulator registers. The proposed MAC unit exploits both the merits of merged operation and register tiling. A Convolutional Neural Network (CNN) is a popular learning based algorithm due to its flexibility and high accuracy. However, a CNN-based application is often computationally intensive as it applies convolution operations extensively on a large data set. In this work, a CNN-based intelligent learning application is analyzed and mapped in the context of SIMD architectures. Experimental results show that the proposed architecture is efficient. In a 64-PE instance, the proposed SIMD processor with MAC4reg achieves an effective performance of 63.2 GOPS. Compared to the two baseline SIMD processors without MAC4reg, the proposed design brings 54.0% and 32.1% reduction in execution time, and 20.5% and 35.1% reduction in energy consumption respectively. © 2016 IEEE.

关键词： Energy utilization

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Power Models Supporting Energy-Efficient Co-Design on Ultra-Low Power embedded systems

Power Models Supporting Energy-Efficient Co-Design on Ultra-...

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international conference on embedded computer systems - architectures, modeling and simulation (SAMOS)

作者： Vi Ngoc-Nha Tran Barry, Brendan Phuong Hoai Ha UiT Arctic Univ Norway Dept Comp Sci Tromso Norway Movidius Ltd Dublin Ireland

ISBN: (纸本)9781509030767

The energy efficiency of computing systems can be enhanced via power models that provide insights into how the systems consume power. However, there are no application general, fine-grained and validated power models which can provide insights into how a given application running on an ultra-low power (ULP) embedded system consumes power. In this study, we devise new fine-grained power models that provide insights into how a given application consumes power on an ULP embedded system. The models support architecture application co-design by considering both platform and application properties. The models are validated with data from 35 micro-benchmarks and three application kernels, namely dense matrix multiplication, sparse matrix vector multiplication and breadth first search, on Movidius Myriad, an ultra-low power embedded system. The absolute percentage errors of the model are at most 8.5% for micro-benchmarks and 12% for application kernels. Based on the models, we propose a framework predicting when to apply race-to-halt (RTH) strategy (i.e., running an application with a maximum setting) to a given application. For the three validated application kernels, the proposed framework is able to predict when to use RTH and when not to use RTH precisely. The experimental results show that the prediction of our new RTH framework is accurate and we can save up to 61% energy for dense matrix multiplication, 59% energy for sparse matrix vector multiplication by using RTH and 5% energy for breadth first search by not using RTH.

关键词： Mathematical model Computational modeling Data transfer embedded systems Kernel Low-power electronics Data models embedded systems powered models low-power electronics data transmission data models Computational modeling Kernel Energy sources Mathematical Model Matrix multiplication Energy efficiency Seeds ULP Co-design Power (Psychology)

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Power models supporting energy-efficient co-design on ultra-low power embedded systems 16

Power models supporting energy-efficient co-design on ultra-...

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16th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2016

作者： Tran, Vi Ngoc-Nha Barry, Brendan Ha, Phuong Hoai Department of Computer Science UiT the Arctic University of Norway Tromso Norway Movidius Ltd. Dublin Ireland

ISBN: (纸本)9781509030767

The energy efficiency of computing systems can be enhanced via power models that provide insights into how the systems consume power. However, there are no application-general, fine-grained and validated power models which can provide insights into how a given application running on an ultra-low power (ULP) embedded system consumes power. In this study, we devise new fine-grained power models that provide insights into how a given application consumes power on an ULP embedded system. The models support architecture-application co-design by considering both platform and application properties. The models are validated with data from 35 micro-benchmarks and three application kernels, namely dense matrix multiplication, sparse matrix vector multiplication and breadth first search, on Movidius Myriad, an ultra-low power embedded system. The absolute percentage errors of the model are at most 8.5% for micro-benchmarks and 12% for application kernels. Based on the models, we propose a framework predicting when to apply race-to-halt (RTH) strategy (i.e., running an application with a maximum setting) to a given application. For the three validated application kernels, the proposed framework is able to predict when to use RTH and when not to use RTH precisely. The experimental results show that the prediction of our new RTH framework is accurate and we can save up to 61% energy for dense matrix multiplication, 59% energy for sparse matrix vector multiplication by using RTH and 5% energy for breadth first search by not using RTH. © 2016 IEEE.

关键词： Energy efficiency

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Preface

International Conference on Perspective Technologies and Met...

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international conference on Perspective Technologies and Methods in MEMS Design 2018年 VII-VIII页

作者： Lobur, Mykhaylo Computer Aided Design Department Lviv Polytechnic National University Ukraine

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A modeling and Verification Approach to the Design of Distributed IMA architectures using TTEthernet 7

A Modeling and Verification Approach to the Design of Distri...

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7th international conference on Ambient systems, Networks and Technologies (ANT) / 6th international conference on Sustainable Energy Information Technology (SEIT)

作者： Robati, Tiyam Gherbi, Abdelouahed Mullins, John Ecole Technol Super Dept Software & IT Engn Montreal PQ Canada Ecole Polytech Montreal Dept Comp & Software Engn Montreal PQ Canada

Integrated Modular Avionics (IMA) architectures complemented with Time-Triggered Ethernet (TTEthernet) provides a strong platform to support the design and deployment of distributed avionic software systems. The complexity of the design and continuous integration of such systems can be managed using a model-based methodology. In this paper, we build on top of our extension of the AADL modeling language to model TTEthernet-based distributed systems and leverage model transformations to enable undertaking the verification of the system models produced with this methodology. In particular, we propose to transform the system models to a model suitable for a simulation with DEVS. We illustrate the proposed approach using an example of a navigation and guidance system and we use this example to show the verification of the contention-freedom property of TTEthernet schedule. (C) 2016 The Authors. Published by Elsevier B.V.

关键词： Integrated Modular Avionics TTEthernet Model transformation Verification DEVS simulation

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EdgeCloudSim: An environment for performance evaluation of Edge Computing systems

EdgeCloudSim: An environment for performance evaluation of E...

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international conference on Fog and Mobile Edge Computing (FMEC)

作者： Cagatay Sonmez Atay Ozgovde Cem Ersoy Bogazici Universitesi Istanbul TR Department of Computer Engineering Bogazici University Istanbul Turkey

ISBN: (纸本)9781538628607

Edge Computing is a fast growing field of research covering a spectrum of technologies such as Cloudlets, Fog Computing and Mobile Edge Computing (MEC). Edge Computing involves technically more sophisticated setup when compared with the pure Cloud Computing and pure Mobile Computing cases since both computational and network resources should be considered simultaneously. In that respect, it provides a larger design space with many parameters rendering a variety of novel approaches feasible. Given the complexity, Edge Computing designs deserve scientific scrutiny for sound assessment of their feasibility. However, despite increasing research activity, this field lacks a simulation tool compatible with the requirements. Starting from available simulators a significant programming effort is required to obtain a simulation tool meeting the actual needs. To decrease the barriers, a new simulator tool called EdgeCloudSim streamlined for Edge Computing scenarios is proposed in this work. EdgeCloudSim builds upon CloudSim to address the specific demands of Edge Computing research and support necessary functionality in terms of computation and networking abilities. To demonstrate the capabilities of EdgeCloudSim an experiment setup based on different edge architectures is simulated and the effect of the computational and networking system parameters on the results are depicted.

关键词： Cloud computing Computational modeling Edge computing Load modeling Delays Wide area networks computer architecture

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Implications of non-volatile memory as primary storage for database management systems 16

Implications of non-volatile memory as primary storage for d...

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16th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2016

作者： Mustafa, Naveed Ul Armejach, Adria Ozturk, Ozcan Cristal, Adrian Unsal, Osman S. Computer Engineering Department Bilkent University Ankara Turkey Barcelona Supercomputing Center Barcelona Spain

ISBN: (纸本)9781509030767

Traditional Database Management System (DBMS) software relies on hard disks for storing relational data. Hard disks are cheap, persistent, and offer huge storage capacities. However, data retrieval latency for hard disks is extremely high. To hide this latency, DRAM is used as an intermediate storage. DRAM is significantly faster than disk, but deployed in smaller capacities due to cost and power constraints, and without the necessary persistency feature that disks have. Non-Volatile Memory (NVM) is an emerging storage class technology which promises the best of both worlds. It can offer large storage capacities, due to better scaling and cost metrics than DRAM, and is non-volatile (persistent) like hard disks. At the same time, its data retrieval time is much lower than that of hard disks and it is also byte-addressable like DRAM. In this paper, we explore the implications of employing NVM as primary storage for DBMS. In other words, we investigate the modifications necessary to be applied on a traditional relational DBMS to take advantage of NVM features. As a case study, we have modified the storage engine (SE) of PostgreSQL enabling efficient use of NVM hardware. We detail the necessary changes and challenges such modifications entail and evaluate them using a comprehensive emulation platform. Results indicate that our modified SE reduces query execution time by up to 40% and 14.4% when compared to disk and NVM storage, with average reductions of 20.5% and 4.5%, respectively. © 2016 IEEE.

关键词： Dynamic random access storage

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Hardware-in-the-loop testbed for load management applications

Hardware-in-the-loop testbed for load management application...

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international conference on Clean Electrical Power (ICCEP)

作者： Sepehr Nakhostin Sergio Moreno Rodríguez Massimo Belometti Luca Omati Politecnico di Milano Milan Italy Electrification Products ABB Bergamo Italy

ISBN: (纸本)9781509046836

This paper focuses on smart power management systems for application in the Low Voltage power distribution. In particular, we consider load management systems based on distributed control implemented by processors embedded in power circuit breakers: such systems can control connection and disconnection of loads with the purpose of maintaining average power within preset boundaries, preventing demand peaks. With the purpose of testing load management systems in a realistic condition, a real time, hardware in the loop testbed has been designed and built. The testbed employs a mathematical model of the electrical consumption of the installation: based on such model, real time, simulated current and voltage signals are generated, that the controller uses as measurement inputs. Based on such inputs, the controller trigger load activation and deactivation strategy. In turn, activation and deactivation commands are fed back into the simulation testbed and taken into account for the continuation of simulation, thus closing the loop. The simulation system includes a complete graphical operator interface, which can be used for demonstration and training purposes, so that performance and operation of load management systems can be made apparent. After describing the architecture and components of the designed system, a test case used for validation is shown.

关键词： Load management Circuit breakers Load modeling Power demand User interfaces Voltage measurement computer architecture

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Real-time benchmark set synthesis based on pWCET estimation and bounded hyper-periods

Real-time benchmark set synthesis based on pWCET estimation ...

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international conference on Circuits, System and simulation (ICCSS)

作者： Ashraf Suyyagh Zeljko Zilic Department of Electrical and Computer Engineering McGill University Montreal QC Canada

ISBN: (纸本)9781538603932

In evaluating performance, schedulability, and energy efficiency metrics for real-time systems, numerous algorithms have been proposed to construct synthetic tasksets for simulation. The resulting taskset characteristics should ideally reflect real workloads while the algorithms generating these tasksets should be efficient. Any experimentation using these tasksets will highly depend on their properties. Current approaches construct the sets by choosing taskset periods and utilisation from statistical distributions and compute the task worst case execution times accordingly. Tasks are generated through timed loops or matrix operations up to the specified task WCET. At times, the taskset hyper-period is bounded to minimise simulation interval through selected assignment of task periods. However, tasks which burn processor cycles through loops and matrix operations do not always reflect realistic task loads. In this paper, we propose a methodology for generating realistic tasksets based on available embedded benchmarks. We extend on previous work and propose new algorithms: CPA-AU/DU (Compute-Propagate-Adjust Ascending/Descending Utilisation) which efficiently pair taskset WCETs with selected discrete periods. Our tasksets have bounded and feasible simulation interval and meet desired total utilisation with minimum digression errors. We also show that our algorithms run in polynomial time.

关键词： Computational modeling Estimation Real-time systems Benchmark testing Hardware Timing Probabilistic logic

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Data centres for IoT applications: The M2DC approach (Invited paper) 16

Data centres for IoT applications: The M2DC approach (Invite...

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16th international conference on embedded computer systems: architectures, modeling and simulation, SAMOS 2016

作者： Oleksiak, Michal Kierzynka Ariel Agosta, Giovanni Brandolese, Carlo Fornaciari, William Pelosi, Gerardo Vor Dem Berge, Micha Christmann, Wolfgang Krupop, Stefan Cecowski, Mariano Plestenjak, Robert Cinkelj, Justin Porrmann, Mario Hagemeyer, Jens Griessl, Rene Peykanu, Meysam Tigges, Lennart Cudennec, Loic Goubier, Thierry Philippe, Jean-Marc Rosinger, Sven Schlitt, Daniel Pieper, Christian Adeniyi-Jones, Chris Janssen, Udo Ceva, Luca Poznan Supercomputing and Networking Center ul. Noskowskiego 10 Poznan61-704 Poland DEIB - Politecnico di Milano Piazza Leonardo da Vinci 32 Milano Italy Christmann Informationstechnik + Medien GmbH and Co. KG Ilseder Huette 10c Ilsede31241 Germany XLAB D.o.o. Pot za Brdom 100 Ljubljana1000 Slovenia Cognitronics and Sensor Systems Group CITEC Bielefeld University Germany CEA LIST PC 172 Gif-sur-Yvette Cedex91191 France OFFIS E.V. - Institute for Information Technology Germany ARM Ltd. CPC-1 Capital Park Fulbourn CambridgeCB21 5XE United Kingdom CEWE Stiftung and Co. KGaA Germany Vodafone Telematics United Kingdom

ISBN: (纸本)9781509030767

The Modular Microserver DataCentre (M2DC) project investigates, develops and demonstrates a modular, highly-efficient, cost-optimized server architecture composed of heterogeneous micro server computing resources, being able to be tailored to meet requirements from various application domains, including the Internet of Things. M2DC is built on three main pillars: a flexible server architecture that can be easily customised, maintained and updated;advanced management strategies and system efficiency enhancements (SEE);well-defined interfaces to surrounding software data centre ecosystem. © 2016 IEEE.

关键词： Internet of things

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