We present a novel approach that assists the task of porting code to an embedded platform. Our tool automatically identifies code segments in the input program that can be replaced with optimized kernels from a platfo...
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ISBN:
(纸本)9781509030774
We present a novel approach that assists the task of porting code to an embedded platform. Our tool automatically identifies code segments in the input program that can be replaced with optimized kernels from a platform-dependent library. Using a C-function as a model that describes the computational kernel, the tool identifies equivalent code regardless of syntactic and computational variations. For a case study using the Texas Instruments C66x DSP library, our approach identified code replacement opportunities that resulted in runtime performance speedups of up to 2.2x.
Design and development of hard Real-Time (RT) embeddedsystems present several crucial requirements regarding criticality and timeliness of these systems. Formal methods have been presented as a promising alternative ...
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Reconfigurable architectures become more popular now general purpose compute performance does not increase as rapidly as before. Field programmable gate arrays are slowly moving into the direction of Coarse Grain Reco...
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ISBN:
(纸本)9781509030774
Reconfigurable architectures become more popular now general purpose compute performance does not increase as rapidly as before. Field programmable gate arrays are slowly moving into the direction of Coarse Grain Reconfigurable architectures (CGRA) by adding DSP and other coarse grained IP blocks, general purpose processors become more heterogeneous and include sub-word parallelism and even some reconfigurable logic. In the past 25 years, several CGRAs have been published. In this paper an overview and classification of these architectures is presented. This work also provides a clear definition of CGRAs and identifies topics for future research which are key to unlock the full potential of CGRAs.
Typically, state-of-the-art approaches in system synthesis do not consider the trend in embeddedsystems design towards systems-of-systems where optimized subsystems exist from previous projects or as 3 rd party IP. ...
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ISBN:
(纸本)9781509030774
Typically, state-of-the-art approaches in system synthesis do not consider the trend in embeddedsystems design towards systems-of-systems where optimized subsystems exist from previous projects or as 3 rd party IP. In this paper, we propose a novel top-down system synthesis approach with additional support for the composition of subsystems that is based on the use of hierarchical mapping edges and a list-based scheduling algorithm using distributed priority queues. The proposed method not only enables composition of existing subsystems, but experimental results also show a significant reduction of the design space while maintaining a good quality of the implemented systems. Especially for large network-on-chip systems (NoC), our approach outperforms an existing top-down methodology in solving time by nearly 50% and in average quality by 11%.
The engineering of cyber physical systems requires holistic simulation perspectives. To cope with the complexity of these systems, we aim to provide a simulation methodology that is efficient regarding model complexit...
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A hybrid approach for mapping applications represented as Directed Acyclic Graphs (DAGs) is introduced in this work. It combines the Benders decomposition principle, which integrates Integer Linear and Constraint Prog...
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ISBN:
(纸本)9781509030774
A hybrid approach for mapping applications represented as Directed Acyclic Graphs (DAGs) is introduced in this work. It combines the Benders decomposition principle, which integrates Integer Linear and Constraint Programming (ILP and CP) methods, with a pure ILP model to find optimal solutions. The cuts that are generated during the iterative Benders solution process are later exploited by the ILP solver to prune the remaining search space. The proposed model succeeds to provide the optimal solution in cases where either method alone fails to do so, while it also reduces the total solution time.
The complexity of modern embeddedsystems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of the field of system-level design and synthesis....
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ISBN:
(纸本)9781509030774
The complexity of modern embeddedsystems, which are increasingly based on heterogeneous multiprocessor system-on-chip (MPSoC) architectures, has led to the emergence of the field of system-level design and synthesis. To cope with the design complexity, system-level design and synthesis methods aim at raising the abstraction level of the design process. Key enablers to this end are, for example, the use of architectural platforms to facilitate re-use of IP components and the notion of high-level system modelling and simulation. The latter allows for capturing the behavior of platform components and their interactions at a high level of abstraction. As such, these high-level models minimize the modeling effort and are optimized for execution speed, and can therefore be applied during the very early design stages to perform design space exploration (DSE). Such early DSE is of paramount importance as early design choices heavily influence the success or failure of the final product. In this talk, I will provide an overview of the recent advances in our research on system-level MPSoC DSE, such as scenario-based DSE for design-time as well as run-time application mapping, and will present some future challenges that need to be addressed in this domain.
Multi-view modeling is a system design methodology where different facets of a system are modeled each with a separate model, called view. The problem of view consistency then arises, namely, does there exist a system...
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ISBN:
(纸本)9781509030774
Multi-view modeling is a system design methodology where different facets of a system are modeled each with a separate model, called view. The problem of view consistency then arises, namely, does there exist a system which could generate a given set of views? In previous work this problem has been studied for the case of discrete systems such as finite automata over finite words, on one hand, and finite automata over infinite words, on the other hand. In this work we study the problem for the case of mixed automata, which accept both finite and infinite words, and the corresponding infinitary regular languages. This model is particularly useful in the multi-view modeling setting, where views are obtained as projections of the system, and where these projections may turn an infinite behavior into a finite one.
The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on programmable logic devices and embedded proces...
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ISBN:
(纸本)9781509030774
The growing complexity of digital signal processing applications make a compelling case the use of high-level design and synthesis methodologies for the implementation on programmable logic devices and embedded processors. Past research has shown that, for complex systems, raising the level of abstraction of design stages does not necessarily come at a penalty in terms of performance or resource requirements. Dataflow programs provide behavioral descriptions capable of expressing both sequential and parallel components of application algorithms and enable natural design abstractions, modularity, and portability. In this paper, an open source tool, implementing dataflow programs onto embedded heterogeneous platforms by means of high-level synthesis, software synthesis and interface synthesis is presented Experimental design results demonstrate the capability and the effectiveness of the tool for implementing a wide range of applications when combined with Vivado HLS.
The memory subsystem of modern multi-core architectures is becoming more and more complex with the increasing number of cores integrated in a single computer system. This complexity leads to profiling needs to let sof...
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ISBN:
(纸本)9781509030774
The memory subsystem of modern multi-core architectures is becoming more and more complex with the increasing number of cores integrated in a single computer system. This complexity leads to profiling needs to let software developers understand how programs use the memory subsystem. Modern processors come with hardware profiling features to help building tools for these profiling needs. Regarding memory profiling, many processors provide means to monitor memory traffic and to sample read and write memory accesses. Unfortunately, these hardware profiling mechanisms are often very complex to use and are specific to each micro-architecture. In this work, we present numap, a library dedicated to the profiling of the memory sub-system of modern multi-core architectures. numap is portable across many micro-architectures and comes with a clean application programming interface allowing to easily build profiling tools on top of it.
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