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17th international Scientific conference on Parallel Computational Technologies, PCT 2023

17th International Scientific Conference on Parallel Computa...

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17th international Scientific conference on Parallel Computational Technologies, PCT 2023

ISBN: (纸本)9783031388637

The proceedings contain 25 papers. The special focus in this conference is on Parallel Computational Technologies. The topics include: On a Template Programming Approach for Shared Memory Parallel architectures with Applications to the Fully Implicit Stokes Solver;parallel Computing in the Tikhonov Regularization Method for Solving the Inverse Problem of Chemical Kinetics;parallel Implementation of the Time-Reversal Mirror Method for Retrieving the Position and Type of a Seismic Source from Observational Data;parallel Implementation of Fast Algorithms in the Vortex Particle Method;Implementation of an Asymptotically Compact Algorithm for GPU simulation of an Acoustic Equation;quantum-Chemical simulation of High-Energy Azoxy Compounds;parallel Algorithms for simulation of the Suspension Transport in Coastal systems Based on the Explicit-Implicit and Splitting Schemes;parallel Numerical Implementation of Three-Dimensional Mathematical Models of Hydrodynamics Taking into Account Vertical Turbulent Exchange;comparison of Two Methods for modeling the Dynamics of Gas Flows in a Protoplanetary Disk;parallel Data Preprocessing Library for Neural Network Training;computer modeling of Metal Nanoclusters and Substrate Interaction at Mesoscopic Level;supercomputer simulation of Plasma Flow in the Diamagnetic Mode of Open Magnetic systems;computer simulation of the Three-Dimensional Synthesis of Phase Images of Nanometer Scale Objects;a Parallel Algorithm for a Two-Phase Gas-Solid-Particle Model with Chemical Reactions and Laser Radiation;MPI-Based Computational Algorithm for modeling a Cylindrical Catalyst Grain During Oxidative Regeneration;research of the Influence of the Thermal State of an Air-Intake Model on In-Flight Icing Conditions;An Efficient LRnLA Algorithm and Data Structure for Manycore and Multicore computers with Hierarchical Cache;Implementation of a Fuzzy Inference Method with Nonsingleton Fuzzification Based on CUDA and GPGPU Technologies;solving the Three-Dim

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RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight Security Enforcement 21st

RT-LIFE: Portable RISC-V Interface for Real-Time Lightweight...

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21st international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Spang, Christoph Meisel, Florian Koch, Andreas Tech Univ Darmstadt Embedded Syst & Applicat Grp Darmstadt Germany

ISBN: (纸本)9783031045806;9783031045790

With the ever-expanding attack surface of low-cost processors in IoT applications, the interest in lightweight hardware support for improving their security is growing. While industry has already adopted mostly static low-overhead mitigation approaches against code-injection attacks, the race against code-reuse attacks is not yet over. One commonly proposed measure against code-reuse attacks aims to enforce runtime-dynamic integrity. In contrast to runtime-dynamic remote attestation, which is limited by its periodic attestation interval (possibly hours or weeks), runtime-dynamic integrity enforcement performs runtime-integrity checking in parallel to the actual execution. This allows very short attack response times, ideally stopping all evil instructions in flight from actually taking effect. To guarantee a prevention-in-time, one requirement is a low latency trace of uncommitted instructions. This typically would require a deep and core-specific integration. As an abstraction layer, we present our highly portable Real-Time Lightweight Integrity enForcement intErface (RT-LIFE), which is optimized to provide the core's state (uncommitted instructions) to an arbitrary runtime-dynamic low-latency Security Enforcement Unit (SecEU) as early as possible, while minimizing the interface's area and clock frequency penalties. We demonstrate RT-LIFE for six very different RISC-V cores together with our initial control-flow-integrity-enforcing SecEU DExIE, discuss the hardware architecture and its timing in detail, and finally provide an open-source release of RT-LIFE.

关键词： Hardware security Security monitoring Portable uncommitted instruction tracing Runtime-dynamic integrity Real-time IoT RISC-V Attack prevention Code-reuse attacks Open-source

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Stability Analysis for Frequency Tunable Bandpass Delta-Sigma ADC architectures 19

Stability Analysis for Frequency Tunable Bandpass Delta-Sigm...

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19th international conference on Synthesis, modeling, Analysis and simulation Methods, and Applications to Circuit Design, SMACD 2023

作者： Flemming, Jesko Wicht, Bernhard Witte, Pascal Department of Integrated Circuits and Embedded Systems University of Applied Sciences and Arts Hanover Germany Institute of Microelectronic Systems Leibniz Universität Hannover Hanover Germany Laboratory of Nano and Quantum Engineering Leibniz Universität Hannover Hanover Germany

ISBN: (纸本)9798350332650

This paper presents bandpass delta-sigma modulator (BP-Δ∑M) structures, which are specifically suited for frequency tuning. The structures are identified through stability analyses and comparisons between chain of resonators feedforward (CRFF) and chain of resonators feedback (CRFB) delta-sigma modulator (Δ∑M) configurations. Frequency tuning is predominantly achieved through altering the resonator coefficients. Therefore, the paper guides designers though the analysis process for identifying suitable tunable BP-Δ∑M structures. When moderately changing the resonators the structures perform almost identical to a non-tunable modulator optimized for the same frequency. For large frequency shifts, the out-of-band gain (OOBG) of the signal transfer function (STF) and noise transfer function (NTF) in the CRFF structure, drastically increases and the control loop becomes unstable. It is shown how utilizing CRFB structures is advantageous for frequency tuning and that the OOBG in CRFF structures can be compensated through a unity STF (USTF) Δ∑M structure. © 2023 IEEE.

关键词： Resonators

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Lightweight design and deployment of object detection model for low-light scenes 4

Lightweight design and deployment of object detection model ...

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4th international conference on computer Vision, Application, and Algorithm, CVAA 2024

作者： Sun, Kangjian Huo, Ju Jiang, Xiaona Gao, Yichao Cai, Chen School of Electrical Engineering and Automation Harbin Institute of Technology Harbin China National Key Laboratory of Modeling and Simulation for Complex Systems Harbin China China FAW Corporation Limited Changchun China College of Design and Engineering National University of Singapore Singapore Signal and Communication Research Institute China Academy of Railway Sciences Beijing China

ISBN: (数字)9781510687622

ISBN: (纸本)9781510687615

Low-light scenes are common in fields such as autonomous driving, which tests the robustness of intelligent systems. This paper tests the performance of object detection in low-light scenes based on the YOLOv8n model. In order to solve the constraint of limited computing power of embedded devices, the YOLOv8n model is adjusted through model pruning and knowledge distillation. The complexity of the model is reduced through these lightweight operations. While ensuring the detection performance as much as possible, the multiply-accumulate operations (MACs) and parameters of the model decreased by about 40% and 27% respectively. The proposed model is evaluated on the Exclusively Dark (ExDARK) dataset and achieves a mean average precision (mAP) value of 0.672. In addition, the proposed model is migrated to the embedded platform NVIDIA Jetson Xavier NX. The deployment process is optimized by multi-process scheduling and multi-thread scheduling. Experiments are also conducted on real data, and the results show that the proposed model can provide a feasible solution for vision-based nighttime autonomous driving. © 2025 SPIE.

关键词： Object detection Deep learning Image processing

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ELAION: ML-Based System for Olive Classification with Edge Devices 23rd

ELAION: ML-Based System for Olive Classification with Edge D...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Theodoropoulos, Dimitris Blazakis, Konstantinos Pnevmatikatos, Dionisios Kalaitzis, Panagiotis Telecommunication Systems Institute Technical University of Crete Chania Greece Institute of Communication and Computation Systems National Technical University of Athens Athens Greece Mediterranean Agronomic Institute of Chania Chania Greece

ISBN: (纸本)9783031460760

Discrimination of morphological characteristics for olive fruits is widely used to quickly classify their cultivar. This process is usually based on visual observations, which require experience and often appear to be very subjective, inconsistent and inaccurate. Towards automating and providing an error-free procedure for olive fruit classification, this work presents ELAION, an end-to-end system for olive cultivar identification using edge devices, such as smartphones and tablets. An application utilizes the device’s camera to send olive images to a back-end server for feature extraction. Results are relayed back to the application, which identifies the originally depicted olive cultivar using pre-trained machine learning models. As a result, ELAION greatly reduces the time and errors on olive fruit identification with on-site results, thus paving the way for becoming an on-site key-tool for olive growers, breeders, and scientists. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Machine learning

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Fault Detection Mechanisms for COTS FPGA systems Used in Low Earth Orbit 23rd

Fault Detection Mechanisms for COTS FPGA Systems Used in Low...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Oberschulte, Tim Marten, Jakob Blume, Holger Institute of Microelectronic Systems Leibniz University Hannover Appelstraße 4 Hannover30167 Germany

ISBN: (纸本)9783031460760

Field-programmable gate array (FPGAs) in space applications come with the drawback of radiation effects, which inevitably will occur in devices of small process size. This also applies to the electronics of the Bose Einstein Condensate and Cold Atom Laboratory (BECCAL) apparatus, which will operate on the international Space Station (ISS) for several years. A total of more than 100 FPGAs distributed throughout the setup will be used for high-precision control of specialized sensors and actuators at nanosecond scale. On ISS, radiation effects must be taken into account, the functionality of the electronics must be monitored, and errors must be handled properly. Due to the large number of devices in BECCAL, commercial off-the-shelf (COTS) FPGAs are used, which are not radiation hardened. This paper describes the methods and measures used to mitigate the effects of radiation in an application specific COTS-FPGA-based communication network. Based on the firmware for a central communication network switch in BECCAL the steps are described to integrate redundancy into the design while optimizing the firmware to stay within the FPGA’s resource constraints. A redundant integrity checker module is developed that can notify preceding network devices of data and configuration bit errors. The firmware is validated and evaluated by injecting faults into data and configuration registers in simulation and real hardware. In the end, the FPGA resource usage of the firmware is reduced by more than half, enabling the use of dual modular redundancy (DMR) for the switching fabric. Together with the triple modular redundancy (TMR) protected integrity checker, this combination completely prevents silent data corruptions in the design as shown in simulation and by injecting faults into hardware using the Intel Fault Injection FPGA IP Core while staying within the resource limitation of a COTS FPGA. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Space applications

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Atalanta: Open-Source RISC-V Microcontroller for Rust-Based Hard Real-Time systems 37th

Atalanta: Open-Source RISC-V Microcontroller for Rust-Based ...

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37th international conference on Architecture of Computing systems (ARCS)

作者： Nurmi, Antti Lindgren, Per Kalache, Abdesattar Lunnikivi, Henri Hamalainen, Timo D. Tampere Univ Tampere Finland Lulea Univ Technol Lulea Sweden

ISBN: (纸本)9783031661457;9783031661464

Real-time systems are a segment of embedded systems that have remained dominated by proprietary hardware architectures, despite the continuing growth of the open-source RISC-V instruction set architecture (ISA). The introduction of core-local interrupt controller (CLIC) extensions to the RISC-V architecture presents a promising opportunity to bridge the technological gap with ARM in low-latency interrupt handling. Regarding software, the real-time interrupt-driven concurrency (RTIC) framework enables ever lighter hard real-time systems with formal compile-time guarantees for memory safety, response time and overall schedulability. In this publication we adapt Ibex, a small, open-source RISC-V processor for CLIC support and present Atalanta, a lightweight microcontroller designed around the RTIC framework. Atalanta implements a localized memory architecture that enables low-latency context switching together with a large number of supported interrupt inputs and levels provided by the CLIC specification. We evaluate Atalanta for real-time performance and implementation feasibility through simulation-based measurements and FPGA prototyping, respectively. We are able to demonstrate an interrupt latency of 5 cycles with minimal jitter and a context switch latency of 21 cycles, placing it competitively against current state-of-the-art solutions. Furthermore, we implement an FPGA prototype for the Xilinx PYNQ-Z1 and VCU118 boards, targeting a frequency of 45 MHz. We publish the sources and implementation scripts of Atalanta under a permissive opensource license.

关键词： RISC-V RTIC CLIC FPGA

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On-Chip Memory Access Reduction for Energy-Efficient Dilated Convolution Processing 23rd

On-Chip Memory Access Reduction for Energy-Efficient Dilated...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Friedrich, Simon Nalapat, Thomas Wittig, Robert Matúš, Emil Fettweis, Gerhard Vodafone Chair Mobile Communications Systems Technical University of Dresden Dresden Germany

ISBN: (纸本)9783031460760

Dilated convolutions have recently become increasingly popular in deep neural networks. However, the inference of these operations on hardware accelerators is not mature enough to reach the efficiency of standard convolutions. Therefore, we extended a dedicated accelerator for dilated convolutions to reduce the number of energy-intensive accesses to the on-chip memory. We achieve this by applying the principle of feature map decomposition to an output-stationary compute array with a strided feature loading. Our solution shows a 50% reduction in memory accesses for an unpadded 3 × 3 kernel and a dilation rate of 9 compared to a recently proposed dilated convolution accelerator. We also support flexible parameter selection for kernel sizes and dilation rates to meet the requirements of modern neural networks. The energy consumption of the additional hardware modules is less than the savings achieved by the reduced memory accesses. This results in a relative energy saving by a factor of 4.77 for dilated convolutions with unpadded 3 × 3 kernels. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Convolution

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NTHPC: Embracing Near-Threshold Operation for High Performance Multi-core systems 23rd

NTHPC: Embracing Near-Threshold Operation for High Performan...

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23rd international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2023

作者： Chakraborty, Shounak Safarpour, Mehdi Silvén, Olli Norwegian University of Science and Technology Trondheim Norway Center for Machine Vision and Signal Analysis University of Oulu Oulu Finland

ISBN: (纸本)9783031460760

System-on-Chip (SoC) manufacturers use Core Level Redundancy (CLR) scheme to cope with fabrication defects. By providing redundancy with extra cores and logic blocks, CLR ensures delivering performance even if a small number of the functional units are defective. CLR even enables selling lower end products if more cores have failed than needed by the most demanding applications. In the current contribution the mechanisms built for CLR are used to increase throughput while complying with the Thermal Design Power (TDP) constraints. We propose NTHPC, that utilizes the designed redundancy support to improve system performance without violating thermal limits. This is done by operating the logic at a voltage close to the threshold voltage of the transistors. Our study using an Intel Xeon multiprocessor shows that Near Threshold Computing (NTC) with CLR mechanisms for thermal controls enabled up to 10.8% average throughput improvement in comparison to plain power gating. © The Author(s), under exclusive license to Springer Nature Switzerland AG 2023.

关键词： Redundancy

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Conservative Design with High-Performance COTS architectures - Beyond Traditional Approaches 29

Conservative Design with High-Performance COTS Architectures...

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29th IEEE international conference on Emerging Technologies and Factory Automation, ETFA 2024

作者： Hapka, Robin Ernst, Rolf Institute of Computer and Network Engineering Tu Braunschweig Germany

ISBN: (纸本)9798350361230

Safety-critical industrial systems are subject to many stringent requirements, including non-functional design constraints that are essential for robustness, reliability, and safety. System timing is often treated as an afterthought, even though data age, race conditions, or missed deadlines can affect functional safety. This challenge has been addressed in real-time system design, but the situation has worsened in recent system designs. Many applications require high performance to achieve behavioral safety goals, i.e., safety of intended functionality, using complex heterogeneous architectures with multi-level memory, interconnected chiplets, and accelerators based on the latest technologies. Machine learning applications in factory automation, robotics, and autonomous systems are important examples. The timing of such architectures is heavily influenced by the physical effects of temperature control and chip variations, including aging, leading to even more complex chip-specific software execution timing. The paper shows that identical chips differ in their timing behavior, and that most of the timing variation of a single chip can be effectively modeled using additive white Gaussian noise. We explain how such timing behavior can be exploited in high-assurance design for safety and reliability, following established reliability analysis, test, and redundancy techniques. © 2024 IEEE.

关键词： Reliability analysis

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