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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

共 2831 条记录，以下是91-100 订阅

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An Application-Specific Network-on-Chip for Control architectures in RF Transceivers

An Application-Specific Network-on-Chip for Control Architec...

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Brandstaetter, Siegfried Huemer, Mario DMCE GmbH & Co KG Freistadter Str 400 A-4040 Linz Austria Klagenfurt Univ A-9020 Klagenfurt Austria

ISBN: (纸本)9781467322973;9781467322966

This paper focuses on the design of an on-chip communication system for control architectures used in RF (Radio Frequency) transceivers. Continuous developments and enhancements of RF transceivers, especially of smart transceivers supporting multi-mode standards, led to new and complex SoC (System-on-Chip) designs. These designs are defined by a distributed controlling concept using several processing modules which are connected over an advanced communication system. Based on the requirements and restrictions of this communication system an application-specific NoC (Network-on-Chip) is presented and analyzed in this work.

关键词： Transceivers Control Architecture radiofrequency network-on-chip ARCHITECTURE COMMUNICATION systems system-on-chip Communication Research

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Integrated model-driven design-space exploration for embedded systems

Integrated model-driven design-space exploration for embedde...

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2011 11th international conference on embedded computer systems: architectures, modeling and simulation, IC-SAMOS 2011

作者： Trčka, Nikola Hendriks, Martijn Basten, Twan Geilen, Marc Somers, Lou Electrical Engineering Department Eindhoven University of Technology Netherlands Department of Mathematics and Computer Science Eindhoven University of Technology Netherlands Computer Science Department Radboud University Nijmegen Netherlands Embedded Systems Institute Netherlands Océ Technologies Netherlands

ISBN: (纸本)9781457708008

embedded systems and their design trajectories are becoming increasingly complex, and there is a growing demand for performance, reliability, energy efficiency and low cost. To cope with these challenges, decision making early in the development trajectory needs to be supported by appropriate modeling and analysis. To achieve this support, we need to find the modeling abstractions that allow extensive design-space exploration, tune these modeling abstractions towards the users, and integrate support for different types of modeling and analysis. © 2011 IEEE.

关键词： embedded systems

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A Lightweight Infrastructure for the Dynamic Creation and Configuration of Virtual Platforms 15

A Lightweight Infrastructure for the Dynamic Creation and Co...

引用

international conference on embedded computer systems architectures modeling and simulation

作者： Sauer, Christian Loeb, Hans-Peter Cadence Design Syst Munich Germany

ISBN: (纸本)9781467373111

Virtual prototypes leverage SystemC/TLM for simulating programmable platforms comprising 100s of modules. Their efficient creation and configuration is vital for acceptable turnaround times, e.g., during performance exploration or software development. Therefore, our lightweight infrastructure provides a factory creating designs from abstract descriptions of module instances, properties, and connections. Modules mark properties as creation or runtime parameters. The resulting generic design descriptions are usable by non-experts and enable front-ends. The infrastructure is a small C++ library that can be combined with existing SystemC/TLM models and simulation kernels. An industrial case study of a complex multiprocessor SoC shows a distinct productivity gain.

关键词： INFRASTRUCTURE Lightweight configurations creation Platform Virtual Software design computer software simulating

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Efficient Computing in Cyber-Physical systems

Efficient Computing in Cyber-Physical Systems

引用

international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Marwedel, Peter Engel, Michael TU Dortmund D-44221 Dortmund Germany

ISBN: (纸本)9781467322973;9781467322966

Computing in cyber-physical systems has to be efficient in terms of a number of objectives. In particular, computing has to be execution-time and energy efficient. In this paper, we will consider optimization techniques aiming at efficiency in terms of these two objectives. In the first part, we will consider techniques for the integration of compilers and worst-case execution time (WCET) estimation. We will demonstrate, how such integration opens the door to WCET-reduction algorithms. For example, an algorithm for WCET-aware compilation reduces the WCET for an automotive application by more than 50% by exploiting scratch pad memories (SPMs). In the second part, we will demonstrate techniques for improving the energy efficiency of cyber-physical systems, in particular the use of SPMs. In the third part, we demonstrate how the optimization for multiple objectives taken into account. This paper provides an overview of work performed at the Chair for embedded systems of TU Dortmund and the Informatik Centrum Dortmund, Germany(1).

关键词： Cyber-physical systems Energy efficiency execution time DNA Integration integration compilers embedded systems seat DOOR Notepads Demonstrate

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A Parameterized Dataflow Language Extension for embedded Streaming systems

A Parameterized Dataflow Language Extension for Embedded Str...

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international conference on embedded computer systems - architectures, modeling and simulation

作者： Lin, Yuan Choi, Yoonseo Mahlke, Scott Mudge, Trevor Chakrabarti, Chaitali Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA Arizona State Univ Dept Elect Engn Tempe AZ 85287 USA

ISBN: (纸本)9781424419852

Many embedded DSP systems can be characterized as streaming applications. Imperative programming languages are ill suited for describing the concurrency within these DSP systems. SPEX is a language extension designed to let the programmers describe the inherent parallelism within DSP systems. In this paper, we highlight SPEX's language features for describing the streaming computation and communication patterns of DSP systems, and allowing the compiler to generate efficient code for embedded DSP architectures. This language extension is based on the parameterized dataflow computation model, with modifications to better describe DSP systems' complex streaming patterns. SPEX is applied as an extension onto the C++ programming language. It consists of a set of language constructs for describing the semantics of parameterized dataflow computations, and a set of language restrictions for helping the embedded compilation process. In this paper, the W-CDMA wireless protocol is used us our case study.

关键词： Code division multiple access

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A Process-Based Reconfigurable SystemC Module for simulation Speedup

A Process-Based Reconfigurable SystemC Module for Simulation...

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13th international conference on embedded computer systems - architectures, modeling and simulation (IC-SAMOS)

作者： Sotiriou-Xanthopoulos, Efstathios Siozios, Kostas Economakos, George Soudris, Dimitrios Natl Tech Univ Athens Sch Elect & Comp Engn Athens 15780 Greece

ISBN: (纸本)9781479901036

As Multi-Processor systems-on-Chip (MPSoC) architectures become more and more complex, Design Space Exploration (DSE) becomes the only viable solution for finding the pareto-optimal designs. To evaluate each solution with real dataset, DSE has to simulate the design under test, which is modeled as a Virtual Platform usually written in SystemC. However, the simulation is a very slow task which includes non-productive time periods like system initialization, while the platform re-compilation also imposes a significant overhead. In this paper, a Process-based Reconfigurable Module is used in order to bypass the non-productive simulation parts, thus accelerating the simulation. The effectiveness of the proposed methodology is proved with a series of computationally intensive multimedia applications, where the simulation time improvements reach 34% on average.

关键词： C++ language integrated circuit design multimedia communication multiprocessing systems system-on-chip virtual reality

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Flexibility inlining into arithmetic data-paths exploiting a regular interconnection scheme

Flexibility inlining into arithmetic data-paths exploiting a...

引用

international conference on embedded computer systems - architectures, modeling and simulation

作者： Xydis, Sotiris Economakos, George Pekmestzi, Kiamal Natl Tech Univ Athens Sch Elect & Comp Engn Iroon Polytexneiou 9 GR-15780 Athens Greece

ISBN: (纸本)9781424410583

This paper presents a design technique for coarse grained reconfigurable cores targeting mostly DSP applications. The proposed technique inlines flexibility into custom Carry-Save-Arithmetic (CSA) datapaths exploiting a stable and canonical interconnection scheme. The canonical interconnection is revealed by a uniformity transformation imposed on the basic architectures of CSA multipliers and CSA chain-adders/subtractors. The design flow for the implementation of the core is analyzed in detail, and a novel reconfigurable architecture prototype is presented. The paper concludes with the experimental results showing that our architecture performs an average latency reduction of 32.63%, compared with datapaths of primitive computational resources, with a tolerable overhead in hardware utilization.

关键词： Reconfigurable architectures

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DVFS-Enabled Power-Performance Trade-Off in MPSoC SW Application Mapping 17

DVFS-Enabled Power-Performance Trade-Off in MPSoC SW Applica...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Onnebrink, Gereon Walbroel, Florian Klimt, Jonathan Leupers, Rainer Ascheid, Gerd Murillo, Luis Gabriel Schurmans, Stefan Chen, Xiaotao Harn, YwhPyng Rhein Westfal TH Aachen Inst Commun Technol & Embedded Syst Aachen Germany Silexica GmbH Cologne Germany Huawei Technol Co Ltd Bridgewater NJ USA

ISBN: (纸本)9781538634370

Heterogeneous MPSoCs are seen as the solution to tackle performance and power demands in the embedded domain. Their HW and SW complexity necessitates an automatic approach to find the most efficient task-to-processor mapping of parallel applications. Tight power budgets require efficient task mapping, and optimally setting the voltage and frequency of each processor. This paper proposes a novel heuristic that minimises the average power consumption, while meeting performance constraints. Integrated into an industrial SW mapping framework, the applicability is validated using three different case studies and representative benchmarks. Moreover, the power-performance trade-off is discussed. A comparison with the optimal solution complements the evaluation, revealing a loss of 19% by the heuristic, but 700x faster execution.

关键词： Power demand Task analysis Optimization Benchmark testing Switches Leakage currents Clocks Benchmark testing Power demand task analysis Timing devices Switches leakage currents Leakage currents power budget MAPPING(MATHEMATICAL) tradeoffs Heuristics

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RACOS: Transparent Access and Virtualization of Reconfigurable Hardware Accelerators 17

RACOS: Transparent Access and Virtualization of Reconfigurab...

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17th Annual international conference on embedded computer systems - architectures, modeling, and simulation (SAMOS)

作者： Vatsolakis, Charalampos Pnevmatikatos, Dionisios Tech Univ Crete Sch Elect & Comp Engn Khania Greece Fdn Res & Technol Hellas Inst Comp Sci Iraklion Greece

ISBN: (纸本)9781538634370

Crafting accelerators using reconfigurable hardware is a promising way to achieve improved performance and power/energy efficiency. However, deploying reconfigurable accelerators is still cumbersome as it involves overall system integration issues and and runtime reconfigurable resource management. We describe the design and implementation of RACOS, a Reconfigurable ACcelerator OS, that provides a simple and intuitive software interface to load/unload reconfigurable hardware accelerators and perform data I/Os transparently to the user. Multiple partially reconfigurable regions are supported, and each region can host either single- or dual-threaded accelerators, effectively virtualizing the reconfigurable resources. RACOS allows multiple applications to use one or more accelerators each, and schedules accelerators for execution according to four policies: simple and inorder that respect the order of request, and out of order and forced that aim to reduce the number of reconfigurations. We evaluate our proposed system varying the number of instances of an accelerated application and show that, despite its generality, RACOS can achieve both high reconfiguration and data communication throughput, close to the maximum reported in bibliography, with a very small resource cost comparable or better than the current state of the art.

关键词： Hardware Software Field programmable gate arrays Throughput Acceleration Libraries Linux Field programmable gate arrays Accelerators hardware accelerator Linux reconfigurable hardware Throughput computer hardware acceleration Libraries computer software Virtualization configurability systems Integration software interface

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An event-based Network-on-Chip debugging system for FPGA-based MPSoCs 17

An event-based Network-on-Chip debugging system for FPGA-bas...

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17th international conference on embedded computer systems: architectures, modeling, and simulation, SAMOS 2017

作者： Ul Hasan Khan, Habib Rettkowski, Jens Eldafrawy, Mohamed Gohringer, Diana Application-Specific Multi-Core Architectures Group Ruhr-University Bochum Germany German University in Cairo Egypt Chai. of Adaptive Dynamic Systems Technische Universität Dresden Germany

ISBN: (纸本)9781538634370

Nowadays, Multiprocessor systems-on-Chip (MPSoCs) have high computation power due to the parallel processing using multiple processing elements (PEs). However, the communication costs increase with the number of PEs. Networks-on-Chip (NoCs) are the most promising solution for addressing the communication issues. This paper discusses the implementation of a user interactive NoC debugger. The system consists of two main parts;an on-chip hardware debugging system and an off-chip C++based computer application. The data debugging is transaction based and allows fault detection and reliable data analysis such as data logging, utilization report and dataflow visualization. The NoC debugger was implemented on a runtime reconfigurable and adaptive routable NoC and tested with a traffic generation technique. © 2017 IEEE.

关键词： Field programmable gate arrays (FPGA)

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