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检索条件"任意字段=International Conference on Embedded Computer Systems Architectures Modeling and Simulation"

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An accurate energy model for streaming applications mapped on MPSoC platforms

An accurate energy model for streaming applications mapped o...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Jelena Spasic Todor Stefanov Leiden Institute of Advanced Computer Science Leiden University Netherlands

ISBN: (纸本)9781479901043

In this paper, we propose a very accurate energy model for streaming applications modeled as Polyhedral Process Networks (PPN) and mapped onto tile-based MPSoC platforms with distributed memory. The energy model is based on the well-defined properties of the PPN application model. To guarantee the accuracy of the energy model, values of important model parameters are obtained by real measurements. The proposed energy model is applicable to different types of processors and communication infrastructures within an MPSoC platform. The energy model is evaluated on FPGA-based MPSoC platforms against real measurements of energy consumption from the FPGA. The obtained energy estimates are highly accurate with an average error of 4% and a standard deviation of 3%. The average model evaluation time per design point takes 2.5 minutes for considered cases, which is very good given the high accuracy of the model.

关键词： Tiles Program processors Energy consumption Accuracy Ports (computers) Power demand Energy measurement

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Lightweight Resource Estimation Model to Extend Battery Life in Video Playback

Lightweight Resource Estimation Model to Extend Battery Life...

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international conference on embedded computer systems: architectures, modeling and simulation

作者： Tero Rintaluoma Olli Silvén Google Kiviharjunlenkki 1 B 90220 Oulu Finland Department of Computer Science and Engineering P.O.B. 4500 FI-90014 University of Oulu Finland

ISBN: (纸本)9781479901043

Modern mobile computing devices are integrating more and more processing units into a single platform. For this reason separate resource managers are needed to control computing resources efectively and in an energy efficient way. Multimedia signal processing applications, such as a video playback, have huge variations in their resource needs depending on the input sequence characteristics. To improve this situation a resource usage estimation model has been developed and evaluated. By using the model it is possible to estimate the resource needs with less than 10% error marginal on average. A proper exploitation of prior information improves both the user experience and the battery life. On the testing platform already a single step in the dynamic voltage and frequency scaling scheme corresponds to 30 minutes in high definition video playback time. The approach does not require changes to the existing encoders or decoders.

关键词： Lightweight Resource Estimation

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Fast transaction-level dynamic power consumption modelling in priority preemptive wormhole switching networks on chip

Fast transaction-level dynamic power consumption modelling i...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： James Harbin Leandro Soares Indrusiak Real-Time Systems Group Department of Computer Science University of York UK

ISBN: (纸本)9781479901043

This paper specifies an architecture for power consumption modelling integrated within cycle-approximate transaction level modelling for network-on-chip (NoC) simulation. NoC simulations during design validation have traditionally been limited to very short durations, due to the necessity to perform cycle-accurate simulation to represent fully the low level system simulated. Due to the high proportion of overall system power that may be consumed by a busy NoC, high-fidelity NoC power modelling is especially important to accurately assess the effectiveness of link coding and other strategies to reduce NoC power consumption. The paper describes the extension of a cycle-approximate TLM methodology to encompass power modelling in NoCs, considering its operation with real application traffic. The proposed scheme avoids modelling of flit-by-flit progress during non-preemptive periods of packet transmission. The simulation performance and accuracy are contrasted with theoretical models and a flit-by-flit scheme (in which each flow control digit passing along a bus wire is simulated). The power consumption reduction delivered by encoding schemes such as bus-invert coding are considered and compared with analytical models to verify the correct performance of the simulation models.

关键词： Power demand Computational modeling Time-varying systems Time-domain analysis Mathematical model Wires Indexes

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Dataflow computing with Polymorphic Registers

Dataflow computing with Polymorphic Registers

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Cătălin Ciobanu Georgi Gaydadjiev Christian Pilato Donatella Sciuto Department of Computer Science and Engineering Chalmers University of Technology Sweden Dipartimento di Elettronica Informazione e Bioingegneria Politecnico di Milano Italy

ISBN: (纸本)9781479901043

Heterogeneous systems are becoming increasingly popular for data processing. They improve performance of simple kernels applied to large amounts of data. However, sequential data loads may have negative impact. Data parallel solutions such as Polymorphic Register Files (PRFs) can potentially accelerate applications by facilitating high speed, parallel access to performance-critical data. Furthermore, by PRF customization, specific data path features are exposed to the programmer in a very convenient way. PRFs allow additional control over the registers dimensions, and the number of elements which can be simultaneously accessed by computational units. This paper shows how PRFs can be integrated in dataflow computational platforms. In particular, starting from an annotated source code, we present a compiler-based methodology that automatically generates the customized PRFs and the enhanced computational kernels that efficiently exploit them.

关键词： Registers Kernel Field programmable gate arrays Vectors computer architecture Organizations Hardware

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On-demand thread-level fault detection in a concurrent programming environment

On-demand thread-level fault detection in a concurrent progr...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Jian Fu Qiang Yang Raphael Poss Chris R. Jesshope Chunyuan Zhang Universiteit van Amsterdam Amsterdam Noord-Holland NL Informatics Institute University of Amsterdam Amsterdam Netherlands School of Computer National University of Defence Technology Changsha China

ISBN: (纸本)9781479901043

The vulnerability of multi-core processors is increasing due to tighter design margins and greater susceptibility to interference. Moreover, concurrent programming environments are the norm in the exploitation of multi-core systems. In this paper, we present an on-demand thread-level fault detection mechanism for multi-cores. The main contribution is on-demand redundancy, which allows users to set the redundancy scope in the concurrent code. To achieve this we introduce intelligent redundant thread creation and synchronization, which manages concurrency and synchronization between the redundant threads via the master. This framework was implemented in an emulation of a multi-threaded, many-core processor with single, in-order issue cores. It was evaluated by a range of programs in image and signal processing, and encryption. The performance overhead of redundancy is less than 11% for single core execution and is always less than 100% for all scenarios. This efficiency derives from the platform's hardware concurrency management and latency tolerance.

关键词： Redundancy Concurrent computing Message systems Synchronization Instruction sets Programming

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Pulse-length determination techniques in the rectangular single event transient fault model

Pulse-length determination techniques in the rectangular sin...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Alireza Rohani Hans G. Kerkhoff Enrico Costenaro Dan Alexandrescu Testable Design and Test of Integrated Systems Group CTIT University of Twente Enschede The Netherlands iRoC Technologies Grenoble France

ISBN: (纸本)9781479901043

One of the well-known models to represent Single Event Transient phenomenon at the logic-level is the rectangular pulse model. However, the pulse-length in this model has a vital contribution to the accuracy and validity of the rectangular pulse model. The work presented in this paper develops two approaches for determination of the pulse-length of the rectangular pulse model used in Single Event Transient (SET) faults. The first determination approach has been extracted from radiation testing along with transistor-level SET analysis tools. The second determination approach has been elicited from asymptotic analytical behaviour of SETs in 45-nm CMOS process. The results show that applying these two pulse-length determination approaches to the rectangular pulse model will cause the fault injection results converge much faster (up to sixteen times), compared to other conventional approaches.

关键词： Circuit faults Mathematical model Integrated circuit modeling Equations Libraries Logic gates Clocks

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computer systems and Technologies: 14th international conference, CompSysTech 2013 - Proceedings

Computer Systems and Technologies: 14th International Confer...

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14th international conference on computer systems and Technologies, CompSysTech 2013

ISBN: (纸本)9781450320214

The proceedings contain 45 papers. The topics discussed include: automatic information extraction from patient records in Bulgarian language;A QoX model for ETL subsystems: theoretical and industry perspectives;implementation aspects of self-healing functionality in long term evolution (LTE) networks;implementing port security feature using SNMP protocol;computer modeling of the throughput of a crossbar switch by P I-patterns for uniform traffic with variable intensity;loading test of Apache HTTP server by video file and usage measurements of the hardware components;MMSoC: a multi-layer multi-core storage-on-chip design for systems with high integration;optimized multicore architectures for data parallel fast Fourier transform;a program for an automatic PicoBlaze type embedded system generation;performance analysis of MQL drilling using artificial neural network;and noncontact automatic heart rate analysis in visible spectrum by specific face regions.

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Exploiting tightly-coupled cores

Exploiting tightly-coupled cores

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Daniel Bates Alex Bradbury Andreas Koltes Robert Mullins Computer Laboratory University of Cambridge UK

ISBN: (纸本)9781479901043

The individual processors of a chip-multiprocessor traditionally have rigid boundaries. Inter-core communication is only possible via memory and control over a core's resources is localised. Specialisation necessary to meet today's challenging energy targets is typically provided through the provision of a range of processor types and accelerators. An alternative approach is to permit specialisation by tailoring the way a large number of homogeneous cores are used. The approach here is to relax processor boundaries, create a richer mix of inter-core communication mechanisms and provide finer-grain control over, and access to, the resources of each core. We evaluate one such design, called Loki, that aims to support specialisation in software on a homogeneous many-core architecture. We focus on the design of a single 8-core tile, conceived as the building block for a larger many-core system. We explore the tile's ability to support a range of parallelisation opportunities and detail the control and communication mechanisms needed to exploit each core's resources in a flexible manner. Performance and a detailed breakdown of energy usage is provided for a range of benchmarks and configurations.

关键词： Tiles computer architecture Benchmark testing Registers Program processors Clocks

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Parallel implementation of real-time semi-global matching on embedded multi-core architectures

Parallel implementation of real-time semi-global matching on...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Oliver Jakob Arndt Daniel Becker Christian Banz Holger Blume Institute of Microelectronic Systems Leibniz Universität Hannover Hanover Germany Corporate Technology Siemens AG Munich Germany

ISBN: (纸本)9781479901043

embedded real-time algorithms are often realized with dedicated hardware, exhibiting high production costs and low programming flexibility thereafter. For instance, semi-global matching for stereo image processing, including complex data flows, traditionally runs on customized hardware modules. Combining the processing and memory capabilities of multiple individual cores, emerging embedded multi-core technologies address these problems. However, considering concurrency issues (e.g., data races and lock contentions), parallel programming requires experienced programmers and technology-specific techniques (e.g., synchronization libraries) and tools (e.g., parallel profilers), which are often not available on embedded platforms. In this work, we introduce a parallel version of a semi-global matching algorithm and demonstrate within this case study runtime optimizations necessary to meet real-time requirements. We also show structured steps of the applied parallelization workflow, illustrating an efficient migration strategy to multi-core platforms using runtime information (e.g., profiles and hardware counters). Finally, to evaluate the resulting performance characteristics, we compare the runtime behavior of the parallel version running on a Freescale P4080 processor with reference values taken on an Intel i7, a field-programmable logic device, an extended general purpose processor and a GPU.

关键词： Hardware Real-time systems Libraries Runtime Synchronization Multicore processing Software

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Efficient runtime support for embedded MPSoCs

Efficient runtime support for embedded MPSoCs

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Dimitris Theodoropoulos Polyvios Pratikakis Dionisios Pnevmatikatos Computer Architecture and VLSI Systems Laboratory Institute of Computer Science Foundation for Research and Technology-Hellas Crete Greece

ISBN: (纸本)9781479901043

Recently, many software runtime systems have been proposed that allow developers to efficiently map applications to contemporary consumer electronic devices and high-performance academic processing platforms. Most of these runtime systems employ advanced scheduling techniques for automatic task assignment to all available processing elements. However, they focus on a particular environment and architecture, and it is not easy to port them to reconfigurable embedded MPSoCs. As a consequence, in the embedded community, researchers implement hardwired application-specific task schedulers, which can not be used by other embedded MPSoCs. To address this problem, in this paper we propose a lightweight runtime software framework for reconfigurable shared-memory MPSoCs, that integrate a master embedded processor connected to slave cores. Similarly to many of the aforementioned advanced runtime systems, we adopt a task-based programming model that uses simple, pragma-based annotations of the application software, in order to dynamically resolve task dependencies. Our runtime system supports heterogeneity in the hardware resources, and is also low-overhead to account for possible limitations in their processing capabilities and available on-chip memory. To evaluate our proposal, we have prototyped an MPSoC with seven slaves to a Xilinx ML605 FPGA board. We run three micro-benchmarks that achieve a performance speedup of 3.8x, 7x and 5.8x, and energy consumption of 27%, 14% and 18% respectively, compared to a single-core baseline system with no runtime support.

关键词： Runtime Software Hardware Real-time systems Field programmable gate arrays Processor scheduling Programming

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