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A scene-driven modeling reconfigurable hardware-in-loop simulation environment for the verification of an autonomous CPS

A scene-driven modeling reconfigurable hardware-in-loop simu...

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2013 5th international conference on Intelligent Human-Machine systems and Cybernetics, IHMSC 2013

作者： Zhang, Kailong Li, Jiwei Lu, Zhou Luo, Mei Wu, Xiao School of Computer Science and Engineering Northwestern Polytechnical University 710072 Xi'an China Centre of Robot Mines Paristech 75006 Paris France Software Engineering group University of Twente Netherlands Xi'an Institute of High-Tech 710025 Xi'an China

ISBN: (纸本)9780769550114

Cyber-Physical System(CPS) is now a new evolutional morphology of embedded systems. With features of merging computation and physical processes together, the traditional verification and simulation methods have being challenged recently. After analyzed the state-of-art of related research, a new simulation environment is studied according to the characters of a special autonomous cyber-physical system-Unmanned Aerial Vehicle, and designed to be scene-driven, modeling and reconfigurable. In this environment, a novel CPS-in-loop architecture, which can support simulations under different customized scenes, is studied firstly to ensure its opening and flexibility. And as another foundation, some dynamics models of CPS and atmospheric ones of relative sensors are introduced to simulate the motion of CPS and the change of its posture. On the basis above, the reconfigurable scene-driven mechanisms that are Based on hybrid events are mainly excogitated. Then, different scenes can be configured in terms of special verification requirements, and then each scene will be decomposed into a spatio-temporal event sequence and scheduled by a scene executor. With this environment, not only the posture of CPS, but also the autonomy of its behavior can be verified and observed. It will be meaningful for the design of such autonomous CPS. © 2013 IEEE.

关键词： Cyber Physical System

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Gama: A spatially explicit, multi-level, agent-based modeling and simulation platform

Gama: A spatially explicit, multi-level, agent-based modelin...

引用

11th international conference on Practical Applications of Agents and Multi-Agent systems, PAAMS 2013

作者： Drogoul, Alexis Amouroux, Edouard Caillou, Philippe Gaudou, Benoit Grignard, Arnaud Marilleau, Nicolas Taillandier, Patrick Vavasseur, Maroussia Vo, Duc-An Zucker, Jean-Daniel IRD UMI UMMISCO 209 32 av. H. Varagnat 93143 Bondy France

ISBN: (纸本)9783642380723

Agent-based modeling is now widely used to investigate complex systems but still lacks integrated and generic tools to support the representation of features usually associated with real complex systems, namely rich, dynamic and realistic environments or multiple levels of agency. The GAMA platform has been developed to address such issues and allow modelers, thanks to the use of a high-level modeling language, to build, couple and reuse complex models combining various agent architectures, environment representations and levels of abstraction. © 2013 Springer-Verlag Berlin Heidelberg.

关键词： modeling languages

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A scalable FFT processor architecture for OFDM based communication systems

A scalable FFT processor architecture for OFDM based communi...

引用

international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Deepak Revanna Omer Anjum Manuele Cucchi Roberto Airoldi Jari Nurmi Department of Electronics and Communications Engineering Tampere University of Technology Finland

ISBN: (纸本)9781479901043

The modern wireless standards predominantly are based on OFDM communication systems. Various mobile devices in recent times support multiple wireless standards and demand efficient transceiver. Hence, in a communication transceiver the baseband hardware needs to be scalable and efficient across multiple standards. In an OFDM based transceiver, FFT computation is one of the most computationally intensive and power hungry modules. Design of FFT hardware is a challenging task while balancing design parameters such as speed, power, area, flexibility and scalability. The research work in this paper proposes a scalable radix-2 N-point novel FFT processor architecture. The architecture design is based on an approach to balance various specified design parameters to meet the requirements of SDR platforms supporting multiple wireless standards. The FFT processor was designed and prototyped using VHDL on an Altera Stratix V FPGA device 5SGSMD5K2F40C2. The processor operates at a maximum frequency of 200MHz, uses less than 1% of FPGA device resources and meets the performance requirements of multiple wireless standards such as IEEE 802.11a/g, IEEE 802.16e, 3GPP-LTE, DAB and DVB. The proposed architecture outperforms the existing fixed and variable length FFT processors in terms of speed, flexibility and scalability.

关键词： Random access memory computer architecture OFDM Read only memory Clocks Standards Wireless communication

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Semi physical simulation of diesel generator set rotational speed control

Semi physical simulation of diesel generator set rotational ...

引用

2013 international conference on Mechatronic systems and Materials Application, ICMSMA 2013

作者： Peng, Min Engineering Institute Wuhan Yangtze Business University Wuhan 430065 China

ISBN: (纸本)9783037858158

The paper build simulation model of MTU396 diesel generating sets through the SIMULINK, and then using MATLAB real-time workshop (RTW) to transfer the SIMULINK simulation model into a portable embedded c + + code, in the Visual c + + integrated development environment to develop semi physical simulation system of diesel rotational speed control. The method makes full use of the SIMULINK rich, convenient modeling environment, at the same time plays a powerful hardware control function of VC and the advantages of human-computer interface flexible design. This paper introduces the development of semi physical simulation system with the method of specific steps and realization method. © (2013) Trans Tech Publications, Switzerland.

关键词： Simulink

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ECONO: Express coherence notifications for efficient cache coherency in many-core CMPs

ECONO: Express coherence notifications for efficient cache c...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： José L. Abellán Alberto Ros Juan Fernández Manuel E. Acacio Electrical and Computer Engineering Department Boston University Boston MA USA Computer Engineering Department University of Murcia Murcia Spain Intel Laboratories Barcelona Barcelona Spain

ISBN: (纸本)9781479901043

It is commonly stated that a directory-based coherence protocol is the design of choice to provide maximum performance in coherence maintenance for shared-memory many-core CMPs. Nevertheless, new solutions are emerging to achieve acceptable levels of on-chip area overhead and energy consumption to also meet scalability. In this work, we propose the Express COherence NOtification (ECONO) protocol, a coherence protocol aimed at providing high performance with minimal on-chip area and energy consumption for superior scalability. To maintain coherence, ECONO relies on express coherence notifications which are broadcast atomically over a dedicated lightweight and power-efficient on-chip network leveraging state-of-the-art technology. We implement and evaluate ECONO utilizing full-system simulation, a representative set of benchmarks, and compare it against two contemporary coherence protocols: Hammer and Directory. While ECONO achieves slightly better performance than Directory, our proposal does not need to encode sharer sets like in Hammer, saving significant on-chip area and energy even when considering the extra hardware resources required by ECONO. Projections for a 1024-core CMP reveal that, in comparison to one of the most scalable directory-based protocols to date, ECONO entails more than 2× less on-chip storage overhead while keeping with reasonable power dissipation.

关键词： Coherence Protocols Tiles System-on-chip Benchmark testing Proposals Complexity theory

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Simsys: A performance simulation framework 13

Simsys: A performance simulation framework

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2013 4th Workshop on Rapid simulation and Performance Evaluation: Methods and Tools, RAPIDO 2013 - In Conjunction with the 8th Intl. conference on High-Performance and embedded architectures and Compilers, HiPEAC 2013

作者： Noudohouenou, José Palomares, Vincent Jalby, William Wong, David C. Kuck, David J. Beyler, Jean Christophe Exascale Computing Research United Kingdom Intel. Corporation United States

ISBN: (纸本)9781450315395

HW/SW codesign or computer system purchase involves many tradeoffs, including the problem data size, choice of algorithm and compiler, types of HW subsystems used, clock frequencies of each, and number of cores. Simsys is a fast simulation tool set to examine various combinations of these choices, allowing specific HW/SW performance attributions. Simsys's measurement level and approach are keys to this operating speed and attribution. A combination of modular tools forms Simsys's automatic procedure for system simulation and analysis. The paper overviews the tools and validates the proposed approach on 27 loop nest codelets extracted from Numerical Recipes. It also includes the experimental method and an error analysis. Three performance quality metrics are defined and evaluated for two simple codelets, demonstrating several modes of performance failure and the weakness of intuition in detecting them, as well as illustrating how better tools could help lead to better computer systems. Future Simsys plans include model enhancement with more HW details and much more extensive experimentation. © 2013 ACM.

关键词： Quality control

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Energy-aware-task-parallelism for efficient dynamic voltage, and frequency scaling, in CGRAs

Energy-aware-task-parallelism for efficient dynamic voltage,...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Syed. M. A. H. Jafri Muhammad Adeel Tajammul Ahmed Hemani Kolin Paul Juha Plosila Hannu Tenhunen Kungliga Tekniska Hogskolan Stockholm SE Royal Institute of Technology Sweden Turun Yliopisto Turku FI

ISBN: (纸本)9781479901043

Today, coarse grained reconfigurable architectures (CGRAs) host multiple applications, with arbitrary communication and computation patterns. Each application itself is composed of multiple tasks, spatially mapped to different parts of platform. Providing worst-case operating point to all applications leads to excessive energy and power consumption. To cater this problem, dynamic voltage and frequency scaling (DVFS) is a frequently used technique. DVFS allows to scale the voltage and/or frequency of the device, based on runtime constraints. Recent research suggests that the efficiency of DVFS can be significantly enhanced by combining dynamic parallelism with DVFS. The proposed methods exploit the speedup induced by parallelism to allow aggressive frequency and voltage scaling. These techniques, employ greedy algorithm, that blindly parallelizes a task whenever required resources are available. Therefore, it is likely to parallelize a task(s) even if it offers no speedup to the application, thereby undermining the effectiveness of parallelism. As a solution to this problem, we present energy aware task parallelism. Our solution relies on a resource allocation graphs and an autonomous parallelism, voltage, and frequency selection algorithm. Using resource allocation graph, as a guide, the autonomous parallelism, voltage, and frequency selection algorithm parallelizes a task only if its parallel version reduces overall application execution time. simulation results, using representative applications (MPEG4, WLAN), show that our solution promises better resource utilization, compared to greedy algorithm. Synthesis results (using WLAN) confirm a significant reduction in energy (up to 36%), power (up to 28%), and configuration memory requirements (up to 36%), compared to state of the art.

关键词： Parallel processing Resource management Greedy algorithms Runtime computer architecture Wireless LAN Radio spectrum management

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Accelerating GPGPU architecture simulation

Accelerating GPGPU architecture simulation

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2013 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, SIGMETRICS 2013

作者： Yu, Zhibin Eeckhout, Lieven Goswami, Nilanjan Li, Tao John, Lizy K. Jin, Hai Xu, Chengzhong Shenzhen Institute of Advanced Technology Chinese Academy of Sciences China ELIS Department Ghent University Belgium Intelligent Design of Efficient Architectures Lab. University of Florida Gainesville FL United States Department of Electrical and Computer Engineering University of Texas Austin TX United States Service Computing Technologies and System Lab./Cluster and Grid Computing Lab. HUST Wuhan China Department of Electrical and Computer Engineering Wayne State University MI United States

ISBN: (纸本)9781450319003

Recently, graphics processing units (GPUs) have opened up new opportunities for speeding up general-purpose parallel applications due to their massive computational power and up to hundreds of thousands of threads enabled by programming models such as CUDA. However, due to the serial nature of existing micro-architecture simulators, these massively parallel architectures and workloads need to be simulated sequentially. As a result, simulating GPGPU architectures with typical benchmarks and input data sets is extremely time-consuming. This paper addresses the GPGPU architecture simulation challenge by generating miniature, yet representative GPGPU kernels. We first summarize the static characteristics of an existing GPGPU kernel in a profile, and analyze its dynamic behavior using the novel concept of the divergence flow statistics graph (DFSG). We subsequently use a GPGPU kernel synthesizing framework to generate a miniature proxy of the original kernel, which can reduce simulation time significantly. The key idea is to reduce the number of simulated instructions by decreasing per-thread iteration counts of loops. Our experimental results show that our approach can accelerate GPGPU architecture simulation by a factor of 88X on average and up to 589X with an average IPC relative error of 5.6%.

关键词： Graphics processing unit

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A just-in-time modulo scheduling for virtual coarse-grained reconfigurable architectures

A just-in-time modulo scheduling for virtual coarse-grained ...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Ricardo Ferreira Vinicius Duarte Waldir Meireles Monica Pereira Luigi Carro Stephan Wong Universidade Federal de Vicosa Vicosa MG BR Departamento de Informatica Universidade Federal Vicosa Vicosa Brazil DIMAP University Federal Rio Grande do Norte Natal Brazil University Federal do Rio Grande do Sul Porto Alegre Brazil EEMCS Computer Engineering Delft University of Technology Delft Netherlands

ISBN: (纸本)9781479901043

In the past decade, most solutions concerning the mapping of the compute-intensive loop kernels to accelerators have used heuristics and compiler-based strategies. These facts require that most of the decisions be taken at design time, thus precluding efficient solutions that can take run-time information into account. Any success in accelerating such applications greatly depends on two steps, extracting the loops and mapping them into the architecture. This last step is a challenge in itself since it is a NP-complete problem. In this paper, we propose a runtime solution that can provide speed ups of 3 to 6 orders of magnitude for the mapping step when compared to the state-of-the-art at minimal performance degradation, by the combined usage of 3 distinct mechanisms: 1) a simple and efficient modulo scheduling heuristic, 2) a crossbar network, which simplifies the placement and routing, 3) a virtual coarse-grained reconfigurable architecture (CGRA). Additionally, since the CGRA is a virtual layer on top of an FPGA, it is possible to use any off-the-shelf FPGA without the need of special tools or IP solutions. Although the mapping is NP-complete even for crossbar-based CGRAs, experimental results demonstrate a huge reduction in compilation time, as opposed to previous solutions that require seconds to map the applications, our solution requires only microseconds to find near optimal schedules. Besides the speed up, the proposed solution enables the use of just-in-time compilation, hence it is intrinsically adaptive to a changing scenario.

关键词： Registers Routing computer architecture Benchmark testing Complexity theory Acceleration Scheduling

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Parallelizing general histogram application for CUDA architectures

Parallelizing general histogram application for CUDA archite...

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international conference on embedded computer systems: architectures, modeling and simulation (IC-SAMOS)

作者： Ugljesa Milic Isaac Gelado Nikola Puzovic Alex Ramirez Milo Tomasevic Centro Nacional de Supercomputacion Barcelona ES Barcelona Supercomputing Center Centro Nacional de Supercomputacion Barcelona Spain School of Electrical Engineering University of Belgrade Belgrade Serbia

ISBN: (纸本)9781479901043

Histogramming is a tool commonly used in data analysis. Although its serial version is simple to implement, providing an efficient and scalable way to parallelize it can be challenging. This especially holds in case of platforms that contain one or several massively parallel devices like CUDA-capable GPUs due to issues with domain decomposition, use of global memory and similar. In this paper we compare two approaches for implementing general purpose histogramming on GPUs. The first algorithm is based on private copies of bin counters stored in shared memory for each block of threads. The second one uses the Thrust library to sort the input elements and then to search for upper bounds according to bin widths. For both algorithms we analyze how the speedup over the sequential version depends on the size of input collection, number of bins, and the type and distribution of input elements. We also implement overlapping of data transfers between host CPU and CUDA device with kernel execution. For both algorithms we analyze the pros and cons in detail. For example, privatization strategy can be up to 2x faster than sort-search with realistic inputs, but can only support a limited number of bins. On the other hand, sort-search strategy has about 50% higher speedup than privatization when we use characters as input and can support unlimited number of bins. Finally, we perform an exploration to determine the optimal algorithm depending on the characteristics and values of input parameters.

关键词： Instruction sets Graphics processing units Histograms Radiation detectors Privatization Kernel Algorithm design and analysis

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